<s>
There	O
are	O
several	O
ways	O
to	O
organise	O
memories	B-General_Concept
with	O
respect	O
to	O
the	O
way	O
they	O
are	O
connected	O
to	O
the	O
cache	B-General_Concept
:	O
</s>
<s>
The	O
memory	O
is	O
one	O
word	O
wide	O
and	O
connected	O
via	O
a	O
one	O
word	O
wide	O
bus	B-General_Concept
to	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
memory	O
is	O
more	O
than	O
one	O
word	O
wide	O
(	O
usually	O
four	O
words	O
wide	O
)	O
and	O
connected	O
by	O
an	O
equally	O
wide	O
bus	B-General_Concept
to	O
the	O
low	O
level	O
cache	B-General_Concept
(	O
which	O
is	O
also	O
wide	O
)	O
.	O
</s>
<s>
From	O
the	O
cache	B-General_Concept
multiple	O
busses	O
of	O
one	O
word	O
wide	O
go	O
to	O
a	O
MUX	B-Protocol
which	O
selects	O
the	O
correct	O
bus	B-General_Concept
to	O
connect	O
to	O
the	O
high	O
level	O
cache	B-General_Concept
.	O
</s>
<s>
There	O
are	O
several	O
memory	O
banks	O
which	O
are	O
one	O
word	O
wide	O
,	O
and	O
one	O
word	O
wide	O
bus	B-General_Concept
.	O
</s>
<s>
There	O
is	O
some	O
logic	O
in	O
the	O
memory	O
that	O
selects	O
the	O
correct	O
bank	O
to	O
use	O
when	O
the	O
memory	O
gets	O
accessed	O
by	O
the	O
cache	B-General_Concept
.	O
</s>
<s>
Memory	B-General_Concept
interleaving	I-General_Concept
is	O
a	O
way	O
to	O
distribute	O
individual	O
addresses	O
over	O
memory	O
modules	O
.	O
</s>
<s>
With	O
memory	B-General_Concept
interleaving	I-General_Concept
,	O
the	O
low-order	O
k	O
bits	O
of	O
the	O
memory	O
address	O
generally	O
specify	O
the	O
module	O
on	O
several	O
buses	O
.	O
</s>
