<s>
A	O
memory	B-Device
divider	I-Device
is	O
a	O
ratio	O
which	O
is	O
used	O
to	O
determine	O
the	O
operating	O
clock	O
frequency	O
of	O
computer	B-General_Concept
memory	I-General_Concept
in	O
accordance	O
with	O
front	B-Architecture
side	I-Architecture
bus	I-Architecture
(	O
FSB	B-Architecture
)	O
frequency	O
,	O
if	O
the	O
memory	O
system	O
is	O
dependent	O
on	O
FSB	B-Architecture
clock	O
speed	O
.	O
</s>
<s>
Along	O
with	O
memory	B-General_Concept
latency	I-General_Concept
timings	O
,	O
memory	B-Device
dividers	I-Device
are	O
extensively	O
used	O
in	O
overclocking	B-Application
memory	O
subsystems	O
to	O
find	O
stable	O
,	O
working	O
memory	O
states	O
at	O
higher	O
FSB	B-Architecture
frequencies	O
.	O
</s>
<s>
The	O
ratio	O
between	O
DRAM	O
and	O
FSB	B-Architecture
is	O
commonly	O
referred	O
to	O
as	O
"	O
DRAM:FSB	B-Device
ratio	I-Device
"	O
.	O
</s>
<s>
Memory	B-Device
dividers	I-Device
are	O
only	O
applicable	O
to	O
those	O
chipsets	B-Device
in	O
which	O
memory	O
speed	O
is	O
dependent	O
on	O
FSB	B-Architecture
speeds	O
.	O
</s>
<s>
Certain	O
chipsets	B-Device
like	O
nVidia	O
680i	O
have	O
separate	O
memory	O
and	O
FSB	B-Architecture
lanes	O
due	O
to	O
which	O
memory	O
clock	O
and	O
FSB	B-Architecture
clock	O
are	O
asynchronous	O
and	O
memory	B-Device
dividers	I-Device
are	O
not	O
used	O
there	O
.	O
</s>
<s>
Setting	O
memory	O
speeds	O
and	O
overclocking	B-Application
memory	O
systems	O
in	O
such	O
chipsets	B-Device
are	O
different	O
issues	O
which	O
do	O
not	O
use	O
memory	B-Device
dividers	I-Device
.	O
</s>
<s>
This	O
article	O
is	O
only	O
applicable	O
to	O
those	O
chipsets	B-Device
in	O
which	O
the	O
memory	O
clock	O
is	O
dependent	O
on	O
FSB	B-Architecture
clock	O
.	O
</s>
<s>
Memory	B-Device
Dividers	I-Device
allow	O
system	O
memory	O
to	O
run	O
slower	O
than	O
or	O
faster	O
than	O
the	O
actual	O
FSB	B-Architecture
(	O
Front	B-Architecture
Side	I-Architecture
Bus	I-Architecture
)	O
speed	O
.	O
</s>
<s>
Ideally	O
,	O
Front	B-Architecture
Side	I-Architecture
Bus	I-Architecture
and	O
system	O
memory	O
should	O
run	O
at	O
the	O
same	O
clock	O
speed	O
because	O
FSB	B-Architecture
connects	O
system	O
memory	O
to	O
the	O
CPU	O
,	O
but	O
it	O
is	O
sometimes	O
desired	O
to	O
run	O
the	O
FSB	B-Architecture
and	O
system	O
memory	O
at	O
different	O
clock	O
speeds	O
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
run	O
FSB	B-Architecture
and	O
memory	O
clock	O
at	O
different	O
clock	O
speeds	O
,	O
within	O
certain	O
limits	O
of	O
the	O
motherboard	B-Device
and	O
corresponding	O
chipset	B-Device
.	O
</s>
<s>
So	O
,	O
settings	O
termed	O
as	O
Memory	B-Device
Divider	I-Device
or	O
FSB/DRAM	O
settings	O
are	O
available	O
and	O
are	O
expressed	O
in	O
a	O
"	O
ratio	O
"	O
which	O
control	O
the	O
difference	O
in	O
memory	O
clock	O
rate	O
and	O
FSB	B-Architecture
speed	O
.	O
</s>
<s>
Entry	O
Level	O
motherboards	B-Device
usually	O
do	O
not	O
provide	O
memory	B-Device
dividers	I-Device
to	O
be	O
changed	O
and	O
the	O
memory	B-Device
dividers	I-Device
are	O
managed	O
by	O
Memory	B-General_Concept
Controller	I-General_Concept
(	O
if	O
chipset	B-Device
supports	O
memory	B-Device
dividers	I-Device
)	O
.	O
</s>
<s>
High	O
end	O
motherboards	B-Device
meant	O
for	O
overclocking	B-Application
provide	O
facilities	O
to	O
change	O
memory	B-Device
dividers	I-Device
(	O
if	O
chipset	B-Device
supports	O
memory	B-Device
dividers	I-Device
)	O
.	O
</s>
<s>
However	O
,	O
in	O
certain	O
chipsets	B-Device
memory	B-Device
dividers	I-Device
are	O
not	O
used	O
,	O
because	O
in	O
those	O
systems	O
memory	O
speed	O
is	O
independent	O
of	O
FSB	B-Architecture
speed	O
.	O
</s>
<s>
Usually	O
(	O
Memory	B-Device
Divider	I-Device
)	O
×	O
(	O
Front	B-Architecture
Side	I-Architecture
Bus	I-Architecture
Frequency	O
)	O
gives	O
I/O	O
Bus	O
clock	O
of	O
the	O
memory	O
.	O
</s>
<s>
By	O
default	O
,	O
FSB	B-Architecture
speed	O
and	O
memory	O
are	O
usually	O
set	O
to	O
a	O
1:1	O
ratio	O
,	O
meaning	O
that	O
increasing	O
FSB	B-Architecture
speed	O
(	O
by	O
overclocking	B-Application
)	O
increases	O
memory	O
speed	O
by	O
the	O
same	O
amount	O
.	O
</s>
<s>
Normally	O
system	O
memory	O
is	O
not	O
built	O
for	O
overclocking	B-Application
and	O
thus	O
may	O
not	O
be	O
able	O
to	O
take	O
the	O
level	O
of	O
overclocking	B-Application
that	O
the	O
processor	O
or	O
motherboard	B-Device
can	O
achieve	O
.	O
</s>
<s>
The	O
memory	B-Device
divider	I-Device
allows	O
users	O
to	O
mitigate	O
this	O
problem	O
by	O
reducing	O
the	O
speed	O
increase	O
of	O
the	O
memory	O
relative	O
to	O
that	O
of	O
the	O
FSB	B-Architecture
and	O
the	O
processor	O
.	O
</s>
<s>
Suppose	O
a	O
computer	O
system	O
has	O
DDR	O
memory	O
,	O
a	O
Memory	B-Device
Divider	I-Device
of	O
1:1	O
,	O
an	O
FSB	B-Architecture
operating	O
at	O
200MHz	O
and	O
a	O
CPU	O
multiplier	O
of	O
10x	O
.	O
</s>
<s>
Then	O
,	O
the	O
base	O
memory	O
clock	O
will	O
operate	O
at	O
(	O
Memory	B-Device
Divider	I-Device
)	O
×	O
(	O
FSB	B-Architecture
)	O
=	O
1	O
×	O
200	O
=	O
200MHz	O
and	O
the	O
effective	O
memory	O
clock	O
would	O
be	O
400MHz	O
since	O
it	O
is	O
a	O
DDR	O
system	O
(	O
"	O
DDR	O
"	O
stands	O
for	O
Double	O
Data	O
Rate	O
;	O
the	O
effective	O
memory	O
clock	O
speed	O
is	O
double	O
the	O
actual	O
clock	O
speed	O
)	O
.	O
</s>
<s>
Now	O
suppose	O
that	O
we	O
overclock	B-Application
FSB	B-Architecture
to	O
250MHz	O
so	O
that	O
CPU	O
operates	O
at	O
10	O
×	O
250MHz	O
=	O
2.5GHz	O
and	O
memory	O
clock	O
operates	O
at	O
250MHz	O
(	O
Memory	B-Device
Divider	I-Device
×	O
FSB	B-Architecture
)	O
.	O
</s>
<s>
But	O
a	O
modern	O
CPU	O
(	O
having	O
overclocking	B-Application
potential	O
)	O
can	O
work	O
at	O
2.5GHz	O
(	O
even	O
if	O
it	O
is	O
designed	O
to	O
work	O
at	O
2GHz	O
)	O
flawlessly	O
without	O
giving	O
any	O
problem	O
of	O
stability	O
.	O
</s>
<s>
To	O
keep	O
running	O
overclocked	O
CPU	O
at	O
2.5GHz	O
or	O
even	O
at	O
higher	O
speeds	O
(	O
by	O
increasing	O
FSB	B-Architecture
)	O
we	O
need	O
to	O
slow	O
down	O
memory	O
clock	O
so	O
as	O
to	O
achieve	O
a	O
stable	O
system	O
.	O
</s>
<s>
For	O
this	O
if	O
we	O
decrease	O
DRAM:FSB	B-Device
ratio	I-Device
to	O
say	O
4:5	O
then	O
resulting	O
memory	O
clock	O
speed	O
is	O
(	O
4/5	O
)	O
×	O
250MHz	O
=	O
200MHz	O
resulting	O
effective	O
clock	O
speed	O
of	O
400MHz	O
on	O
DDR-400	O
.	O
</s>
