<s>
Memory	B-Architecture
disambiguation	I-Architecture
is	O
a	O
set	O
of	O
techniques	O
employed	O
by	O
high-performance	O
out-of-order	B-General_Concept
execution	I-General_Concept
microprocessors	B-Architecture
that	O
execute	O
memory	O
access	O
instructions	O
(	O
loads	O
and	O
stores	O
)	O
out	O
of	O
program	O
order	O
.	O
</s>
<s>
The	O
mechanisms	O
for	O
performing	O
memory	B-Architecture
disambiguation	I-Architecture
,	O
implemented	O
using	O
digital	O
logic	O
inside	O
the	O
microprocessor	B-Architecture
core	O
,	O
detect	O
true	O
dependencies	O
between	O
memory	O
operations	O
at	O
execution	O
time	O
and	O
allow	O
the	O
processor	O
to	O
recover	O
when	O
a	O
dependence	O
has	O
been	O
violated	O
.	O
</s>
<s>
They	O
also	O
eliminate	O
spurious	O
memory	O
dependencies	O
and	O
allow	O
for	O
greater	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
by	O
allowing	O
safe	O
out-of-order	B-General_Concept
execution	I-General_Concept
of	O
loads	O
and	O
stores	O
.	O
</s>
<s>
When	O
attempting	O
to	O
execute	O
instructions	O
out	O
of	O
order	O
,	O
a	O
microprocessor	B-Architecture
must	O
respect	O
true	O
dependencies	O
between	O
instructions	O
.	O
</s>
<s>
In	O
this	O
example	O
,	O
the	O
add	O
instruction	O
on	O
line	O
2	O
is	O
dependent	O
on	O
the	O
add	O
instruction	O
on	O
line	O
1	O
because	O
the	O
register	B-General_Concept
R1	O
is	O
a	O
source	O
operand	O
of	O
the	O
addition	O
operation	O
on	O
line	O
2	O
.	O
</s>
<s>
In	O
this	O
case	O
,	O
the	O
dependence	O
is	O
static	O
and	O
easily	O
determined	O
by	O
a	O
microprocessor	B-Architecture
,	O
because	O
the	O
sources	O
and	O
destinations	O
are	O
registers	O
.	O
</s>
<s>
The	O
destination	O
register	B-General_Concept
of	O
the	O
add	O
instruction	O
on	O
line	O
1	O
(	O
R1	O
)	O
is	O
part	O
of	O
the	O
instruction	O
encoding	O
,	O
and	O
so	O
can	O
be	O
determined	O
by	O
the	O
microprocessor	B-Architecture
early	O
on	O
,	O
during	O
the	O
decode	O
stage	O
of	O
the	O
pipeline	O
.	O
</s>
<s>
To	O
respect	O
this	O
true	O
dependence	O
,	O
the	O
microprocessor	B-Architecture
's	O
scheduler	O
logic	O
will	O
issue	O
these	O
instructions	O
in	O
the	O
correct	O
order	O
(	O
instruction	O
1	O
first	O
,	O
followed	O
by	O
instruction	O
2	O
)	O
so	O
that	O
the	O
results	O
of	O
1	O
are	O
available	O
when	O
instruction	O
2	O
needs	O
them	O
.	O
</s>
<s>
Such	O
non-static	O
dependencies	O
arise	O
with	O
memory	O
instructions	O
(	O
loads	O
and	O
stores	O
)	O
because	O
the	O
location	O
of	O
the	O
operand	O
may	O
be	O
indirectly	O
specified	O
as	O
a	O
register	B-General_Concept
operand	O
rather	O
than	O
directly	O
specified	O
in	O
the	O
instruction	O
encoding	O
itself	O
.	O
</s>
<s>
The	O
microprocessor	B-Architecture
cannot	O
statically	O
determine	O
,	O
prior	O
to	O
execution	O
,	O
if	O
the	O
memory	O
locations	O
specified	O
in	O
these	O
two	O
instructions	O
are	O
different	O
,	O
or	O
are	O
the	O
same	O
location	O
,	O
because	O
the	O
locations	O
depend	O
on	O
the	O
values	O
in	O
R2	O
and	O
R4	O
.	O
</s>
<s>
Consider	O
the	O
following	O
code	O
snippet	O
,	O
given	O
in	O
MIPS	B-Device
assembly	I-Device
:	O
</s>
<s>
Assume	O
that	O
the	O
scheduling	O
logic	O
will	O
issue	O
an	O
instruction	O
to	O
the	O
execution	O
unit	O
when	O
all	O
of	O
its	O
register	B-General_Concept
operands	O
are	O
ready	O
.	O
</s>
<s>
Similarly	O
,	O
assume	O
that	O
register	B-General_Concept
$26	O
is	O
ready	O
.	O
</s>
<s>
Modern	O
microprocessors	B-Architecture
use	O
the	O
following	O
mechanisms	O
,	O
implemented	O
in	O
hardware	B-Architecture
,	O
to	O
resolve	O
ambiguous	O
dependences	O
and	O
recover	O
when	O
a	O
dependence	O
was	O
violated	O
.	O
</s>
<s>
Values	O
from	O
store	O
instructions	O
are	O
not	O
committed	O
to	O
the	O
memory	O
system	O
(	O
in	O
modern	O
microprocessors	B-Architecture
,	O
CPU	B-General_Concept
cache	I-General_Concept
)	O
when	O
they	O
execute	O
.	O
</s>
<s>
Instead	O
,	O
the	O
store	O
instructions	O
,	O
including	O
the	O
memory	O
address	O
and	O
store	O
data	O
,	O
are	O
buffered	O
in	O
a	O
store	O
queue	B-Application
until	O
they	O
reach	O
the	O
retirement	O
point	O
.	O
</s>
<s>
Additionally	O
,	O
buffering	O
stores	O
until	O
retirement	O
allows	O
processors	O
to	O
speculatively	O
execute	O
store	O
instructions	O
that	O
follow	O
an	O
instruction	O
that	O
may	O
produce	O
an	O
exception	B-General_Concept
(	O
such	O
as	O
a	O
load	O
of	O
a	O
bad	O
address	O
,	O
divide	O
by	O
zero	O
,	O
etc	O
.	O
)	O
</s>
<s>
or	O
a	O
conditional	B-General_Concept
branch	I-General_Concept
instruction	O
whose	O
direction	O
(	O
taken	O
or	O
not	O
taken	O
)	O
is	O
not	O
yet	O
known	O
.	O
</s>
<s>
If	O
the	O
exception-producing	O
instruction	O
has	O
not	O
executed	O
or	O
the	O
branch	O
direction	O
was	O
predicted	O
incorrectly	O
,	O
the	O
processor	O
will	O
have	O
fetched	O
and	O
executed	O
instructions	O
on	O
a	O
"	O
wrong	O
path.	O
"	O
</s>
<s>
These	O
instructions	O
should	O
not	O
have	O
been	O
executed	O
at	O
all	O
;	O
the	O
exception	B-General_Concept
condition	I-General_Concept
should	O
have	O
occurred	O
before	O
any	O
of	O
the	O
speculative	O
instructions	O
executed	O
,	O
or	O
the	O
branch	O
should	O
have	O
gone	O
the	O
other	O
direction	O
and	O
caused	O
different	O
instructions	O
to	O
be	O
fetched	O
and	O
executed	O
.	O
</s>
<s>
The	O
processor	O
must	O
"	O
throw	O
away	O
"	O
any	O
results	O
from	O
the	O
bad-path	O
,	O
speculatively-executed	O
instructions	O
when	O
it	O
discovers	O
the	O
exception	B-General_Concept
or	O
branch	O
misprediction	O
.	O
</s>
<s>
Thus	O
,	O
without	O
store	O
buffering	O
,	O
stores	O
cannot	O
execute	O
until	O
all	O
previous	O
possibly-exception-causing	O
instructions	O
have	O
executed	O
(	O
and	O
not	O
caused	O
an	O
exception	B-General_Concept
)	O
and	O
all	O
previous	O
branch	O
directions	O
are	O
known	O
.	O
</s>
<s>
Forcing	O
stores	O
to	O
wait	O
until	O
branch	O
directions	O
and	O
exceptions	O
are	O
known	O
significantly	O
reduces	O
the	O
out-of-order	O
aggressiveness	O
and	O
limits	O
ILP	O
(	O
Instruction	B-Operating_System
level	I-Operating_System
parallelism	I-Operating_System
)	O
and	O
performance	O
.	O
</s>
<s>
With	O
store	O
buffering	O
,	O
stores	O
can	O
execute	O
ahead	O
of	O
exception-causing	O
or	O
unresolved	O
branch	B-General_Concept
instructions	I-General_Concept
,	O
buffering	O
their	O
data	O
in	O
the	O
store	O
queue	B-Application
but	O
not	O
committing	O
their	O
values	O
until	O
retirement	O
.	O
</s>
<s>
This	O
prevents	O
stores	O
on	O
mispredicted	O
or	O
bad	O
paths	O
from	O
committing	O
their	O
values	O
to	O
the	O
memory	O
system	O
while	O
still	O
offering	O
the	O
increased	O
ILP	O
and	O
performance	O
from	O
full	O
out-of-order	B-General_Concept
execution	I-General_Concept
of	O
stores	O
.	O
</s>
<s>
Consider	O
the	O
following	O
scenario	O
:	O
a	O
store	O
executes	O
and	O
buffers	O
its	O
address	O
and	O
data	O
in	O
the	O
store	O
queue	B-Application
.	O
</s>
<s>
To	O
solve	O
this	O
problem	O
,	O
processors	O
employ	O
a	O
technique	O
called	O
store-to-load	O
forwarding	O
using	O
the	O
store	O
queue	B-Application
.	O
</s>
<s>
In	O
addition	O
to	O
buffering	O
stores	O
until	O
retirement	O
,	O
the	O
store	O
queue	B-Application
serves	O
a	O
second	O
purpose	O
:	O
forwarding	O
data	O
from	O
completed	O
but	O
not-yet-retired	O
(	O
"	O
in-flight	O
"	O
)	O
stores	O
to	O
later	O
loads	O
.	O
</s>
<s>
Rather	O
than	O
a	O
simple	O
FIFO	B-Operating_System
queue	B-Application
,	O
the	O
store	O
queue	B-Application
is	O
really	O
a	O
Content-Addressable	B-Data_Structure
Memory	I-Data_Structure
(	O
CAM	B-Data_Structure
)	O
searched	O
using	O
the	O
memory	O
address	O
.	O
</s>
<s>
When	O
a	O
load	O
executes	O
,	O
it	O
searches	O
the	O
store	O
queue	B-Application
for	O
in-flight	O
stores	O
to	O
the	O
same	O
address	O
that	O
are	O
logically	O
earlier	O
in	O
program	O
order	O
.	O
</s>
<s>
Multiple	O
stores	O
to	O
the	O
load	O
's	O
memory	O
address	O
may	O
be	O
present	O
in	O
the	O
store	O
queue	B-Application
.	O
</s>
<s>
To	O
handle	O
this	O
case	O
,	O
the	O
store	O
queue	B-Application
is	O
priority	O
encoded	O
to	O
select	O
the	O
latest	O
store	O
that	O
is	O
logically	O
earlier	O
than	O
the	O
load	O
in	O
program	O
order	O
.	O
</s>
<s>
The	O
determination	O
of	O
which	O
store	O
is	O
"	O
latest	O
"	O
can	O
be	O
achieved	O
by	O
attaching	O
some	O
sort	O
of	O
timestamp	O
to	O
the	O
instructions	O
as	O
they	O
are	O
fetched	O
and	O
decoded	O
,	O
or	O
alternatively	O
by	O
knowing	O
the	O
relative	O
position	O
(	O
slot	O
)	O
of	O
the	O
load	O
with	O
respect	O
to	O
the	O
oldest	O
and	O
newest	O
stores	O
within	O
the	O
store	O
queue	B-Application
.	O
</s>
<s>
When	O
a	O
load	O
executes	O
,	O
it	O
accesses	O
the	O
memory	O
system	O
and/or	O
store	O
queue	B-Application
to	O
obtain	O
its	O
data	O
value	O
,	O
and	O
then	O
its	O
address	O
and	O
data	O
are	O
buffered	O
in	O
a	O
load	O
queue	B-Application
until	O
retirement	O
.	O
</s>
<s>
The	O
load	O
queue	B-Application
is	O
similar	O
in	O
structure	O
and	O
function	O
to	O
the	O
store	O
queue	B-Application
,	O
and	O
in	O
fact	O
in	O
some	O
processors	O
may	O
be	O
combined	O
with	O
the	O
store	O
queue	B-Application
in	O
a	O
single	O
structure	O
called	O
a	O
load-store	O
queue	B-Application
,	O
or	O
LSQ	O
.	O
</s>
<s>
With	O
this	O
technique	O
,	O
the	O
load	O
queue	B-Application
,	O
like	O
the	O
store	O
queue	B-Application
,	O
is	O
a	O
CAM	B-Data_Structure
searched	O
using	O
the	O
memory	O
access	O
address	O
,	O
and	O
keeps	O
track	O
of	O
all	O
in-flight	O
loads	O
.	O
</s>
<s>
When	O
a	O
store	O
executes	O
,	O
it	O
searches	O
the	O
load	O
queue	B-Application
for	O
completed	O
loads	O
from	O
the	O
same	O
address	O
that	O
are	O
logically	O
later	O
in	O
program	O
order	O
.	O
</s>
<s>
If	O
such	O
a	O
matching	O
load	O
exists	O
,	O
it	O
must	O
have	O
executed	O
before	O
the	O
store	O
and	O
thus	O
read	O
an	O
incorrect	O
,	O
old	O
value	O
from	O
the	O
memory	O
system/store	O
queue	B-Application
.	O
</s>
<s>
The	O
store	O
remains	O
in	O
the	O
store	O
queue	B-Application
and	O
retirement	O
buffer	O
and	O
retires	O
normally	O
,	O
committing	O
its	O
value	O
to	O
the	O
memory	O
system	O
when	O
it	O
retires	O
.	O
</s>
<s>
This	O
technique	O
requires	O
an	O
associative	O
search	O
of	O
the	O
load	O
queue	B-Application
on	O
every	O
store	O
execution	O
,	O
which	O
consumes	O
circuit	O
power	O
and	O
can	O
prove	O
to	O
be	O
a	O
difficult	O
timing	O
path	O
for	O
large	O
load	O
queues	B-Application
.	O
</s>
<s>
This	O
technique	O
is	O
conceptually	O
simpler	O
than	O
the	O
load	O
queue	B-Application
search	O
,	O
and	O
it	O
eliminates	O
a	O
second	O
CAM	B-Data_Structure
and	O
its	O
power-hungry	O
search	O
(	O
the	O
load	O
queue	B-Application
can	O
now	O
be	O
a	O
simple	O
FIFO	B-Operating_System
queue	B-Application
)	O
.	O
</s>
<s>
A	O
minor	O
benefit	O
of	O
this	O
scheme	O
(	O
compared	O
to	O
a	O
load-queue	O
search	O
)	O
is	O
that	O
it	O
will	O
not	O
flag	O
a	O
RAW	O
dependence	O
violation	O
and	O
trigger	O
a	O
pipeline	O
flush	O
if	O
a	O
store	O
that	O
would	O
have	O
caused	O
a	O
RAW	O
dependence	O
violation	O
(	O
the	O
store	O
's	O
address	O
matches	O
an	O
in-flight	O
load	O
's	O
address	O
)	O
has	O
a	O
data	O
value	O
that	O
matches	O
the	O
data	O
value	O
already	O
in	O
the	O
cache	O
.	O
</s>
<s>
In	O
the	O
load-queue	O
search	O
scheme	O
,	O
an	O
additional	O
data	O
comparison	O
would	O
need	O
to	O
be	O
added	O
to	O
the	O
load-queue	O
search	O
hardware	B-Architecture
to	O
prevent	O
such	O
a	O
pipeline	O
flush	O
.	O
</s>
<s>
CPUs	O
that	O
fully	O
support	O
out-of-order	B-General_Concept
execution	I-General_Concept
of	O
loads	O
and	O
stores	O
must	O
be	O
able	O
to	O
detect	O
RAW	O
dependence	O
violations	O
when	O
they	O
occur	O
.	O
</s>
<s>
Processors	O
that	O
fully	O
support	O
out-of-order	O
load/store	O
execution	O
can	O
use	O
an	O
additional	O
,	O
related	O
technique	O
,	O
called	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
,	O
to	O
attempt	O
to	O
predict	O
true	O
dependences	O
between	O
loads	O
and	O
stores	O
before	O
their	O
addresses	O
are	O
known	O
.	O
</s>
<s>
See	O
the	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
article	O
for	O
more	O
details	O
.	O
</s>
