<s>
Memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
is	O
a	O
technique	O
,	O
employed	O
by	O
high-performance	O
out-of-order	B-General_Concept
execution	I-General_Concept
microprocessors	B-Architecture
that	O
execute	O
memory	O
access	O
operations	O
(	O
loads	O
and	O
stores	O
)	O
out	O
of	O
program	O
order	O
,	O
to	O
predict	O
true	O
dependencies	O
between	O
loads	O
and	O
stores	O
at	O
instruction	O
execution	B-General_Concept
time	O
.	O
</s>
<s>
With	O
the	O
predicted	O
dependence	O
information	O
,	O
the	O
processor	O
can	O
then	O
decide	O
to	O
speculatively	B-General_Concept
execute	I-General_Concept
certain	O
loads	O
and	O
stores	O
out	O
of	O
order	O
,	O
while	O
preventing	O
other	O
loads	O
and	O
stores	O
from	O
executing	O
out-of-order	O
(	O
keeping	O
them	O
in-order	O
)	O
.	O
</s>
<s>
Later	O
in	O
the	O
pipeline	B-General_Concept
,	O
memory	B-Architecture
disambiguation	I-Architecture
techniques	O
are	O
used	O
to	O
determine	O
if	O
the	O
loads	O
and	O
stores	O
were	O
correctly	O
executed	O
and	O
,	O
if	O
not	O
,	O
to	O
recover	O
.	O
</s>
<s>
By	O
using	O
the	O
memory	O
dependence	O
predictor	O
to	O
keep	O
most	O
dependent	O
loads	O
and	O
stores	O
in	O
order	O
,	O
the	O
processor	O
gains	O
the	O
benefits	O
of	O
aggressive	O
out-of-order	O
load/store	O
execution	B-General_Concept
but	O
avoids	O
many	O
of	O
the	O
memory	O
dependence	O
violations	O
that	O
occur	O
when	O
loads	O
and	O
stores	O
were	O
incorrectly	O
executed	O
.	O
</s>
<s>
This	O
increases	O
performance	O
because	O
it	O
reduces	O
the	O
number	O
of	O
pipeline	B-General_Concept
flushes	O
that	O
are	O
required	O
to	O
recover	O
from	O
these	O
memory	O
dependence	O
violations	O
.	O
</s>
<s>
See	O
the	O
memory	B-Architecture
disambiguation	I-Architecture
article	O
for	O
more	O
information	O
on	O
memory	O
dependencies	O
,	O
memory	O
dependence	O
violations	O
,	O
and	O
recovery	O
.	O
</s>
<s>
In	O
general	O
,	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
predicts	O
whether	O
two	O
memory	O
operations	O
are	O
dependent	O
,	O
that	O
is	O
,	O
if	O
they	O
interact	O
by	O
accessing	O
the	O
same	O
memory	O
location	O
.	O
</s>
<s>
Besides	O
using	O
store	O
to	O
load	O
(	O
RAW	O
or	O
true	O
)	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
for	O
the	O
out-of-order	O
scheduling	O
of	O
loads	O
and	O
stores	O
,	O
other	O
applications	O
of	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
have	O
been	O
proposed	O
.	O
</s>
<s>
Memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
is	O
an	O
optimization	O
on	O
top	O
of	O
memory	B-Architecture
dependency	I-Architecture
speculation	I-Architecture
.	O
</s>
<s>
Sequential	O
execution	B-General_Concept
semantics	O
imply	O
that	O
stores	O
and	O
loads	O
appear	O
to	O
execute	O
in	O
the	O
order	O
specified	O
by	O
the	O
program	O
.	O
</s>
<s>
However	O
,	O
as	O
with	O
out-of-order	B-General_Concept
execution	I-General_Concept
of	O
other	O
instructions	O
,	O
it	O
may	O
be	O
possible	O
to	O
execute	O
two	O
memory	O
operations	O
in	O
a	O
different	O
order	O
from	O
that	O
implied	O
by	O
the	O
program	O
.	O
</s>
<s>
Αs	O
the	O
scope	O
of	O
the	O
out-of-order	B-General_Concept
execution	I-General_Concept
increased	O
over	O
few	O
tens	O
of	O
instructions	O
,	O
naive	O
memory	O
dependence	O
speculation	O
was	O
used	O
.	O
</s>
<s>
As	O
the	O
scope	O
of	O
out-of-order	B-General_Concept
execution	I-General_Concept
increases	O
further	O
into	O
several	O
tens	O
of	O
instructions	O
,	O
the	O
performance	O
benefits	O
of	O
naive	O
speculation	O
decrease	O
.	O
</s>
<s>
Selective	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
stalls	O
specific	O
loads	O
until	O
it	O
is	O
certain	O
that	O
no	O
violation	O
may	O
occur	O
.	O
</s>
<s>
Exact	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
was	O
developed	O
at	O
the	O
University	O
of	O
Wisconsin	O
–	O
Madison	O
.	O
</s>
<s>
Memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
has	O
other	O
applications	O
beyond	O
the	O
scheduling	O
of	O
loads	O
and	O
stores	O
.	O
</s>
<s>
For	O
example	O
,	O
speculative	O
memory	O
cloaking	O
and	O
speculative	O
memory	O
bypassing	O
use	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
to	O
streamline	O
the	O
communication	O
of	O
values	O
through	O
memory	O
.	O
</s>
<s>
Memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
for	O
loads	O
and	O
stores	O
is	O
analogous	O
to	O
branch	B-General_Concept
prediction	I-General_Concept
for	O
conditional	B-General_Concept
branch	I-General_Concept
instructions	O
.	O
</s>
<s>
In	O
branch	B-General_Concept
prediction	I-General_Concept
,	O
the	O
branch	B-General_Concept
predictor	I-General_Concept
predicts	O
which	O
way	O
the	O
branch	O
will	O
resolve	O
before	O
it	O
is	O
known	O
.	O
</s>
<s>
Later	O
,	O
when	O
the	O
branch	B-General_Concept
instruction	I-General_Concept
executes	O
,	O
it	O
can	O
be	O
determined	O
if	O
the	O
branch	B-General_Concept
instruction	I-General_Concept
was	O
correctly	O
predicted	O
.	O
</s>
<s>
If	O
not	O
,	O
this	O
is	O
a	O
branch	B-General_Concept
misprediction	I-General_Concept
,	O
and	O
a	O
pipeline	B-General_Concept
flush	O
is	O
necessary	O
to	O
throw	O
away	O
instructions	O
that	O
were	O
speculatively	O
fetched	O
and	O
executed	O
.	O
</s>
<s>
Branch	B-General_Concept
prediction	I-General_Concept
can	O
be	O
thought	O
of	O
as	O
a	O
two	O
step	O
process	O
.	O
</s>
<s>
Similarly	O
,	O
memory	B-Architecture
dependence	I-Architecture
prediction	I-Architecture
can	O
be	O
thought	O
of	O
as	O
a	O
two	O
step	O
process	O
.	O
</s>
