<s>
The	O
memory	B-General_Concept
controller	I-General_Concept
is	O
a	O
digital	O
circuit	O
that	O
manages	O
the	O
flow	O
of	O
data	O
going	O
to	O
and	O
from	O
the	O
computer	O
's	O
main	O
memory	O
.	O
</s>
<s>
A	O
memory	B-General_Concept
controller	I-General_Concept
can	O
be	O
a	O
separate	O
chip	O
or	O
integrated	O
into	O
another	O
chip	O
,	O
such	O
as	O
being	O
placed	O
on	O
the	O
same	O
die	O
or	O
as	O
an	O
integral	O
part	O
of	O
a	O
microprocessor	B-Architecture
;	O
in	O
the	O
latter	O
case	O
,	O
it	O
is	O
usually	O
called	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
(	O
IMC	O
)	O
.	O
</s>
<s>
A	O
memory	B-General_Concept
controller	I-General_Concept
is	O
sometimes	O
also	O
called	O
a	O
memory	B-General_Concept
chip	I-General_Concept
controller	I-General_Concept
(	O
MCC	O
)	O
or	O
a	O
memory	B-General_Concept
controller	I-General_Concept
unit	I-General_Concept
(	O
MCU	O
)	O
.	O
</s>
<s>
A	O
common	O
form	O
of	O
memory	B-General_Concept
controller	I-General_Concept
is	O
the	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	B-General_Concept
)	O
which	O
in	O
many	O
operating	B-General_Concept
systems	I-General_Concept
implements	O
virtual	B-General_Concept
addressing	I-General_Concept
.	O
</s>
<s>
Most	O
modern	O
desktop	O
or	O
workstation	O
microprocessors	B-Architecture
use	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
(	O
IMC	O
)	O
,	O
including	O
microprocessors	B-Architecture
from	O
Intel	O
,	O
AMD	O
,	O
and	O
those	O
built	O
around	O
the	O
ARM	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
Prior	O
to	O
K8	B-Device
(	O
circa	O
2003	O
)	O
,	O
AMD	O
microprocessors	B-Architecture
had	O
a	O
memory	B-General_Concept
controller	I-General_Concept
implemented	O
on	O
their	O
motherboard	O
's	O
northbridge	B-Device
.	O
</s>
<s>
In	O
K8	B-Device
and	O
later	O
,	O
AMD	O
employed	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
Likewise	O
,	O
until	O
Nehalem	B-Device
(	O
circa	O
2008	O
)	O
,	O
Intel	O
microprocessors	B-Architecture
used	O
memory	B-General_Concept
controllers	I-General_Concept
implemented	O
on	O
the	O
motherboard	O
's	O
northbridge	B-Device
.	O
</s>
<s>
Nehalem	B-Device
and	O
later	O
switched	O
to	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
Other	O
examples	O
of	O
microprocessors	B-Architecture
that	O
use	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
include	O
NVIDIA	O
's	O
Fermi	B-General_Concept
,	O
IBM	O
's	O
POWER5	B-Device
,	O
and	O
Sun	O
Microsystems	O
's	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
.	O
</s>
<s>
While	O
an	O
integrated	B-General_Concept
memory	I-General_Concept
controller	I-General_Concept
has	O
the	O
potential	O
to	O
increase	O
the	O
system	O
's	O
performance	O
,	O
such	O
as	O
by	O
reducing	O
memory	B-General_Concept
latency	I-General_Concept
,	O
it	O
locks	O
the	O
microprocessor	B-Architecture
to	O
a	O
specific	O
type	O
(	O
or	O
types	O
)	O
of	O
memory	O
,	O
forcing	O
a	O
redesign	O
in	O
order	O
to	O
support	O
newer	O
memory	O
technologies	O
.	O
</s>
<s>
When	O
the	O
memory	B-General_Concept
controller	I-General_Concept
is	O
not	O
on-die	O
,	O
the	O
same	O
CPU	O
may	O
be	O
installed	O
on	O
a	O
new	O
motherboard	O
,	O
with	O
an	O
updated	O
northbridge	B-Device
.	O
</s>
<s>
Some	O
microprocessors	B-Architecture
in	O
the	O
1990s	O
,	O
such	O
as	O
the	O
DEC	O
Alpha	B-General_Concept
21066	I-General_Concept
and	O
HP	O
PA-7300LC	B-General_Concept
,	O
had	O
integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
;	O
however	O
,	O
rather	O
than	O
for	O
performance	O
gains	O
,	O
this	O
was	O
implemented	O
to	O
reduce	O
the	O
cost	O
of	O
systems	O
by	O
eliminating	O
the	O
need	O
for	O
an	O
external	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
Some	O
CPUs	O
are	O
designed	O
to	O
have	O
their	O
memory	B-General_Concept
controllers	I-General_Concept
as	O
dedicated	O
external	O
components	O
that	O
are	O
not	O
part	O
of	O
the	O
chipset	O
.	O
</s>
<s>
An	O
example	O
is	O
IBM	O
POWER8	B-Device
,	O
which	O
uses	O
external	O
Centaur	O
chips	O
that	O
are	O
mounted	O
onto	O
DIMM	B-General_Concept
modules	O
and	O
act	O
as	O
memory	O
buffers	O
,	O
L4	O
cache	O
chips	O
,	O
and	O
as	O
the	O
actual	O
memory	B-General_Concept
controllers	I-General_Concept
.	O
</s>
<s>
Memory	B-General_Concept
controllers	I-General_Concept
contain	O
the	O
logic	O
necessary	O
to	O
read	O
and	O
write	O
to	O
DRAM	O
,	O
and	O
to	O
"	B-General_Concept
refresh	I-General_Concept
"	I-General_Concept
the	I-General_Concept
DRAM	I-General_Concept
.	O
</s>
<s>
Reading	O
and	O
writing	O
to	O
DRAM	O
is	O
performed	O
by	O
selecting	O
the	O
row	O
and	O
column	O
data	O
addresses	O
of	O
the	O
DRAM	O
as	O
the	O
inputs	O
to	O
the	O
multiplexer	B-Protocol
circuit	O
,	O
where	O
the	O
demultiplexer	O
on	O
the	O
DRAM	O
uses	O
the	O
converted	O
inputs	O
to	O
select	O
the	O
correct	O
memory	O
location	O
and	O
return	O
the	O
data	O
,	O
which	O
is	O
then	O
passed	O
back	O
through	O
a	O
multiplexer	B-Protocol
to	O
consolidate	O
the	O
data	O
in	O
order	O
to	O
reduce	O
the	O
required	O
bus	O
width	O
for	O
the	O
operation	O
.	O
</s>
<s>
Memory	B-General_Concept
controllers	I-General_Concept
 '	O
bus	O
widths	O
range	O
from	O
8-bit	O
in	O
earlier	O
systems	O
,	O
to	O
512-bit	O
in	O
more	O
complicated	O
systems	O
and	O
video	O
cards	O
(	O
typically	O
implemented	O
as	O
four	O
64-bit	B-Device
simultaneous	O
memory	B-General_Concept
controllers	I-General_Concept
operating	O
in	O
parallel	O
,	O
though	O
some	O
are	O
designed	O
to	O
operate	O
in	O
"	O
gang	O
mode	O
"	O
where	O
two	O
64-bit	B-Device
memory	B-General_Concept
controllers	I-General_Concept
can	O
be	O
used	O
to	O
access	O
a	O
128-bit	O
memory	O
device	O
)	O
.	O
</s>
<s>
Some	O
memory	B-General_Concept
controllers	I-General_Concept
,	O
such	O
as	O
the	O
one	O
integrated	O
into	O
PowerQUICC	B-General_Concept
II	O
processors	O
,	O
include	O
error	B-Error_Name
detection	I-Error_Name
and	I-Error_Name
correction	I-Error_Name
hardware	O
.	O
</s>
<s>
A	O
few	O
experimental	O
memory	B-General_Concept
controllers	I-General_Concept
(	O
mostly	O
aimed	O
at	O
the	O
server	O
market	O
where	O
data	O
protection	O
is	O
legally	O
required	O
)	O
contain	O
a	O
second	O
level	O
of	O
address	O
translation	O
,	O
in	O
addition	O
to	O
the	O
first	O
level	O
of	O
address	O
translation	O
performed	O
by	O
the	O
CPU	O
's	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
Memory	B-General_Concept
controllers	I-General_Concept
integrated	O
into	O
certain	O
Intel	B-Device
Core	I-Device
processors	O
also	O
provide	O
memory	O
scrambling	O
as	O
a	O
feature	O
that	O
turns	O
user	O
data	O
written	O
to	O
the	O
main	O
memory	O
into	O
pseudo-random	B-Error_Name
patterns	O
.	O
</s>
<s>
Double	O
data	O
rate	O
(	O
DDR	O
)	O
memory	B-General_Concept
controllers	I-General_Concept
are	O
used	O
to	O
drive	O
DDR	O
SDRAM	O
,	O
where	O
data	O
is	O
transferred	O
on	O
both	O
rising	O
and	O
falling	O
edges	O
of	O
the	O
system	O
's	O
memory	O
clock	O
.	O
</s>
<s>
DDR	O
memory	B-General_Concept
controllers	I-General_Concept
are	O
significantly	O
more	O
complicated	O
when	O
compared	O
to	O
single	O
data	O
rate	O
controllers	O
,	O
but	O
they	O
allow	O
for	O
twice	O
the	O
data	O
to	O
be	O
transferred	O
without	O
increasing	O
the	O
memory	O
cell	O
's	O
clock	O
rate	O
or	O
bus	O
width	O
.	O
</s>
<s>
Multichannel	O
memory	O
memory	B-General_Concept
controllers	I-General_Concept
are	O
memory	B-General_Concept
controllers	I-General_Concept
where	O
the	O
DRAM	O
devices	O
are	O
separated	O
on	O
to	O
multiple	O
different	O
buses	O
to	O
allow	O
the	O
memory	O
controller(s )	O
to	O
access	O
them	O
in	O
parallel	O
.	O
</s>
<s>
Fully	O
buffered	O
memory	O
systems	O
place	O
a	O
memory	O
buffer	O
device	O
on	O
every	O
memory	B-General_Concept
module	I-General_Concept
(	O
called	O
an	O
FB-DIMM	B-General_Concept
when	O
Fully	O
Buffered	O
RAM	O
is	O
used	O
)	O
,	O
which	O
unlike	O
traditional	O
memory	B-General_Concept
controller	I-General_Concept
devices	O
,	O
use	O
a	O
serial	O
data	O
link	O
to	O
the	O
memory	B-General_Concept
controller	I-General_Concept
instead	O
of	O
the	O
parallel	O
link	O
used	O
in	O
previous	O
RAM	O
designs	O
.	O
</s>
<s>
This	O
increase	O
is	O
due	O
to	O
the	O
time	O
required	O
to	O
convert	O
the	O
parallel	O
information	O
read	O
from	O
the	O
DRAM	O
cell	O
to	O
the	O
serial	O
format	O
used	O
by	O
the	O
FB-DIMM	B-General_Concept
controller	O
,	O
and	O
back	O
to	O
a	O
parallel	O
form	O
in	O
the	O
memory	B-General_Concept
controller	I-General_Concept
on	O
the	O
motherboard	O
.	O
</s>
<s>
In	O
theory	O
,	O
the	O
FB-DIMM	B-General_Concept
'	O
s	O
memory	O
buffer	O
device	O
could	O
be	O
built	O
to	O
access	O
any	O
DRAM	O
cells	O
,	O
allowing	O
for	O
memory	O
cell	O
agnostic	O
memory	B-General_Concept
controller	I-General_Concept
design	O
,	O
but	O
this	O
has	O
not	O
been	O
demonstrated	O
,	O
as	O
the	O
technology	O
is	O
in	O
its	O
infancy	O
.	O
</s>
<s>
Many	O
flash	B-Device
memory	I-Device
devices	O
,	O
such	O
as	O
USB	O
flash	O
drives	O
and	O
solid	B-Device
state	I-Device
drives	I-Device
,	O
include	O
a	O
flash	B-Device
memory	I-Device
controller	I-Device
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
is	O
inherently	O
slower	O
to	O
access	O
than	O
RAM	O
and	O
often	O
becomes	O
unusable	O
after	O
a	O
few	O
million	O
write	O
cycles	O
,	O
which	O
generally	O
makes	O
it	O
unsuitable	O
for	O
RAM	O
applications	O
.	O
</s>
