<s>
The	O
memory	B-Algorithm
cell	I-Algorithm
is	O
the	O
fundamental	O
building	O
block	O
of	O
computer	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
The	O
memory	B-Algorithm
cell	I-Algorithm
is	O
an	O
electronic	O
circuit	O
that	O
stores	O
one	O
bit	O
of	O
binary	O
information	O
and	O
it	O
must	O
be	O
set	O
to	O
store	O
a	O
logic	O
1	O
(	O
high	O
voltage	O
level	O
)	O
and	O
reset	O
to	O
store	O
a	O
logic	O
0	O
(	O
low	O
voltage	O
level	O
)	O
.	O
</s>
<s>
The	O
value	O
in	O
the	O
memory	B-Algorithm
cell	I-Algorithm
can	O
be	O
accessed	O
by	O
reading	O
it	O
.	O
</s>
<s>
Over	O
the	O
history	O
of	O
computing	O
,	O
different	O
memory	B-Algorithm
cell	I-Algorithm
architectures	O
have	O
been	O
used	O
,	O
including	O
core	O
memory	O
and	O
bubble	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Today	O
,	O
the	O
most	O
common	O
memory	B-Algorithm
cell	I-Algorithm
architecture	O
is	O
MOS	B-Architecture
memory	I-Architecture
,	O
which	O
consists	O
of	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	B-Architecture
)	O
memory	B-Algorithm
cells	I-Algorithm
.	O
</s>
<s>
Modern	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
uses	O
MOS	B-Architecture
field-effect	I-Architecture
transistors	I-Architecture
(	O
MOSFETs	B-Architecture
)	O
as	O
flip-flops	B-General_Concept
,	O
along	O
with	O
MOS	B-Architecture
capacitors	O
for	O
certain	O
types	O
of	O
RAM	B-Architecture
.	O
</s>
<s>
The	O
SRAM	B-Architecture
(	O
static	B-Architecture
RAM	I-Architecture
)	O
memory	B-Algorithm
cell	I-Algorithm
is	O
a	O
type	O
of	O
flip-flop	B-General_Concept
circuit	O
,	O
typically	O
implemented	O
using	O
MOSFETs	B-Architecture
.	O
</s>
<s>
A	O
second	O
type	O
,	O
DRAM	O
(	O
dynamic	O
RAM	B-Architecture
)	O
,	O
is	O
based	O
around	O
MOS	B-Architecture
capacitors	O
.	O
</s>
<s>
On	O
the	O
other	O
hand	O
,	O
most	O
non-volatile	B-General_Concept
memory	I-General_Concept
(	O
NVM	O
)	O
is	O
based	O
on	O
floating-gate	B-Algorithm
memory	B-Algorithm
cell	I-Algorithm
architectures	O
.	O
</s>
<s>
Non-volatile	B-General_Concept
memory	I-General_Concept
technologies	O
including	O
EPROM	B-General_Concept
,	O
EEPROM	B-General_Concept
and	O
flash	B-Device
memory	I-Device
use	O
floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
,	O
which	O
are	O
based	O
around	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
transistors	B-Application
.	O
</s>
<s>
The	O
memory	B-Algorithm
cell	I-Algorithm
is	O
the	O
fundamental	O
building	O
block	O
of	O
memory	O
.	O
</s>
<s>
It	O
can	O
be	O
implemented	O
using	O
different	O
technologies	O
,	O
such	O
as	O
bipolar	O
,	O
MOS	B-Architecture
,	O
and	O
other	O
semiconductor	O
devices	O
.	O
</s>
<s>
Regardless	O
of	O
the	O
implementation	O
technology	O
used	O
,	O
the	O
purpose	O
of	O
the	O
binary	O
memory	B-Algorithm
cell	I-Algorithm
is	O
always	O
the	O
same	O
.	O
</s>
<s>
Logic	O
circuits	O
without	O
memory	B-Algorithm
cells	I-Algorithm
are	O
called	O
combinational	O
,	O
meaning	O
the	O
output	O
depends	O
only	O
on	O
the	O
present	O
input	O
.	O
</s>
<s>
In	O
computers	O
,	O
it	O
allows	O
to	O
store	O
both	O
programs	O
and	O
data	O
and	O
memory	B-Algorithm
cells	I-Algorithm
are	O
also	O
used	O
for	O
temporary	O
storage	O
of	O
the	O
output	O
of	O
combinational	O
circuits	O
to	O
be	O
used	O
later	O
by	O
digital	O
systems	O
.	O
</s>
<s>
Logic	O
circuits	O
that	O
use	O
memory	B-Algorithm
cells	I-Algorithm
are	O
called	O
sequential	O
circuits	O
,	O
meaning	O
the	O
output	O
depends	O
not	O
only	O
on	O
the	O
present	O
input	O
,	O
but	O
also	O
on	O
the	O
history	O
of	O
past	O
inputs	O
.	O
</s>
<s>
This	O
dependence	O
on	O
the	O
history	O
of	O
past	O
inputs	O
makes	O
these	O
circuits	O
stateful	B-Application
and	O
it	O
is	O
the	O
memory	B-Algorithm
cells	I-Algorithm
that	O
store	O
this	O
state	O
.	O
</s>
<s>
Computer	B-General_Concept
memory	I-General_Concept
used	O
in	O
most	O
contemporary	O
computer	O
systems	O
is	O
built	O
mainly	O
out	O
of	O
DRAM	B-Algorithm
cells	I-Algorithm
;	O
since	O
the	O
layout	O
is	O
much	O
smaller	O
than	O
SRAM	B-Architecture
,	O
it	O
can	O
be	O
more	O
densely	O
packed	O
yielding	O
cheaper	O
memory	O
with	O
greater	O
capacity	O
.	O
</s>
<s>
Since	O
the	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
stores	O
its	O
value	O
as	O
the	O
charge	O
of	O
a	O
capacitor	O
,	O
and	O
there	O
are	O
current	O
leakage	O
issues	O
,	O
its	O
value	O
must	O
be	O
constantly	O
rewritten	O
.	O
</s>
<s>
This	O
is	O
one	O
of	O
the	O
reasons	O
that	O
make	O
DRAM	B-Algorithm
cells	I-Algorithm
slower	O
than	O
the	O
larger	O
SRAM	B-Architecture
(	O
static	B-Architecture
RAM	I-Architecture
)	O
cells	O
,	O
which	O
has	O
its	O
value	O
always	O
available	O
.	O
</s>
<s>
That	O
is	O
the	O
reason	O
why	O
SRAM	B-Architecture
memory	O
is	O
used	O
for	O
on-chip	B-General_Concept
cache	I-General_Concept
included	O
in	O
modern	O
microprocessor	B-Architecture
chips	O
.	O
</s>
<s>
On	O
December	O
11	O
,	O
1946	O
Freddie	O
Williams	O
applied	O
for	O
a	O
patent	O
on	O
his	O
cathode-ray	O
tube	O
(	O
CRT	O
)	O
storing	O
device	O
(	O
Williams	B-General_Concept
tube	I-General_Concept
)	O
with	O
128	O
40-bit	O
words	O
.	O
</s>
<s>
It	O
was	O
operational	O
in	O
1947	O
and	O
is	O
considered	O
the	O
first	O
practical	O
implementation	O
of	O
random-access	B-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
.	O
</s>
<s>
Practical	O
magnetic-core	O
memory	O
was	O
developed	O
by	O
An	O
Wang	O
in	O
1948	O
,	O
and	O
improved	O
by	O
Jay	O
Forrester	O
and	O
Jan	O
A	O
.	O
Rajchman	O
in	O
the	O
early	O
1950s	O
,	O
before	O
being	O
commercialised	O
with	O
the	O
Whirlwind	B-Device
computer	I-Device
in	O
1953	O
.	O
</s>
<s>
Semiconductor	B-Architecture
memory	I-Architecture
began	O
in	O
the	O
early	O
1960s	O
with	O
bipolar	O
memory	B-Algorithm
cells	I-Algorithm
,	O
made	O
of	O
bipolar	O
transistors	B-Application
.	O
</s>
<s>
The	O
invention	O
of	O
the	O
MOSFET	B-Architecture
(	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
)	O
,	O
also	O
known	O
as	O
the	O
MOS	B-Architecture
transistor	I-Architecture
,	O
by	O
Mohamed	O
M	O
.	O
Atalla	O
and	O
Dawon	O
Kahng	O
at	O
Bell	O
Labs	O
in	O
1959	O
,	O
enabled	O
the	O
practical	O
use	O
of	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	B-Architecture
)	O
transistors	B-Application
as	O
memory	B-Algorithm
cell	I-Algorithm
storage	O
elements	O
,	O
a	O
function	O
previously	O
served	O
by	O
magnetic	O
cores	O
.	O
</s>
<s>
The	O
first	O
modern	O
memory	B-Algorithm
cells	I-Algorithm
were	O
introduced	O
in	O
1964	O
,	O
when	O
John	O
Schmidt	O
designed	O
the	O
first	O
64-bit	O
p-channel	O
MOS	B-Architecture
(	O
PMOS	B-Algorithm
)	O
static	B-Architecture
random-access	I-Architecture
memory	I-Architecture
(	O
SRAM	B-Architecture
)	O
.	O
</s>
<s>
SRAM	B-Architecture
typically	O
has	O
six-transistor	O
cells	O
,	O
whereas	O
DRAM	O
(	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
)	O
typically	O
has	O
single-transistor	O
cells	O
.	O
</s>
<s>
In	O
1965	O
,	O
Toshiba	O
's	O
Toscal	O
BC-1411	O
electronic	B-Application
calculator	I-Application
used	O
a	O
form	O
of	O
capacitive	O
bipolar	O
DRAM	O
,	O
storing	O
180-bit	O
data	O
on	O
discrete	O
memory	B-Algorithm
cells	I-Algorithm
,	O
consisting	O
of	O
germanium	O
bipolar	O
transistors	B-Application
and	O
capacitors	O
.	O
</s>
<s>
MOS	B-Architecture
technology	I-Architecture
is	O
the	O
basis	O
for	O
modern	O
DRAM	O
.	O
</s>
<s>
In	O
1966	O
,	O
Dr.	O
Robert	O
H	O
.	O
Dennard	O
at	O
the	O
IBM	O
Thomas	O
J	O
.	O
Watson	O
Research	O
Center	O
was	O
working	O
on	O
MOS	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
While	O
examining	O
the	O
characteristics	O
of	O
MOS	B-Architecture
technology	I-Architecture
,	O
he	O
found	O
it	O
was	O
capable	O
of	O
building	O
capacitors	O
,	O
and	O
that	O
storing	O
a	O
charge	O
or	O
no	O
charge	O
on	O
the	O
MOS	B-Architecture
capacitor	O
could	O
represent	O
the	O
1	O
and	O
0	O
of	O
a	O
bit	O
,	O
while	O
the	O
MOS	B-Architecture
transistor	I-Architecture
could	O
control	O
writing	O
the	O
charge	O
to	O
the	O
capacitor	O
.	O
</s>
<s>
This	O
led	O
to	O
his	O
development	O
of	O
a	O
single-transistor	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
.	O
</s>
<s>
In	O
1967	O
,	O
Dennard	O
filed	O
a	O
patent	O
for	O
a	O
single-transistor	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
,	O
based	O
on	O
MOS	B-Architecture
technology	I-Architecture
.	O
</s>
<s>
The	O
first	O
commercial	O
bipolar	O
64-bit	O
SRAM	B-Architecture
was	O
released	O
by	O
Intel	O
in	O
1969	O
with	O
the	O
3101	O
Schottky	O
TTL	B-General_Concept
.	O
</s>
<s>
One	O
year	O
later	O
,	O
it	O
released	O
the	O
first	O
DRAM	O
integrated	O
circuit	O
chip	B-Architecture
,	O
the	O
Intel	B-General_Concept
1103	I-General_Concept
,	O
based	O
on	O
MOS	B-Architecture
technology	I-Architecture
.	O
</s>
<s>
By	O
1972	O
,	O
it	O
beat	O
previous	O
records	O
in	O
semiconductor	B-Architecture
memory	I-Architecture
sales	O
.	O
</s>
<s>
DRAM	O
chips	O
during	O
the	O
early	O
1970s	O
had	O
three-transistor	O
cells	O
,	O
before	O
single-transistor	O
cells	O
became	O
standard	O
since	O
the	O
mid-1970s	O
.	O
</s>
<s>
CMOS	B-Device
memory	I-Device
was	O
commercialized	O
by	O
RCA	O
,	O
which	O
launched	O
a	O
288-bit	O
CMOS	B-Device
SRAM	B-Architecture
memory	B-Architecture
chip	I-Architecture
in	O
1968	O
.	O
</s>
<s>
CMOS	B-Device
memory	I-Device
was	O
initially	O
slower	O
than	O
NMOS	B-Architecture
memory	O
,	O
which	O
was	O
more	O
widely	O
used	O
by	O
computers	O
in	O
the	O
1970s	O
.	O
</s>
<s>
In	O
1978	O
,	O
Hitachi	O
introduced	O
the	O
twin-well	O
CMOS	B-Device
process	O
,	O
with	O
its	O
HM6147	O
(	O
4kb	O
SRAM	B-Architecture
)	O
memory	B-Architecture
chip	I-Architecture
,	O
manufactured	O
with	O
a	O
3	O
µm	O
process	O
.	O
</s>
<s>
The	O
HM6147	O
chip	B-Architecture
was	O
able	O
to	O
match	O
the	O
performance	O
of	O
the	O
fastest	O
NMOS	B-Architecture
memory	B-Architecture
chip	I-Architecture
at	O
the	O
time	O
,	O
while	O
the	O
HM6147	O
also	O
consumed	O
significantly	O
less	O
power	O
.	O
</s>
<s>
With	O
comparable	O
performance	O
and	O
much	O
less	O
power	O
consumption	O
,	O
the	O
twin-well	O
CMOS	B-Device
process	O
eventually	O
overtook	O
NMOS	B-Architecture
as	O
the	O
most	O
common	O
semiconductor	B-Architecture
manufacturing	I-Architecture
process	I-Architecture
for	O
computer	B-General_Concept
memory	I-General_Concept
in	O
the	O
1980s	O
.	O
</s>
<s>
The	O
two	O
most	O
common	O
types	O
of	O
DRAM	O
memory	B-Algorithm
cells	I-Algorithm
since	O
the	O
1980s	O
have	O
been	O
trench-capacitor	O
cells	O
and	O
stacked-capacitor	O
cells	O
.	O
</s>
<s>
stacked-capacitor	O
cells	O
are	O
the	O
earliest	O
form	O
of	O
three-dimensional	O
memory	O
(	O
3D	O
memory	O
)	O
,	O
where	O
memory	B-Algorithm
cells	I-Algorithm
are	O
stacked	O
vertically	O
in	O
a	O
three-dimensional	O
cell	O
structure	O
.	O
</s>
<s>
The	O
floating-gate	B-Algorithm
MOSFET	I-Algorithm
(	O
FGMOS	B-Algorithm
)	O
was	O
invented	O
by	O
Dawon	O
Kahng	O
and	O
Simon	O
Sze	O
at	O
Bell	O
Labs	O
in	O
1967	O
.	O
</s>
<s>
They	O
proposed	O
the	O
concept	O
of	O
floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
,	O
using	O
FGMOS	B-Algorithm
transistors	B-Application
,	O
which	O
could	O
be	O
used	O
to	O
produce	O
reprogrammable	B-General_Concept
ROM	I-General_Concept
(	O
read-only	O
memory	O
)	O
.	O
</s>
<s>
Floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
later	O
became	O
the	O
basis	O
for	O
non-volatile	B-General_Concept
memory	I-General_Concept
(	O
NVM	O
)	O
technologies	O
including	O
EPROM	B-General_Concept
(	O
erasable	B-General_Concept
programmable	I-General_Concept
ROM	I-General_Concept
)	O
,	O
EEPROM	B-General_Concept
(	O
electrically	B-General_Concept
erasable	I-General_Concept
programmable	I-General_Concept
ROM	I-General_Concept
)	O
and	O
flash	B-Device
memory	I-Device
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
was	O
invented	O
by	O
Fujio	O
Masuoka	O
at	O
Toshiba	O
in	O
1980	O
.	O
</s>
<s>
Multi-level	B-Device
cell	I-Device
(	O
MLC	O
)	O
flash	B-Device
memory	I-Device
was	O
introduced	O
by	O
NEC	O
,	O
which	O
demonstrated	O
quad-level	O
cells	O
in	O
a	O
64Mb	O
flash	B-Device
chip	I-Device
storing	O
2-bit	O
per	O
cell	O
in	O
1996	O
.	O
</s>
<s>
3D	O
V-NAND	O
,	O
where	O
flash	B-Device
memory	I-Device
cells	O
are	O
stacked	O
vertically	O
using	O
3D	O
charge	B-Algorithm
trap	I-Algorithm
flash	I-Algorithm
(	O
CTP	O
)	O
technology	O
,	O
was	O
first	O
announced	O
by	O
Toshiba	O
in	O
2007	O
,	O
and	O
first	O
commercially	O
manufactured	O
by	O
Samsung	O
Electronics	O
in	O
2013	O
.	O
</s>
<s>
The	O
following	O
schematics	O
detail	O
the	O
three	O
most	O
used	O
implementations	O
for	O
memory	B-Algorithm
cells	I-Algorithm
:	O
</s>
<s>
The	O
dynamic	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
cell	O
(	O
DRAM	O
)	O
;	O
</s>
<s>
The	O
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
cell	O
(	O
SRAM	B-Architecture
)	O
;	O
</s>
<s>
Flip-flops	B-General_Concept
like	O
the	O
J/K	O
shown	O
below	O
,	O
using	O
only	O
logic	O
gates	O
.	O
</s>
<s>
thumb|DRAM	O
cell	O
(	O
1	O
transistor	B-Application
and	O
one	O
capacitor	O
)	O
.thumb	O
|SRAM	O
cell	O
(	O
6	O
transistors	B-Application
)	O
.thumb	O
|Clocked	O
J/K	O
flip-flop	B-General_Concept
.	O
</s>
<s>
The	O
storage	O
element	O
of	O
the	O
DRAM	O
memory	B-Algorithm
cell	I-Algorithm
is	O
the	O
capacitor	O
labeled	O
(	O
4	O
)	O
in	O
the	O
diagram	O
above	O
.	O
</s>
<s>
The	O
nMOS	B-Architecture
transistor	I-Architecture
(	O
3	O
)	O
acts	O
as	O
a	O
gate	O
to	O
allow	O
reading	O
or	O
writing	O
when	O
open	O
or	O
storing	O
when	O
closed	O
.	O
</s>
<s>
For	O
reading	O
the	O
Word	O
line	O
(	O
2	O
)	O
drives	O
a	O
logic	O
1	O
(	O
voltage	O
high	O
)	O
into	O
the	O
gate	O
of	O
the	O
nMOS	B-Architecture
transistor	I-Architecture
(	O
3	O
)	O
which	O
makes	O
it	O
conductive	O
and	O
the	O
charge	O
stored	O
at	O
the	O
capacitor	O
(	O
4	O
)	O
is	O
then	O
transferred	O
to	O
the	O
bit	O
line	O
(	O
1	O
)	O
.	O
</s>
<s>
The	O
word	O
line	O
activates	O
the	O
nMOS	B-Architecture
transistor	I-Architecture
(	O
3	O
)	O
connecting	O
it	O
to	O
the	O
storage	O
capacitor	O
(	O
4	O
)	O
.	O
</s>
<s>
The	O
only	O
issue	O
is	O
to	O
keep	O
it	O
open	O
enough	O
time	O
to	O
ensure	O
that	O
the	O
capacitor	O
is	O
fully	O
charged	O
or	O
discharged	O
before	O
turning	O
off	O
the	O
nMOS	B-Architecture
transistor	I-Architecture
(	O
3	O
)	O
.	O
</s>
<s>
The	O
working	O
principle	O
of	O
SRAM	B-Architecture
memory	B-Algorithm
cell	I-Algorithm
can	O
be	O
easier	O
to	O
understand	O
if	O
the	O
transistors	B-Application
M1	O
through	O
M4	O
are	O
drawn	O
as	O
logic	O
gates	O
.	O
</s>
<s>
To	O
read	O
the	O
contents	O
of	O
the	O
memory	B-Algorithm
cell	I-Algorithm
stored	O
in	O
the	O
loop	O
,	O
the	O
transistors	B-Application
M5	O
and	O
M6	O
must	O
be	O
turned	O
on	O
.	O
</s>
<s>
The	O
writing	O
process	O
is	O
similar	O
,	O
the	O
difference	O
is	O
that	O
now	O
the	O
new	O
value	O
that	O
will	O
be	O
stored	O
in	O
the	O
memory	B-Algorithm
cell	I-Algorithm
is	O
driven	O
into	O
the	O
bit	O
line	O
(	O
)	O
and	O
the	O
inverted	O
one	O
into	O
its	O
complement	O
(	O
)	O
.	O
</s>
<s>
Next	O
transistors	B-Application
M5	O
and	O
M6	O
are	O
open	O
by	O
driving	O
a	O
logic	O
1	O
(	O
voltage	O
high	O
)	O
into	O
the	O
word	O
line	O
(	O
)	O
.	O
</s>
<s>
if	O
the	O
value	O
of	O
the	O
loop	O
is	O
different	O
from	O
the	O
new	O
value	O
driven	O
there	O
are	O
two	O
conflicting	O
values	O
,	O
in	O
order	O
for	O
the	O
voltage	O
in	O
the	O
bit	O
lines	O
to	O
overwrite	O
the	O
output	O
of	O
the	O
inverters	O
,	O
the	O
size	O
of	O
the	O
M5	O
and	O
M6	O
transistors	B-Application
must	O
be	O
larger	O
than	O
that	O
of	O
the	O
M1-M4	O
transistors	B-Application
.	O
</s>
<s>
The	O
flip-flop	B-General_Concept
has	O
many	O
different	O
implementations	O
,	O
its	O
storage	O
element	O
is	O
usually	O
a	O
latch	B-General_Concept
consisting	O
of	O
a	O
NAND	O
gate	O
loop	O
or	O
a	O
NOR	O
gate	O
loop	O
with	O
additional	O
gates	O
used	O
to	O
implement	O
clocking	O
.	O
</s>
<s>
Flip-flops	B-General_Concept
are	O
typically	O
implemented	O
using	O
MOSFETs	B-Architecture
.	O
</s>
<s>
Floating-gate	B-Algorithm
memory	B-Algorithm
cells	I-Algorithm
,	O
based	O
on	O
floating-gate	B-Algorithm
MOSFETs	I-Algorithm
,	O
are	O
used	O
for	O
most	O
non-volatile	B-General_Concept
memory	I-General_Concept
(	O
NVM	O
)	O
technologies	O
,	O
including	O
EPROM	B-General_Concept
,	O
EEPROM	B-General_Concept
and	O
flash	B-Device
memory	I-Device
.	O
</s>
