<s>
Memory	B-General_Concept
bandwidth	I-General_Concept
is	O
the	O
rate	O
at	O
which	O
data	O
can	O
be	O
read	O
from	O
or	O
stored	O
into	O
a	O
semiconductor	B-Architecture
memory	I-Architecture
by	O
a	O
processor	B-General_Concept
.	O
</s>
<s>
Memory	B-General_Concept
bandwidth	I-General_Concept
is	O
usually	O
expressed	O
in	O
units	O
of	O
bytes/second	O
,	O
though	O
this	O
can	O
vary	O
for	O
systems	O
with	O
natural	O
data	O
sizes	O
that	O
are	O
not	O
a	O
multiple	O
of	O
the	O
commonly	O
used	O
8-bit	O
bytes	O
.	O
</s>
<s>
Memory	B-General_Concept
bandwidth	I-General_Concept
that	O
is	O
advertised	O
for	O
a	O
given	O
memory	O
or	O
system	O
is	O
usually	O
the	O
maximum	O
theoretical	O
bandwidth	O
.	O
</s>
<s>
In	O
practice	O
the	O
observed	O
memory	B-General_Concept
bandwidth	I-General_Concept
will	O
be	O
less	O
than	O
(	O
and	O
is	O
guaranteed	O
not	O
to	O
exceed	O
)	O
the	O
advertised	O
bandwidth	O
.	O
</s>
<s>
A	O
variety	O
of	O
computer	O
benchmarks	O
exist	O
to	O
measure	O
sustained	O
memory	B-General_Concept
bandwidth	I-General_Concept
using	O
a	O
variety	O
of	O
access	O
patterns	O
.	O
</s>
<s>
These	O
are	O
intended	O
to	O
provide	O
insight	O
into	O
the	O
memory	B-General_Concept
bandwidth	I-General_Concept
that	O
a	O
system	O
should	O
sustain	O
on	O
various	O
classes	O
of	O
real	O
applications	O
.	O
</s>
<s>
Using	O
the	O
same	O
1	O
million	O
byte	O
copy	O
example	O
,	O
the	O
hardware	O
bandwidth	O
on	O
computer	O
systems	O
with	O
a	O
write	B-General_Concept
allocate	I-General_Concept
cache	I-General_Concept
policy	I-General_Concept
would	O
include	O
an	O
additional	O
1	O
million	O
bytes	O
of	O
traffic	O
because	O
the	O
hardware	O
reads	O
the	O
target	O
array	O
from	O
memory	O
into	O
cache	O
before	O
performing	O
the	O
stores	O
.	O
</s>
<s>
Number	O
of	O
interfaces	O
:	O
Modern	O
personal	O
computers	O
typically	O
use	O
two	O
memory	O
interfaces	O
(	O
dual-channel	B-Architecture
mode	O
)	O
for	O
an	O
effective	O
128-bit	O
bus	O
width	O
.	O
</s>
<s>
For	O
example	O
,	O
a	O
computer	O
with	O
dual-channel	B-Architecture
memory	I-Architecture
and	O
one	O
DDR2-800	O
module	O
per	O
channel	O
running	O
at	O
400MHz	O
would	O
have	O
a	O
theoretical	O
maximum	O
memory	B-General_Concept
bandwidth	I-General_Concept
of	O
:	O
</s>
<s>
This	O
theoretical	O
maximum	O
memory	B-General_Concept
bandwidth	I-General_Concept
is	O
referred	O
to	O
as	O
the	O
"	O
burst	O
rate	O
,	O
"	O
which	O
may	O
not	O
be	O
sustainable	O
.	O
</s>
<s>
In	O
a	O
dual-channel	B-Architecture
mode	O
configuration	O
,	O
this	O
is	O
effectively	O
a	O
128-bit	O
width	O
.	O
</s>
<s>
Thus	O
,	O
the	O
memory	O
configuration	O
in	O
the	O
example	O
can	O
be	O
simplified	O
as	O
:	O
two	O
DDR2-800	O
modules	O
running	O
in	O
dual-channel	B-Architecture
mode	O
.	O
</s>
<s>
Some	O
personal	O
computers	O
and	O
most	O
modern	O
graphics	O
cards	O
use	O
more	O
than	O
two	O
memory	O
interfaces	O
(	O
e.g.	O
,	O
four	O
for	O
Intel	O
's	O
LGA	B-Device
2011	I-Device
platform	O
and	O
the	O
NVIDIA	O
GeForce	O
GTX	O
980	O
)	O
.	O
</s>
