<s>
Memory	B-General_Concept
architecture	I-General_Concept
describes	O
the	O
methods	O
used	O
to	O
implement	O
electronic	O
computer	B-General_Concept
data	I-General_Concept
storage	I-General_Concept
in	O
a	O
manner	O
that	O
is	O
a	O
combination	O
of	O
the	O
fastest	O
,	O
most	O
reliable	O
,	O
most	O
durable	O
,	O
and	O
least	O
expensive	O
way	O
to	O
store	O
and	O
retrieve	O
information	O
.	O
</s>
<s>
Memory	B-General_Concept
architecture	I-General_Concept
also	O
explains	O
how	O
binary	O
digits	O
are	O
converted	O
into	O
electric	O
signals	O
and	O
then	O
stored	O
in	O
the	O
memory	O
cells	O
.	O
</s>
<s>
For	O
example	O
,	O
dynamic	B-General_Concept
memory	I-General_Concept
is	O
commonly	O
used	O
for	O
primary	B-General_Concept
data	I-General_Concept
storage	I-General_Concept
due	O
to	O
its	O
fast	O
access	O
speed	O
.	O
</s>
<s>
However	O
dynamic	B-General_Concept
memory	I-General_Concept
must	O
be	O
repeatedly	O
refreshed	B-General_Concept
with	O
a	O
surge	O
of	O
current	O
dozens	O
of	O
time	O
per	O
second	O
,	O
or	O
the	O
stored	O
data	O
will	O
decay	O
and	O
be	O
lost	O
.	O
</s>
<s>
Flash	B-Device
memory	I-Device
allows	O
for	O
long-term	O
storage	O
over	O
a	O
period	O
of	O
years	O
,	O
but	O
it	O
is	O
much	O
slower	O
than	O
dynamic	B-General_Concept
memory	I-General_Concept
,	O
and	O
the	O
static	O
memory	O
storage	O
cells	O
wear	O
out	O
with	O
frequent	O
use	O
.	O
</s>
<s>
Similarly	O
,	O
the	O
data	B-General_Concept
bus	I-General_Concept
is	O
often	O
designed	O
to	O
suit	O
specific	O
needs	O
such	O
as	O
serial	O
or	O
parallel	O
data	O
access	O
,	O
and	O
the	O
memory	O
may	O
be	O
designed	O
to	O
provide	O
for	O
parity	B-Error_Name
error	I-Error_Name
detection	O
or	O
even	O
error	B-General_Concept
correction	I-General_Concept
.	O
</s>
<s>
The	O
earliest	O
memory	B-General_Concept
architectures	I-General_Concept
are	O
the	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
which	O
has	O
two	O
physically	O
separate	O
memories	O
and	O
data	O
paths	O
for	O
program	O
and	O
data	O
,	O
and	O
the	O
Princeton	B-Architecture
architecture	I-Architecture
which	O
uses	O
a	O
single	O
memory	O
and	O
data	O
path	O
for	O
both	O
program	O
and	O
data	O
storage	O
.	O
</s>
<s>
Most	O
general	O
purpose	O
computers	O
use	O
a	O
hybrid	O
split-cache	O
modified	B-Device
Harvard	I-Device
architecture	I-Device
that	O
appears	O
to	O
an	O
application	O
program	O
to	O
have	O
a	O
pure	O
Princeton	B-Architecture
architecture	I-Architecture
machine	O
with	O
gigabytes	O
of	O
virtual	B-Architecture
memory	I-Architecture
,	O
but	O
internally	O
(	O
for	O
speed	O
)	O
it	O
operates	O
with	O
an	O
instruction	O
cache	B-General_Concept
physically	O
separate	O
from	O
a	O
data	O
cache	B-General_Concept
,	O
more	O
like	O
the	O
Harvard	O
model	O
.	O
</s>
<s>
DSP	O
systems	O
usually	O
have	O
a	O
specialized	O
,	O
high	O
bandwidth	O
memory	O
subsystem	O
;	O
with	O
no	O
support	O
for	O
memory	B-General_Concept
protection	I-General_Concept
or	O
virtual	B-Architecture
memory	I-Architecture
management	O
.	O
</s>
<s>
Many	O
digital	B-Architecture
signal	I-Architecture
processors	I-Architecture
have	O
3	O
physically	O
separate	O
memories	O
and	O
datapaths	O
--	O
program	O
storage	O
,	O
coefficient	O
storage	O
,	O
and	O
data	O
storage	O
.	O
</s>
<s>
A	O
series	O
of	O
multiply	B-Algorithm
–	I-Algorithm
accumulate	I-Algorithm
operations	I-Algorithm
fetch	O
from	O
all	O
three	O
areas	O
simultaneously	O
to	O
efficiently	O
implement	O
audio	O
filters	O
as	O
convolutions	B-Language
.	O
</s>
