<s>
In	O
a	O
computer	O
,	O
the	O
memory	B-General_Concept
address	I-General_Concept
register	B-General_Concept
(	O
MAR	O
)	O
is	O
the	O
CPU	B-General_Concept
register	B-General_Concept
that	O
either	O
stores	O
the	O
memory	B-General_Concept
address	I-General_Concept
from	O
which	O
data	O
will	O
be	O
fetched	O
to	O
the	O
CPU	B-General_Concept
registers	O
,	O
or	O
the	O
address	O
to	O
which	O
data	O
will	O
be	O
sent	O
and	O
stored	O
via	O
system	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
In	O
other	O
words	O
,	O
this	O
register	B-General_Concept
is	O
used	O
to	O
access	O
data	O
and	O
instructions	O
from	O
memory	O
during	O
the	O
execution	O
phase	O
of	O
instruction	O
.	O
</s>
<s>
MAR	O
holds	O
the	O
memory	B-General_Concept
location	I-General_Concept
of	O
data	O
that	O
needs	O
to	O
be	O
accessed	O
.	O
</s>
<s>
When	O
reading	O
from	O
memory	O
,	O
data	O
addressed	O
by	O
MAR	O
is	O
fed	O
into	O
the	O
MDR	B-General_Concept
(	O
memory	B-General_Concept
data	I-General_Concept
register	I-General_Concept
)	O
and	O
then	O
used	O
by	O
the	O
CPU	B-General_Concept
.	O
</s>
<s>
When	O
writing	O
to	O
memory	O
,	O
the	O
CPU	B-General_Concept
writes	O
data	O
from	O
MDR	B-General_Concept
to	O
the	O
memory	B-General_Concept
location	I-General_Concept
whose	O
address	O
is	O
stored	O
in	O
MAR	O
.	O
</s>
<s>
MAR	O
,	O
which	O
is	O
found	O
inside	O
the	O
CPU	B-General_Concept
,	O
goes	O
either	O
to	O
the	O
RAM	B-Architecture
(	O
random-access	B-Architecture
memory	I-Architecture
)	O
or	O
cache	O
.	O
</s>
<s>
The	O
MAR	O
register	B-General_Concept
is	O
half	O
of	O
a	O
minimal	O
interface	O
between	O
a	O
microprogram	B-Device
and	O
computer	B-General_Concept
storage	I-General_Concept
;	O
the	O
other	O
half	O
is	O
a	O
MDR	B-General_Concept
.	O
</s>
<s>
In	O
general	O
,	O
MAR	O
is	O
a	O
parallel	O
load	O
register	B-General_Concept
that	O
contains	O
the	O
next	O
memory	B-General_Concept
address	I-General_Concept
to	O
be	O
manipulated	O
,	O
for	O
example	O
the	O
next	O
address	O
to	O
be	O
read	O
or	O
written	O
.	O
</s>
