<s>
Memory-mapped	B-Architecture
I/O	I-Architecture
(	O
MMIO	B-Architecture
)	O
and	O
port-mapped	B-General_Concept
I/O	I-General_Concept
(	O
PMIO	B-Architecture
)	O
are	O
two	O
complementary	O
methods	O
of	O
performing	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
between	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
peripheral	B-Device
devices	I-Device
in	O
a	O
computer	O
.	O
</s>
<s>
An	O
alternative	O
approach	O
is	O
using	O
dedicated	O
I/O	B-Device
processors	I-Device
,	O
commonly	O
known	O
as	O
channels	B-Device
on	O
mainframe	B-Architecture
computers	I-Architecture
,	O
which	O
execute	O
their	O
own	O
instructions	O
.	O
</s>
<s>
Memory-mapped	B-Architecture
I/O	I-Architecture
uses	O
the	O
same	O
address	B-General_Concept
space	I-General_Concept
to	O
address	O
both	O
main	O
memory	O
and	O
I/O	B-General_Concept
devices	I-General_Concept
.	O
</s>
<s>
The	O
memory	O
and	O
registers	O
of	O
the	O
I/O	B-General_Concept
devices	I-General_Concept
are	O
mapped	O
to	O
(	O
associated	O
with	O
)	O
address	O
values	O
.	O
</s>
<s>
So	O
a	O
memory	O
address	O
may	O
refer	O
to	O
either	O
a	O
portion	O
of	O
physical	O
RAM	B-Architecture
,	O
or	O
instead	O
to	O
memory	O
and	O
registers	O
of	O
the	O
I/O	B-General_Concept
device	I-General_Concept
.	O
</s>
<s>
Each	O
I/O	B-General_Concept
device	I-General_Concept
monitors	O
the	O
CPU	O
's	O
address	B-Architecture
bus	I-Architecture
and	O
responds	O
to	O
any	O
CPU	O
access	O
of	O
an	O
address	O
assigned	O
to	O
that	O
device	O
,	O
connecting	O
the	O
data	B-General_Concept
bus	I-General_Concept
to	O
the	O
desired	O
device	O
's	O
hardware	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
To	O
accommodate	O
the	O
I/O	B-General_Concept
devices	I-General_Concept
,	O
some	O
areas	O
of	O
the	O
address	B-Architecture
bus	I-Architecture
used	O
by	O
the	O
CPU	O
must	O
be	O
reserved	O
for	O
I/O	B-General_Concept
and	O
must	O
not	O
be	O
available	O
for	O
normal	O
physical	O
memory	O
.	O
</s>
<s>
The	O
reservation	O
may	O
be	O
permanent	O
,	O
or	O
temporary	O
(	O
as	O
achieved	O
via	O
bank	B-General_Concept
switching	I-General_Concept
)	O
.	O
</s>
<s>
An	O
example	O
of	O
the	O
latter	O
is	O
found	O
in	O
the	O
Commodore	O
64	O
,	O
which	O
uses	O
a	O
form	O
of	O
memory	O
mapping	O
to	O
cause	O
RAM	B-Architecture
or	O
I/O	B-General_Concept
hardware	I-General_Concept
to	O
appear	O
in	O
the	O
0xD000-0xDFFF	O
range	O
.	O
</s>
<s>
Port-mapped	B-General_Concept
I/O	I-General_Concept
often	O
uses	O
a	O
special	O
class	O
of	O
CPU	O
instructions	O
designed	O
specifically	O
for	O
performing	O
I/O	B-General_Concept
,	O
such	O
as	O
the	O
in	O
and	O
out	O
instructions	O
found	O
on	O
microprocessors	B-Architecture
based	O
on	O
the	O
x86	B-Operating_System
and	O
x86-64	B-Device
architectures	O
.	O
</s>
<s>
Different	O
forms	O
of	O
these	O
two	O
instructions	O
can	O
copy	O
one	O
,	O
two	O
or	O
four	O
bytes	O
(	O
outb	O
,	O
outw	O
and	O
outl	O
,	O
respectively	O
)	O
between	O
the	O
EAX	O
register	B-General_Concept
or	O
one	O
of	O
that	O
register	B-General_Concept
's	O
subdivisions	O
on	O
the	O
CPU	O
and	O
a	O
specified	O
I/O	B-Architecture
port	I-Architecture
address	O
which	O
is	O
assigned	O
to	O
an	O
I/O	B-General_Concept
device	I-General_Concept
.	O
</s>
<s>
I/O	B-General_Concept
devices	I-General_Concept
have	O
a	O
separate	O
address	B-General_Concept
space	I-General_Concept
from	O
general	O
memory	O
,	O
either	O
accomplished	O
by	O
an	O
extra	O
"	O
I/O	B-General_Concept
"	O
pin	O
on	O
the	O
CPU	O
's	O
physical	O
interface	O
,	O
or	O
an	O
entire	O
bus	B-General_Concept
dedicated	O
to	O
I/O	B-General_Concept
.	O
</s>
<s>
Because	O
the	O
address	B-General_Concept
space	I-General_Concept
for	O
I/O	B-General_Concept
is	O
isolated	O
from	O
that	O
for	O
main	O
memory	O
,	O
this	O
is	O
sometimes	O
referred	O
to	O
as	O
isolated	O
I/O	B-General_Concept
.	O
</s>
<s>
Different	O
CPU-to-device	O
communication	O
methods	O
,	O
such	O
as	O
memory	O
mapping	O
,	O
do	O
not	O
affect	O
the	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
for	O
a	O
device	O
,	O
because	O
,	O
by	O
definition	O
,	O
DMA	O
is	O
a	O
memory-to-device	O
communication	O
method	O
that	O
bypasses	O
the	O
CPU	O
.	O
</s>
<s>
Hardware	O
interrupts	B-Application
are	O
another	O
communication	O
method	O
between	O
the	O
CPU	O
and	O
peripheral	B-Device
devices	I-Device
,	O
however	O
,	O
for	O
a	O
number	O
of	O
reasons	O
,	O
interrupts	B-Application
are	O
always	O
treated	O
separately	O
.	O
</s>
<s>
An	O
interrupt	B-Application
is	O
device-initiated	O
,	O
as	O
opposed	O
to	O
the	O
methods	O
mentioned	O
above	O
,	O
which	O
are	O
CPU-initiated	O
.	O
</s>
<s>
Lastly	O
,	O
each	O
interrupt	B-Application
line	I-Application
carries	O
only	O
one	O
bit	O
of	O
information	O
with	O
a	O
fixed	O
meaning	O
,	O
namely	O
"	O
an	O
event	O
that	O
requires	O
attention	O
has	O
occurred	O
in	O
a	O
device	O
on	O
this	O
interrupt	B-Application
line	I-Application
"	O
.	O
</s>
<s>
I/O	B-General_Concept
operations	I-General_Concept
can	O
slow	O
memory	O
access	O
if	O
the	O
address	O
and	O
data	B-General_Concept
buses	I-General_Concept
are	O
shared	O
.	O
</s>
<s>
This	O
is	O
because	O
the	O
peripheral	B-Device
device	I-Device
is	O
usually	O
much	O
slower	O
than	O
main	O
memory	O
.	O
</s>
<s>
In	O
some	O
architectures	O
,	O
port-mapped	B-General_Concept
I/O	I-General_Concept
operates	O
via	O
a	O
dedicated	O
I/O	B-General_Concept
bus	I-General_Concept
,	O
alleviating	O
the	O
problem	O
.	O
</s>
<s>
One	O
merit	O
of	O
memory-mapped	B-Architecture
I/O	I-Architecture
is	O
that	O
,	O
by	O
discarding	O
the	O
extra	O
complexity	O
that	O
port	B-Architecture
I/O	I-Architecture
brings	O
,	O
a	O
CPU	O
requires	O
less	O
internal	O
logic	O
and	O
is	O
thus	O
cheaper	O
,	O
faster	O
,	O
easier	O
to	O
build	O
,	O
consumes	O
less	O
power	O
and	O
can	O
be	O
physically	O
smaller	O
;	O
this	O
follows	O
the	O
basic	O
tenets	O
of	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computing	I-Architecture
,	O
and	O
is	O
also	O
advantageous	O
in	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
The	O
other	O
advantage	O
is	O
that	O
,	O
because	O
regular	O
memory	O
instructions	O
are	O
used	O
to	O
address	O
devices	O
,	O
all	O
of	O
the	O
CPU	O
's	O
addressing	O
modes	O
are	O
available	O
for	O
the	O
I/O	B-General_Concept
as	O
well	O
as	O
the	O
memory	O
,	O
and	O
instructions	O
that	O
perform	O
an	O
ALU	B-General_Concept
operation	O
directly	O
on	O
a	O
memory	O
operand	O
(	O
loading	O
an	O
operand	O
from	O
a	O
memory	O
location	O
,	O
storing	O
the	O
result	O
to	O
a	O
memory	O
location	O
,	O
or	O
both	O
)	O
can	O
be	O
used	O
with	O
I/O	B-General_Concept
device	I-General_Concept
registers	O
as	O
well	O
.	O
</s>
<s>
In	O
contrast	O
,	O
port-mapped	B-General_Concept
I/O	I-General_Concept
instructions	O
are	O
often	O
very	O
limited	O
,	O
often	O
providing	O
only	O
for	O
simple	O
load-and-store	O
operations	O
between	O
CPU	B-General_Concept
registers	I-General_Concept
and	O
I/O	B-Architecture
ports	I-Architecture
,	O
so	O
that	O
,	O
for	O
example	O
,	O
to	O
add	O
a	O
constant	O
to	O
a	O
port-mapped	O
device	O
register	B-General_Concept
would	O
require	O
three	O
instructions	O
:	O
read	O
the	O
port	O
to	O
a	O
CPU	B-General_Concept
register	I-General_Concept
,	O
add	O
the	O
constant	O
to	O
the	O
CPU	B-General_Concept
register	I-General_Concept
,	O
and	O
write	O
the	O
result	O
back	O
to	O
the	O
port	O
.	O
</s>
<s>
As	O
16-bit	B-Device
processors	I-Device
have	O
become	O
obsolete	O
and	O
replaced	O
with	O
32-bit	O
and	O
64-bit	B-Device
in	O
general	O
use	O
,	O
reserving	O
ranges	O
of	O
memory	O
address	B-General_Concept
space	I-General_Concept
for	O
I/O	B-General_Concept
is	O
less	O
of	O
a	O
problem	O
,	O
as	O
the	O
memory	O
address	B-General_Concept
space	I-General_Concept
of	O
the	O
processor	O
is	O
usually	O
much	O
larger	O
than	O
the	O
required	O
space	O
for	O
all	O
memory	O
and	O
I/O	B-General_Concept
devices	I-General_Concept
in	O
a	O
system	O
.	O
</s>
<s>
Therefore	O
,	O
it	O
has	O
become	O
more	O
frequently	O
practical	O
to	O
take	O
advantage	O
of	O
the	O
benefits	O
of	O
memory-mapped	B-Architecture
I/O	I-Architecture
.	O
</s>
<s>
However	O
,	O
even	O
with	O
address	B-General_Concept
space	I-General_Concept
being	O
no	O
longer	O
a	O
major	O
concern	O
,	O
neither	O
I/O	B-General_Concept
mapping	O
method	O
is	O
universally	O
superior	O
to	O
the	O
other	O
,	O
and	O
there	O
will	O
be	O
cases	O
where	O
using	O
port-mapped	B-General_Concept
I/O	I-General_Concept
is	O
still	O
preferable	O
.	O
</s>
<s>
Memory-mapped	B-Architecture
I/O	I-Architecture
is	O
preferred	O
in	O
x86-based	O
architectures	O
because	O
the	O
instructions	O
that	O
perform	O
port-based	O
I/O	B-General_Concept
are	O
limited	O
to	O
one	O
register	B-General_Concept
:	O
EAX	O
,	O
AX	O
,	O
and	O
AL	O
are	O
the	O
only	O
registers	O
that	O
data	O
can	O
be	O
moved	O
into	O
or	O
out	O
of	O
,	O
and	O
either	O
a	O
byte-sized	O
immediate	O
value	O
in	O
the	O
instruction	O
or	O
a	O
value	O
in	O
register	B-General_Concept
DX	O
determines	O
which	O
port	O
is	O
the	O
source	O
or	O
destination	O
port	O
of	O
the	O
transfer	O
.	O
</s>
<s>
Since	O
any	O
general-purpose	O
register	B-General_Concept
can	O
send	O
or	O
receive	O
data	O
to	O
or	O
from	O
memory	O
and	O
memory-mapped	B-Architecture
I/O	I-Architecture
devices	O
,	O
memory-mapped	B-Architecture
I/O	I-Architecture
uses	O
fewer	O
instructions	O
and	O
can	O
run	O
faster	O
than	O
port	B-Architecture
I/O	I-Architecture
.	O
</s>
<s>
AMD	O
did	O
not	O
extend	O
the	O
port	B-Architecture
I/O	I-Architecture
instructions	O
when	O
defining	O
the	O
x86-64	B-Device
architecture	O
to	O
support	O
64-bit	B-Device
ports	O
,	O
so	O
64-bit	B-Device
transfers	O
cannot	O
be	O
performed	O
using	O
port	B-Architecture
I/O	I-Architecture
.	O
</s>
<s>
Since	O
the	O
caches	B-General_Concept
mediate	O
accesses	O
to	O
memory	O
addresses	O
,	O
data	O
written	O
to	O
different	O
addresses	O
may	O
reach	O
the	O
peripherals	B-Device
 '	O
memory	O
or	O
registers	O
out	O
of	O
the	O
program	O
order	O
,	O
i.e.	O
</s>
<s>
if	O
software	O
writes	O
data	O
to	O
an	O
address	O
and	O
then	O
writes	O
data	O
to	O
another	O
address	O
,	O
the	O
cache	B-General_Concept
write	B-General_Concept
buffer	I-General_Concept
does	O
not	O
guarantee	O
that	O
the	O
data	O
will	O
reach	O
the	O
peripherals	B-Device
in	O
that	O
order	O
.	O
</s>
<s>
Any	O
program	O
that	O
does	O
not	O
include	O
cache-flushing	B-General_Concept
instructions	O
after	O
each	O
write	O
in	O
the	O
sequence	O
may	O
see	O
unintended	O
IO	O
effects	O
if	O
a	O
cache	B-General_Concept
system	O
optimizes	O
the	O
write	O
order	O
.	O
</s>
<s>
Writes	O
to	O
memory	O
can	O
often	O
be	O
reordered	O
to	O
reduce	O
redundancy	O
or	O
to	O
make	O
better	O
use	O
of	O
memory	O
access	O
cycles	O
without	O
changing	O
the	O
final	O
state	O
of	O
what	O
got	O
stored	O
;	O
whereas	O
,	O
the	O
same	O
optimizations	O
might	O
completely	O
change	O
the	O
meaning	O
and	O
effect	O
of	O
writes	O
to	O
memory-mapped	B-Architecture
I/O	I-Architecture
regions	O
.	O
</s>
<s>
Lack	O
of	O
foresight	O
in	O
the	O
choice	O
of	O
memory-mapped	B-Architecture
I/O	I-Architecture
regions	O
led	O
to	O
many	O
of	O
the	O
RAM-capacity	O
barriers	O
in	O
older	O
generations	O
of	O
computers	O
.	O
</s>
<s>
Designers	O
rarely	O
expected	O
machines	O
to	O
grow	O
to	O
make	O
full	O
use	O
of	O
an	O
architecture	O
's	O
theoretical	O
RAM	B-Architecture
capacity	O
,	O
and	O
thus	O
often	O
used	O
some	O
of	O
the	O
high-order	O
bits	O
of	O
the	O
address-space	O
as	O
selectors	O
for	O
memory-mapped	B-Architecture
I/O	I-Architecture
functions	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
640	O
KB	O
barrier	O
in	O
the	O
IBM	O
PC	O
and	O
derivatives	O
is	O
due	O
to	O
reserving	O
the	O
region	O
between	O
640	O
and	O
1024	O
KB	O
(	O
64k	O
segments	O
10	O
through	O
16	O
)	O
for	O
the	O
Upper	B-Device
Memory	I-Device
Area	I-Device
.	O
</s>
<s>
This	O
choice	O
initially	O
made	O
little	O
impact	O
,	O
but	O
it	O
eventually	O
limited	O
the	O
total	O
amount	O
of	O
RAM	B-Architecture
available	O
within	O
the	O
20-bit	O
available	O
address	B-General_Concept
space	I-General_Concept
.	O
</s>
<s>
The	O
3	O
GB	O
barrier	O
and	O
PCI	B-General_Concept
hole	I-General_Concept
are	O
similar	O
manifestations	O
of	O
this	O
with	O
32-bit	O
address	B-General_Concept
spaces	I-General_Concept
,	O
exacerbated	O
by	O
details	O
of	O
the	O
x86	B-Operating_System
boot	O
process	O
and	O
MMU	B-General_Concept
design	O
.	O
</s>
<s>
64-bit	B-Device
architectures	I-Device
often	O
technically	O
have	O
similar	O
issues	O
,	O
but	O
these	O
only	O
rarely	O
have	O
practical	O
consequences	O
.	O
</s>
<s>
A	O
simple	O
system	O
built	O
around	O
an	O
8-bit	O
microprocessor	B-Architecture
might	O
provide	O
16-bit	B-Device
address	O
lines	O
,	O
allowing	O
it	O
to	O
address	O
up	O
to	O
64kibibytes	O
(	O
KiB	O
)	O
of	O
memory	O
.	O
</s>
<s>
On	O
such	O
a	O
system	O
,	O
the	O
first	O
32KiB	O
of	O
address	B-General_Concept
space	I-General_Concept
may	O
be	O
allotted	O
to	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
,	O
another	O
16KiB	O
to	O
read-only	B-Device
memory	I-Device
(	O
ROM	B-Device
)	O
and	O
the	O
remainder	O
to	O
a	O
variety	O
of	O
other	O
devices	O
such	O
as	O
timers	O
,	O
counters	O
,	O
video	O
display	O
chips	O
,	O
sound	O
generating	O
devices	O
,	O
etc	O
.	O
</s>
<s>
The	O
hardware	O
of	O
the	O
system	O
is	O
arranged	O
so	O
that	O
devices	O
on	O
the	O
address	B-Architecture
bus	I-Architecture
will	O
only	O
respond	O
to	O
particular	O
addresses	O
which	O
are	O
intended	O
for	O
them	O
,	O
while	O
all	O
other	O
addresses	O
are	O
ignored	O
.	O
</s>
<s>
This	O
is	O
the	O
job	O
of	O
the	O
address	B-Device
decoding	I-Device
circuitry	I-Device
,	O
and	O
that	O
establishes	O
the	O
memory	B-General_Concept
map	I-General_Concept
of	O
the	O
system	O
.	O
</s>
<s>
As	O
a	O
result	O
,	O
system	O
's	O
memory	B-General_Concept
map	I-General_Concept
may	O
look	O
like	O
in	O
the	O
table	O
on	O
the	O
right	O
.	O
</s>
<s>
This	O
memory	B-General_Concept
map	I-General_Concept
contains	O
gaps	O
,	O
which	O
is	O
also	O
quite	O
common	O
in	O
actual	O
system	O
architectures	O
.	O
</s>
<s>
Assuming	O
the	O
fourth	O
register	B-General_Concept
of	O
the	O
video	O
controller	O
sets	O
the	O
background	O
colour	O
of	O
the	O
screen	O
,	O
the	O
CPU	O
can	O
set	O
this	O
colour	O
by	O
writing	O
a	O
value	O
to	O
the	O
memory	O
location	O
A003	O
using	O
its	O
standard	O
memory	O
write	O
instruction	O
.	O
</s>
<s>
Using	O
the	O
same	O
method	O
,	O
graphs	O
can	O
be	O
displayed	O
on	O
a	O
screen	O
by	O
writing	O
character	O
values	O
into	O
a	O
special	O
area	O
of	O
RAM	B-Architecture
within	O
the	O
video	O
controller	O
.	O
</s>
<s>
Prior	O
to	O
cheap	O
RAM	B-Architecture
that	O
enabled	O
bit-mapped	O
displays	O
,	O
this	O
character	O
cell	O
method	O
was	O
a	O
popular	O
technique	O
for	O
computer	O
video	O
displays	O
(	O
see	O
Text	B-Application
user	I-Application
interface	I-Application
)	O
.	O
</s>
<s>
1:1	O
mapping	O
of	O
unique	O
addresses	O
to	O
one	O
hardware	B-General_Concept
register	I-General_Concept
(	O
physical	O
memory	O
location	O
)	O
.	O
</s>
<s>
Involves	O
checking	O
every	O
line	O
of	O
the	O
address	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
n:1	O
mapping	O
of	O
n	O
unique	O
addresses	O
to	O
one	O
hardware	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
It	O
may	O
also	O
be	O
done	O
to	O
simplify	O
the	O
decoding	O
hardware	O
by	O
using	O
simpler	O
and	O
often	O
cheaper	O
logic	O
that	O
examines	O
only	O
some	O
address	O
lines	O
,	O
when	O
not	O
all	O
of	O
the	O
CPU	O
's	O
address	B-General_Concept
space	I-General_Concept
is	O
needed	O
.	O
</s>
<s>
Commonly	O
,	O
the	O
decoding	O
itself	O
is	O
programmable	O
,	O
so	O
the	O
system	O
can	O
reconfigure	O
its	O
own	O
memory	B-General_Concept
map	I-General_Concept
as	O
required	O
,	O
though	O
this	O
is	O
a	O
newer	O
development	O
and	O
generally	O
in	O
conflict	O
with	O
the	O
intent	O
of	O
being	O
cheaper	O
.	O
</s>
<s>
Synonyms	O
:	O
foldback	O
,	O
multiply	O
mapped	O
,	O
partially	O
mapped	O
,	O
address	O
aliasing	B-Application
.	O
</s>
<s>
This	O
is	O
done	O
with	O
devices	O
such	O
as	O
RAMs	B-Architecture
and	O
ROMs	O
that	O
have	O
a	O
sequence	O
of	O
address	O
inputs	O
,	O
and	O
with	O
peripheral	O
chips	O
that	O
have	O
a	O
similar	O
sequence	O
of	O
inputs	O
for	O
addressing	O
a	O
bank	O
of	O
registers	O
.	O
</s>
<s>
Linear	O
addressing	O
is	O
rarely	O
used	O
alone	O
(	O
only	O
when	O
there	O
are	O
few	O
devices	O
on	O
the	O
bus	B-General_Concept
,	O
as	O
using	O
purely	O
linear	O
addressing	O
for	O
more	O
than	O
one	O
device	O
usually	O
wastes	O
a	O
lot	O
of	O
address	B-General_Concept
space	I-General_Concept
)	O
but	O
instead	O
is	O
combined	O
with	O
one	O
of	O
the	O
other	O
methods	O
to	O
select	O
a	O
device	O
or	O
group	O
of	O
devices	O
within	O
which	O
the	O
linear	O
addressing	O
selects	O
a	O
single	O
register	B-General_Concept
or	O
memory	O
location	O
.	O
</s>
<s>
In	O
Windows-based	O
computers	O
,	O
memory	O
can	O
also	O
be	O
accessed	O
via	O
specific	O
drivers	O
such	O
as	O
DOLLx8KD	O
which	O
gives	O
I/O	B-General_Concept
access	O
in	O
8-	O
,	O
16	O
-	O
and	O
32-bit	O
on	O
most	O
Windows	O
platforms	O
starting	O
from	O
Windows	O
95	O
up	O
to	O
Windows	O
7	O
.	O
</s>
<s>
Installing	O
I/O	B-Architecture
port	I-Architecture
drivers	O
will	O
ensure	O
memory	O
access	O
by	O
activating	O
the	O
drivers	O
with	O
simple	O
DLL	O
calls	O
allowing	O
port	B-Architecture
I/O	I-Architecture
and	O
when	O
not	O
needed	O
,	O
the	O
driver	O
can	O
be	O
closed	O
to	O
prevent	O
unauthorized	O
access	O
to	O
the	O
I/O	B-Architecture
ports	I-Architecture
.	O
</s>
<s>
Linux	O
provides	O
the	O
utility	O
to	O
allow	O
reading	O
from	O
and	O
writing	O
to	O
MMIO	B-Architecture
addresses	O
.	O
</s>
<s>
The	O
Linux	O
kernel	O
also	O
allows	O
tracing	O
MMIO	B-Architecture
access	O
from	O
kernel	O
modules	O
(	O
drivers	O
)	O
using	O
the	O
kernel	O
's	O
mmiotrace	O
debug	O
facility	O
.	O
</s>
