<s>
Memory-level	B-Operating_System
parallelism	I-Operating_System
(	O
MLP	O
)	O
is	O
a	O
term	O
in	O
computer	B-General_Concept
architecture	I-General_Concept
referring	O
to	O
the	O
ability	O
to	O
have	O
pending	O
multiple	O
memory	B-General_Concept
operations	O
,	O
in	O
particular	O
cache	B-General_Concept
misses	O
or	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
misses	O
,	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
In	O
a	O
single	O
processor	O
,	O
MLP	O
may	O
be	O
considered	O
a	O
form	O
of	O
instruction-level	B-Operating_System
parallelism	I-Operating_System
(	O
ILP	O
)	O
.	O
</s>
<s>
However	O
,	O
ILP	O
is	O
often	O
conflated	O
with	O
superscalar	B-General_Concept
,	O
the	O
ability	O
to	O
execute	O
more	O
than	O
one	O
instruction	O
at	O
the	O
same	O
time	O
,	O
e.g.	O
</s>
<s>
a	O
processor	O
such	O
as	O
the	O
Intel	B-Device
Pentium	I-Device
Pro	I-Device
is	O
five-way	O
superscalar	B-General_Concept
,	O
with	O
the	O
ability	O
to	O
start	O
executing	O
five	O
different	O
microinstructions	O
in	O
a	O
given	O
cycle	O
,	O
but	O
it	O
can	O
handle	O
four	O
different	O
cache	B-General_Concept
misses	O
for	O
up	O
to	O
20	O
different	O
load	O
microinstructions	O
at	O
any	O
time	O
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
have	O
a	O
machine	O
that	O
is	O
not	O
superscalar	B-General_Concept
but	O
which	O
nevertheless	O
has	O
high	O
MLP	O
.	O
</s>
<s>
Arguably	O
a	O
machine	O
that	O
has	O
no	O
ILP	O
,	O
which	O
is	O
not	O
superscalar	B-General_Concept
,	O
which	O
executes	O
one	O
instruction	O
at	O
a	O
time	O
in	O
a	O
non-pipelined	O
manner	O
,	O
but	O
which	O
performs	O
hardware	O
prefetching	O
(	O
not	O
software	O
instruction-level	O
prefetching	O
)	O
exhibits	O
MLP	O
(	O
due	O
to	O
multiple	O
prefetches	O
outstanding	O
)	O
but	O
not	O
ILP	O
.	O
</s>
<s>
This	O
is	O
because	O
there	O
are	O
multiple	O
memory	B-General_Concept
operations	O
outstanding	O
,	O
but	O
not	O
instructions	O
.	O
</s>
