<s>
A	O
massively	B-General_Concept
parallel	I-General_Concept
processor	I-General_Concept
array	I-General_Concept
,	O
also	O
known	O
as	O
a	O
multi	O
purpose	O
processor	O
array	O
(	O
MPPA	O
)	O
is	O
a	O
type	O
of	O
integrated	O
circuit	O
which	O
has	O
a	O
massively	B-Operating_System
parallel	I-Operating_System
array	O
of	O
hundreds	O
or	O
thousands	O
of	O
CPUs	O
and	O
RAM	B-Architecture
memories	I-Architecture
.	O
</s>
<s>
These	O
processors	O
pass	O
work	O
to	O
one	O
another	O
through	O
a	O
reconfigurable	B-Protocol
interconnect	O
of	O
channels	O
.	O
</s>
<s>
MPPAs	O
are	O
based	O
on	O
a	O
software	O
parallel	O
programming	O
model	O
for	O
developing	O
high-performance	O
embedded	B-Architecture
system	I-Architecture
applications	O
.	O
</s>
<s>
MPPA	O
is	O
a	O
MIMD	B-Operating_System
(	O
Multiple	O
Instruction	O
streams	O
,	O
Multiple	O
Data	O
)	O
architecture	O
,	O
with	O
distributed	B-Operating_System
memory	I-Operating_System
accessed	O
locally	O
,	O
not	O
shared	O
globally	O
.	O
</s>
<s>
The	O
MPPA	O
's	O
massive	B-Operating_System
parallelism	I-Operating_System
and	O
its	O
distributed	B-Operating_System
memory	I-Operating_System
MIMD	B-Operating_System
architecture	O
distinguishes	O
it	O
from	O
multicore	B-Architecture
and	O
manycore	B-General_Concept
architectures	O
,	O
which	O
have	O
fewer	O
processors	O
and	O
an	O
SMP	B-Operating_System
or	O
other	O
shared	B-Operating_System
memory	I-Operating_System
architecture	I-Operating_System
,	O
mainly	O
intended	O
for	O
general-purpose	O
computing	O
.	O
</s>
<s>
It	O
's	O
also	O
distinguished	O
from	O
GPGPUs	B-Architecture
with	O
SIMD	B-Device
architectures	O
,	O
used	O
for	O
HPC	B-Architecture
applications	O
.	O
</s>
<s>
An	O
MPPA	O
application	O
is	O
developed	O
by	O
expressing	O
it	O
as	O
a	O
hierarchical	O
block	B-Application
diagram	I-Application
or	O
workflow	B-Operating_System
,	O
whose	O
basic	O
objects	O
run	O
in	O
parallel	O
,	O
each	O
on	O
their	O
own	O
processor	O
.	O
</s>
<s>
An	O
MPPA	O
's	O
model	O
of	O
computation	O
is	O
similar	O
to	O
a	O
Kahn	B-Application
process	I-Application
network	I-Application
or	O
communicating	O
sequential	O
processes	O
(	O
CSP	O
)	O
.	O
</s>
<s>
MPPAs	O
are	O
used	O
in	O
high-performance	O
embedded	B-Architecture
systems	I-Architecture
and	O
hardware	B-General_Concept
acceleration	I-General_Concept
of	O
desktop	B-Device
computer	I-Device
and	O
server	B-Application
applications	I-Application
,	O
such	O
as	O
video	O
compression	O
,	O
image	B-Algorithm
processing	I-Algorithm
,	O
medical	B-Application
imaging	I-Application
,	O
network	B-General_Concept
processing	I-General_Concept
,	O
software-defined	B-Architecture
radio	I-Architecture
and	O
other	O
compute-intensive	O
streaming	O
media	O
applications	O
,	O
which	O
otherwise	O
would	O
use	O
FPGA	B-Architecture
,	O
DSP	B-Architecture
and/or	O
ASIC	O
chips	O
.	O
</s>
<s>
MPPAs	O
developed	O
in	O
companies	O
include	O
ones	O
designed	O
at	O
:	O
Ambric	B-Device
,	O
PicoChip	B-General_Concept
,	O
Intel	O
,	O
IntellaSys	O
,	O
GreenArrays	O
,	O
ASOCS	B-Application
,	O
Tilera	B-Architecture
,	O
Kalray	O
,	O
Coherent	O
Logix	O
,	O
Tabula	O
,	O
and	O
Adapteva	B-Application
.	O
</s>
<s>
Aspex	O
(	O
Ericsson	O
)	O
Linedancer	O
differs	O
in	O
that	O
it	O
was	O
a	O
Massive	O
wide	O
SIMD	B-Device
Array	O
rather	O
than	O
an	O
MPPA	O
.	O
</s>
<s>
Strictly	O
speaking	O
it	O
could	O
qualify	O
as	O
SIMT	B-General_Concept
due	O
to	O
all	O
4096	O
of	O
the	O
3,000	O
gate	O
cores	O
having	O
its	O
own	O
Content-Addressable	O
Memory	O
.	O
</s>
<s>
Fabricated	O
MPPAs	O
developed	O
in	O
universities	O
include	O
:	O
36-core	O
and	O
167-core	O
Asynchronous	B-General_Concept
Array	I-General_Concept
of	I-General_Concept
Simple	I-General_Concept
Processors	I-General_Concept
(	O
AsAP	O
)	O
arrays	O
from	O
the	O
University	O
of	O
California	O
,	O
Davis	O
,	O
16-core	O
RAW	O
from	O
MIT	O
,	O
and	O
16-core	O
and	O
24-core	O
arrays	O
from	O
Fudan	O
University	O
.	O
</s>
<s>
The	O
Chinese	O
Sunway	B-Device
project	O
developed	O
their	O
own	O
260-core	O
SW26010	B-General_Concept
manycore	B-General_Concept
chip	O
for	O
the	O
TaihuLight	B-Device
supercomputer	B-Architecture
,	O
which	O
is	O
as	O
of	O
2016	O
the	O
world	O
's	O
fastest	O
supercomputer	B-Architecture
.	O
</s>
<s>
Anton	O
3	O
processors	O
,	O
designed	O
by	O
D	B-Application
.	I-Application
E	I-Application
.	I-Application
Shaw	I-Application
Research	I-Application
for	O
molecular	O
dynamics	O
simulations	O
,	O
contain	O
arrays	O
of	O
576	O
processors	O
arranged	O
in	O
a	O
12×24	O
tiled	O
grid	O
of	O
pairs	O
of	O
cores	O
;	O
a	O
routed	O
network	O
links	O
these	O
tiles	O
together	O
and	O
extends	O
off-chip	O
to	O
other	O
nodes	O
in	O
a	O
full	O
system	O
.	O
</s>
