<s>
Manycore	B-General_Concept
processors	I-General_Concept
are	O
special	O
kinds	O
of	O
multi-core	B-Architecture
processors	I-Architecture
designed	O
for	O
a	O
high	O
degree	O
of	O
parallel	B-Operating_System
processing	I-Operating_System
,	O
containing	O
numerous	O
simpler	O
,	O
independent	O
processor	O
cores	O
(	O
from	O
a	O
few	O
tens	O
of	O
cores	O
to	O
thousands	O
or	O
more	O
)	O
.	O
</s>
<s>
Manycore	B-General_Concept
processors	I-General_Concept
are	O
used	O
extensively	O
in	O
embedded	B-Architecture
computers	I-Architecture
and	O
high-performance	B-Architecture
computing	I-Architecture
.	O
</s>
<s>
Manycore	B-General_Concept
processors	I-General_Concept
are	O
distinct	O
from	O
multi-core	B-Architecture
processors	I-Architecture
in	O
being	O
optimized	O
from	O
the	O
outset	O
for	O
a	O
higher	O
degree	O
of	O
explicit	O
parallelism	B-Operating_System
,	O
and	O
for	O
higher	O
throughput	O
(	O
or	O
lower	O
power	O
consumption	O
)	O
at	O
the	O
expense	O
of	O
latency	O
and	O
lower	O
single-thread	O
performance	O
.	O
</s>
<s>
The	O
broader	O
category	O
of	O
multi-core	B-Architecture
processors	I-Architecture
,	O
by	O
contrast	O
,	O
are	O
usually	O
designed	O
to	O
efficiently	O
run	O
both	O
parallel	O
and	O
serial	O
code	O
,	O
and	O
therefore	O
place	O
more	O
emphasis	O
on	O
high	O
single-thread	O
performance	O
(	O
e.g.	O
</s>
<s>
devoting	O
more	O
silicon	O
to	O
out	B-General_Concept
of	I-General_Concept
order	I-General_Concept
execution	I-General_Concept
,	O
deeper	O
pipelines	B-General_Concept
,	O
more	O
superscalar	B-General_Concept
execution	I-General_Concept
units	O
,	O
and	O
larger	O
,	O
more	O
general	O
caches	O
)	O
,	O
and	O
shared	B-Operating_System
memory	I-Operating_System
.	O
</s>
<s>
These	O
techniques	O
devote	O
runtime	O
resources	O
toward	O
figuring	O
out	O
implicit	O
parallelism	B-Operating_System
in	O
a	O
single	O
thread	O
.	O
</s>
<s>
2	O
,	O
4	O
,	O
8	O
)	O
and	O
may	O
be	O
complemented	O
by	O
a	O
manycore	B-General_Concept
accelerator	B-General_Concept
(	O
such	O
as	O
a	O
GPU	B-Architecture
)	O
in	O
a	O
heterogeneous	O
system	O
.	O
</s>
<s>
Cache	B-General_Concept
coherency	I-General_Concept
is	O
an	O
issue	O
limiting	O
the	O
scaling	O
of	O
multicore	B-Architecture
processors	I-Architecture
.	O
</s>
<s>
Manycore	B-General_Concept
processors	I-General_Concept
may	O
bypass	O
this	O
with	O
methods	O
such	O
as	O
message	B-Architecture
passing	I-Architecture
,	O
scratchpad	B-General_Concept
memory	I-General_Concept
,	O
DMA	B-General_Concept
,	O
partitioned	B-Application
global	I-Application
address	I-Application
space	I-Application
,	O
or	O
read-only/non	O
-coherent	O
caches	O
.	O
</s>
<s>
A	O
manycore	B-General_Concept
processor	I-General_Concept
using	O
a	O
network	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
and	O
local	O
memories	O
gives	O
software	O
the	O
opportunity	O
to	O
explicitly	O
optimise	O
the	O
spatial	O
layout	O
of	O
tasks	O
(	O
e.g.	O
</s>
<s>
Manycore	B-General_Concept
processors	I-General_Concept
may	O
have	O
more	O
in	O
common	O
(	O
conceptually	O
)	O
with	O
technologies	O
originating	O
in	O
high-performance	B-Architecture
computing	I-Architecture
such	O
as	O
clusters	B-Architecture
and	O
vector	B-Operating_System
processors	I-Operating_System
.	O
</s>
<s>
GPUs	B-Architecture
may	O
be	O
considered	O
a	O
form	O
of	O
manycore	B-General_Concept
processor	I-General_Concept
having	O
multiple	O
shader	O
processing	O
units	O
,	O
and	O
only	O
being	O
suitable	O
for	O
highly	O
parallel	B-Operating_System
code	I-Operating_System
(	O
high	O
throughput	O
,	O
but	O
extremely	O
poor	O
single	O
thread	O
performance	O
)	O
.	O
</s>
<s>
A	O
number	O
of	O
computers	O
built	O
from	O
multicore	B-Architecture
processors	I-Architecture
have	O
one	O
million	O
or	O
more	O
individual	O
CPU	B-Architecture
cores	I-Architecture
.	O
</s>
<s>
Gyoukou	O
(	O
Japanese	O
:	O
暁光	O
Hepburn	O
:	O
gyōkō	O
,	O
dawn	O
light	O
)	O
,	O
a	O
supercomputer	B-Architecture
developed	O
by	O
ExaScaler	O
and	O
PEZY	B-General_Concept
Computing	I-General_Concept
,	O
with	O
20,480,000	O
processing	O
elements	O
total	O
plus	O
the	O
1,250	O
Intel	O
Xeon	O
D	O
host	O
processors	O
.	O
</s>
<s>
SpiNNaker	B-General_Concept
,	O
a	O
massively	B-Operating_System
parallel	I-Operating_System
(	O
1	O
million	O
CPU	B-Architecture
cores	I-Architecture
)	O
manycore	B-General_Concept
processor	I-General_Concept
(	O
ARM-based	O
)	O
built	O
as	O
part	O
of	O
the	O
Human	O
Brain	O
Project	O
.	O
</s>
<s>
Quite	O
a	O
few	O
supercomputers	B-Architecture
have	O
over	O
a	O
million	O
of	O
even	O
over	O
5	O
million	O
CPU	B-Architecture
cores	I-Architecture
.	O
</s>
<s>
GPUs	B-Architecture
used	O
with	O
,	O
then	O
those	O
cores	O
are	O
not	O
listed	O
in	O
the	O
core-count	O
,	O
then	O
quite	O
a	O
few	O
more	O
computers	O
would	O
hit	O
those	O
targets	O
.	O
</s>
<s>
Fugaku	B-Device
,	O
a	O
Japanese	O
supercomputer	B-Architecture
using	O
Fujitsu	B-Device
A64FX	I-Device
ARM-based	O
cores	O
,	O
7,630,848	O
in	O
total	O
.	O
</s>
<s>
Sunway	B-Device
TaihuLight	I-Device
,	O
a	O
massively	B-Operating_System
parallel	I-Operating_System
(	O
10	O
million	O
CPU	B-Architecture
cores	I-Architecture
)	O
Chinese	O
supercomputer	B-Architecture
,	O
once	O
one	O
of	O
the	O
fastest	B-Operating_System
supercomputers	I-Operating_System
in	O
the	O
world	O
,	O
using	O
a	O
custom	O
manycore	B-General_Concept
architecture	O
.	O
</s>
<s>
As	O
of	O
November	O
2018	O
,	O
it	O
was	O
the	O
world	O
's	O
third	O
fastest	B-Operating_System
supercomputer	I-Operating_System
(	O
as	O
ranked	O
by	O
the	O
TOP500	B-Operating_System
list	O
)	O
,	O
obtaining	O
its	O
performance	O
from	O
40,960	O
SW26010	B-General_Concept
manycore	B-General_Concept
processors	I-General_Concept
,	O
each	O
containing	O
256	O
cores	O
.	O
</s>
