<s>
The	O
Mano	B-Device
machine	I-Device
is	O
a	O
computer	O
theoretically	O
described	O
by	O
M	O
.	O
Morris	O
Mano	O
.	O
</s>
<s>
It	O
contains	O
a	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
,	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
,	O
and	O
an	O
input-output	O
bus	O
.	O
</s>
<s>
Its	O
limited	O
instruction	O
set	O
and	O
small	O
address	O
space	O
limit	O
it	O
to	O
use	O
as	O
a	O
Microcontroller	B-Architecture
.	O
</s>
<s>
The	O
Mano	B-Device
machine	I-Device
is	O
similar	O
in	O
many	O
respects	O
to	O
the	O
PDP-8	B-Device
,	O
such	O
as	O
the	O
same	O
address	O
space	O
,	O
only	O
one	O
accumulator	O
register	O
,	O
and	O
many	O
similar	O
instructions	O
.	O
</s>
<s>
The	O
Mano	B-Device
machine	I-Device
has	O
a	O
4096x16	O
shared	O
data/program	O
memory	O
segment	O
requiring	O
a	O
12-bit	O
address	O
bus	O
.	O
</s>
<s>
The	O
machine	O
specifications	O
include	O
a	O
finite	B-Architecture
state	I-Architecture
machine	I-Architecture
that	O
determines	O
the	O
processor	O
's	O
micro-operations	O
.	O
</s>
<s>
The	O
canonical	O
implementation	O
of	O
the	O
state	B-Architecture
machine	I-Architecture
is	O
an	O
excellent	O
candidate	O
for	O
reduction	O
,	O
and	O
can	O
also	O
be	O
re-implemented	O
as	O
a	O
pipelined	B-General_Concept
processor	I-General_Concept
.	O
</s>
