<s>
The	O
MPC5xx	B-General_Concept
family	O
of	O
processors	O
such	O
as	O
the	O
MPC555	B-General_Concept
and	O
MPC565	B-General_Concept
are	O
32-bit	O
PowerPC	B-Architecture
embedded	B-Architecture
microprocessors	I-Architecture
that	O
operate	O
between	O
40	O
and	O
66	O
MHz	O
and	O
are	O
frequently	O
used	O
in	O
automotive	O
applications	O
including	O
engine	O
and	O
transmission	O
controllers	O
.	O
</s>
<s>
Delphi	O
Corporation	O
use	O
either	O
the	O
MPC561	O
or	O
MPC565	B-General_Concept
in	O
the	O
engine	O
controllers	O
they	O
supply	O
to	O
General	O
Motors	O
,	O
with	O
nearly	O
all	O
2009	O
model	O
GM	O
North	O
America	O
vehicles	O
now	O
using	O
an	O
MPC5xx	B-General_Concept
in	O
the	O
engine	O
controller	O
.	O
</s>
<s>
Bosch	O
also	O
used	O
the	O
MPC5xx	B-General_Concept
throughout	O
the	O
ME(D )	O
-9	O
series	O
of	O
Gasoline	O
Engine	O
Controllers	O
,	O
EDC-16	O
series	O
of	O
Diesel	O
Engine	O
Controllers	O
as	O
did	O
the	O
Cummins	O
B	O
series	O
diesel	O
engine	O
ECU	B-Device
.	O
</s>
<s>
They	O
are	O
generally	O
considered	O
microcontrollers	B-Architecture
because	O
of	O
their	O
integrated	O
peripheral	O
set	O
and	O
their	O
unusual	O
architecture	B-General_Concept
:	O
no	O
MMU	B-General_Concept
,	O
large	O
on-chip	O
SRAM	B-Architecture
and	O
very	O
large	O
(	O
as	O
much	O
as	O
1	O
MB	O
)	O
low	O
latency	O
access	O
on-chip	O
flash	B-Device
memories	I-Device
,	O
which	O
means	O
their	O
architecture	B-General_Concept
is	O
tailored	O
to	O
control	O
applications	O
.	O
</s>
<s>
Instead	O
of	O
a	O
block-address	O
translation	O
and	O
a	O
hardware-driven	O
,	O
fixed-page	O
address	O
translation	O
prescribed	O
by	O
the	O
first	O
PowerPC	B-Architecture
specification	O
,	O
the	O
5xx	O
cores	O
provided	O
a	O
software-driven	O
translation	O
mechanism	O
that	O
supported	O
variable	O
page	O
sizes	O
.	O
</s>
<s>
This	O
model	O
is	O
the	O
basis	O
for	O
the	O
embedded	O
MMU	B-General_Concept
model	O
in	O
the	O
current	O
Power	B-Architecture
ISA	I-Architecture
specification	O
.	O
</s>
<s>
MPC5xx	B-General_Concept
–	O
All	O
PowerPC	B-Architecture
5xx	O
family	O
processors	O
share	O
this	O
common	O
naming	O
scheme	O
.	O
</s>
<s>
The	O
development	O
of	O
the	O
PowerPC	B-Architecture
5xx	O
family	O
is	O
discontinued	O
in	O
favour	O
for	O
the	O
more	O
flexible	O
and	O
powerful	O
PowerPC	B-Device
55xx	I-Device
family	I-Device
.	O
</s>
<s>
The	O
peripherals	O
on	O
each	O
model	O
vary	O
,	O
but	O
frequently	O
include	O
analog-to-digital	O
converters	O
(	O
ADC	O
)	O
,	O
Time	O
Processor	O
Units	O
(	O
TPU	O
)	O
,	O
GPIO	B-Architecture
,	O
and	O
UARTS/serial	B-Protocol
(	O
QSMCM	O
)	O
.	O
</s>
<s>
The	O
MPC5xx	B-General_Concept
family	O
descends	O
from	O
the	O
MPC8xx	O
PowerQUICC	B-General_Concept
family	O
core	O
,	O
which	O
means	O
it	O
uses	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
single	O
issue	O
core	O
.	O
</s>
<s>
Unlike	O
the	O
8xx	O
family	O
,	O
the	O
5xx	O
variants	O
have	O
a	O
floating	B-General_Concept
point	I-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
While	O
some	O
of	O
the	O
earlier	O
chips	O
like	O
the	O
MPC509	O
had	O
an	O
instruction	O
cache	O
,	O
the	O
recent	O
chips	O
have	O
the	O
capability	O
to	O
contain	O
large	O
amounts	O
of	O
NOR	O
flash	B-Device
memory	I-Device
on-board	O
which	O
is	O
capable	O
of	O
bursting	O
instructions	O
to	O
the	O
processor	O
.	O
</s>
<s>
Some	O
low-cost	O
chips	O
omit	O
the	O
flash	B-Device
memory	I-Device
because	O
it	O
adds	O
a	O
lot	O
of	O
die	O
area	O
,	O
driving	O
up	O
the	O
price	O
of	O
the	O
chip	O
.	O
</s>
<s>
If	O
most	O
of	O
the	O
data	O
can	O
be	O
stored	O
in	O
the	O
on-chip	O
SRAM	B-Architecture
available	O
to	O
the	O
datapath	O
of	O
the	O
processor	O
in	O
a	O
single	O
cycle	O
,	O
performance	O
can	O
be	O
quite	O
good	O
.	O
</s>
<s>
If	O
data	O
must	O
be	O
accessed	O
off-chip	O
frequently	O
,	O
performance	O
can	O
be	O
reduced	O
because	O
the	O
chip	O
cannot	O
burst	O
data	O
accesses	O
from	O
external	O
RAM	O
and	O
has	O
a	O
very	O
slow	O
bus	B-General_Concept
access	O
protocol	O
.	O
</s>
