<s>
The	O
Rise	O
mP6	B-General_Concept
was	O
a	O
superpipelined	B-General_Concept
and	O
superscalar	B-General_Concept
microprocessor	B-Architecture
designed	O
by	O
Rise	O
Technology	O
to	O
compete	O
with	O
the	O
Intel	B-General_Concept
Pentium	I-General_Concept
line	O
.	O
</s>
<s>
Rise	O
Technology	O
had	O
spent	O
5	O
years	O
developing	O
a	O
x86	B-Operating_System
compatible	I-Operating_System
microprocessor	B-Architecture
,	O
and	O
finally	O
introduced	O
it	O
in	O
November	O
1998	O
as	O
a	O
low-cost	O
,	O
low-power	O
alternative	O
for	O
the	O
Super	O
Socket	B-General_Concept
7	I-General_Concept
platform	O
,	O
that	O
allowed	O
for	O
higher	O
Front-side	B-Architecture
bus	I-Architecture
speeds	O
than	O
the	O
previous	O
Socket	B-General_Concept
7	I-General_Concept
and	O
that	O
made	O
it	O
possible	O
for	O
other	O
CPU	O
manufacturers	O
to	O
keep	O
competing	O
against	O
Intel	O
,	O
that	O
had	O
moved	O
to	O
the	O
Slot	B-Device
1	I-Device
platform	O
.	O
</s>
<s>
The	O
mP6	B-General_Concept
made	O
use	O
of	O
the	O
MMX	B-Architecture
instruction	O
set	O
and	O
had	O
three	O
MMX	B-Architecture
pipelines	O
which	O
allowed	O
the	O
CPU	O
to	O
execute	O
up	O
to	O
three	O
MMX	B-Architecture
instructions	O
in	O
a	O
single	O
cycle	O
.	O
</s>
<s>
Its	O
three	O
integer	O
units	O
made	O
it	O
possible	O
to	O
execute	O
three	O
integer	O
instructions	O
in	O
a	O
single	O
cycle	O
as	O
well	O
and	O
the	O
fully	O
pipelined	O
floating	B-Algorithm
point	I-Algorithm
unit	O
could	O
execute	O
up	O
to	O
two	O
floating-point	B-Algorithm
instructions	O
per	O
cycle	O
.	O
</s>
<s>
To	O
further	O
improve	O
the	O
performance	O
the	O
core	O
utilized	O
branch	B-General_Concept
prediction	I-General_Concept
and	O
a	O
number	O
of	O
techniques	O
to	O
resolve	O
data	B-Operating_System
dependency	I-Operating_System
conflicts	O
.	O
</s>
<s>
According	O
to	O
Rise	O
,	O
the	O
mP6	B-General_Concept
should	O
perform	O
almost	O
as	O
fast	O
as	O
Intel	B-General_Concept
Pentium	I-General_Concept
II	I-General_Concept
at	O
the	O
same	O
frequencies	O
.	O
</s>
<s>
Despite	O
its	O
innovative	O
features	O
,	O
the	O
real-life	O
performance	O
of	O
the	O
mP6	B-General_Concept
proved	O
disappointing	O
.	O
</s>
<s>
Another	O
reason	O
was	O
that	O
the	O
Rise	O
mP6	B-General_Concept
's	O
PR	O
266	O
rating	O
was	O
based	O
upon	O
the	O
old	O
Intel	B-General_Concept
Pentium	I-General_Concept
MMX	B-Architecture
,	O
while	O
its	O
main	O
competitors	O
were	O
the	O
Intel	B-Device
Celeron	I-Device
266	I-Device
,	O
the	O
IDT	B-Device
WinChip	I-Device
2-266	I-Device
and	O
the	O
AMD	O
K6-2	O
266	O
,	O
that	O
all	O
delivered	O
more	O
performance	O
in	O
most	O
benchmarks	O
and	O
applications	O
.	O
</s>
<s>
The	O
Celeron	B-Device
and	O
the	O
K6-2	O
actually	O
worked	O
at	O
266	O
MHz	O
,	O
and	O
the	O
WinChip	B-Device
2	I-Device
's	O
PR	O
rating	O
was	O
based	O
upon	O
the	O
performance	O
of	O
its	O
AMD	O
opponent	O
.	O
</s>
<s>
Silicon	O
Integrated	O
Systems	O
(	O
SiS	O
)	O
licensed	O
the	O
mP6	B-General_Concept
technology	O
,	O
and	O
used	O
it	O
in	O
the	O
SiS	O
550	O
,	O
a	O
system-on-a-chip	B-Architecture
(	O
SoC	B-Architecture
)	O
that	O
integrated	O
the	O
mP6	B-General_Concept
CPU	O
,	O
the	O
north	O
and	O
south	O
bridges	O
,	O
and	O
sound	O
and	O
video	O
on	O
a	O
single	O
chip	O
.	O
</s>
<s>
The	O
SiS	O
551	O
chip	O
was	O
also	O
marketed	O
by	O
DM&P	O
as	O
Vortex86	B-Device
(	O
M6127D	O
)	O
.	O
</s>
<s>
Later	O
DM&P	O
took	O
over	O
mP6	B-General_Concept
design	O
from	O
SiS	O
and	O
continues	O
development	O
under	O
Vortex86	B-Device
SoC	B-Architecture
product	O
line	O
.	O
</s>
<s>
DM&P	O
further	O
signed	O
an	O
agreement	O
with	O
Xcore	O
to	O
allow	O
them	O
to	O
rebrand	O
the	O
chip	O
as	O
Xcore86	B-Device
.	O
</s>
<s>
+	O
The	O
various	O
models	O
of	O
the	O
Rise	O
mP6	B-General_Concept
with	O
their	O
PR	O
rating	O
,	O
data	O
from	O
Model	O
number	O
Frequency	O
L1	O
Cache	O
FSB	B-Architecture
Mult	O
.	O
</s>
