<s>
The	O
6529	O
Single	O
Port	O
Interface	O
(	O
SPI	O
aka	O
PIO	O
)	O
was	O
an	O
integrated	O
circuit	O
made	O
by	O
MOS	B-Architecture
Technology	I-Architecture
.	O
</s>
<s>
It	O
served	O
as	O
an	O
I/O	O
controller	O
for	O
the	O
6502	B-General_Concept
family	O
of	O
microprocessors	O
,	O
providing	O
a	O
single	O
8-bit	O
digital	B-General_Concept
bidirectional	O
parallel	B-Device
I/O	B-Architecture
port	I-Architecture
.	O
</s>
<s>
Unlike	O
the	O
more	O
sophisticated	O
6522	B-Device
VIA	I-Device
and	O
6526	B-Device
CIA	I-Device
,	O
it	O
did	O
not	O
allow	O
the	O
data	O
direction	O
for	O
each	O
I/O	O
line	O
to	O
be	O
separately	O
specified	O
,	O
nor	O
did	O
it	O
support	O
serial	B-Protocol
I/O	I-Protocol
or	O
contain	O
any	O
timer	B-Device
capabilities	O
.	O
</s>
<s>
The	O
form	O
factor	O
was	O
a	O
JEDEC-standard	O
20-pin	O
ceramic	O
or	O
plastic	O
DIP	B-Algorithm
.	O
</s>
