<s>
The	O
MOS	B-General_Concept
Technology	I-General_Concept
8502	I-General_Concept
is	O
an	O
8-bit	O
microprocessor	B-Architecture
designed	O
by	O
MOS	B-Architecture
Technology	I-Architecture
and	O
used	O
in	O
the	O
Commodore	B-Device
128	I-Device
(	O
C128	O
)	O
.	O
</s>
<s>
It	O
is	O
an	O
improved	O
version	O
of	O
the	O
MOS	B-General_Concept
6510	I-General_Concept
used	O
in	O
the	O
Commodore	O
64	O
(	O
C64	O
)	O
.	O
</s>
<s>
The	O
8502	B-General_Concept
allows	O
the	O
C128	O
to	O
run	O
at	O
double	O
the	O
clock	O
rate	O
of	O
the	O
C64	O
with	O
some	O
limitations	O
.	O
</s>
<s>
Common	O
random	B-Architecture
access	I-Architecture
memory	I-Architecture
(	O
RAM	B-Architecture
)	O
of	O
the	O
Commodore	O
C64-era	O
allowed	O
accesses	O
at	O
2MHz	O
.	O
</s>
<s>
If	O
the	O
CPU	O
and	O
display	B-General_Concept
chip	I-General_Concept
both	O
shared	O
the	O
same	O
memory	O
to	O
communicate	O
,	O
which	O
was	O
the	O
common	O
solution	O
in	O
the	O
era	O
when	O
RAM	B-Architecture
was	O
expensive	O
,	O
then	O
one	O
would	O
normally	O
have	O
to	O
have	O
the	O
CPU	O
and	O
display	B-General_Concept
chip	I-General_Concept
chips	O
mediate	O
access	O
to	O
the	O
bus	O
so	O
that	O
only	O
one	O
of	O
them	O
used	O
it	O
at	O
a	O
time	O
,	O
generally	O
by	O
having	O
one	O
pause	O
the	O
other	O
.	O
</s>
<s>
That	O
meant	O
the	O
display	B-General_Concept
chip	I-General_Concept
could	O
access	O
memory	O
during	O
alternating	O
clock	O
phases	O
without	O
having	O
to	O
pause	O
the	O
CPU	O
.	O
</s>
<s>
In	O
the	O
original	O
C64	O
,	O
this	O
timing	O
trick	O
was	O
used	O
to	O
allow	O
the	O
VIC-II	O
to	O
interleave	O
its	O
access	O
to	O
main	O
memory	O
with	O
that	O
of	O
the	O
6510	B-General_Concept
.	O
</s>
<s>
The	O
8502	B-General_Concept
is	O
mostly	O
a	O
conversion	O
of	O
the	O
original	O
6502	O
to	O
be	O
fabricated	O
on	O
Intel	O
's	O
HMOS-II	O
process	O
,	O
introduced	O
in	O
1979	O
and	O
available	O
for	O
3rd	O
party	O
use	O
.	O
</s>
<s>
With	O
the	O
move	O
to	O
the	O
HMOS	O
process	O
,	O
most	O
of	O
the	O
8502s	B-General_Concept
were	O
capable	O
of	O
running	O
at	O
2MHz	O
,	O
the	O
equivalent	O
of	O
the	O
6502B	O
.	O
</s>
<s>
Changing	O
the	O
running	O
speed	O
of	O
a	O
6502-based	O
processor	O
is	O
as	O
simple	O
as	O
changing	O
the	O
input	O
clock	O
signal	O
,	O
which	O
meant	O
the	O
8502	B-General_Concept
could	O
easily	O
switch	O
between	O
2MHz	O
and	O
the	O
6510	B-General_Concept
's	O
1MHz	O
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
the	O
8502	B-General_Concept
could	O
only	O
run	O
at	O
double-speed	O
full-time	O
when	O
being	O
used	O
with	O
the	O
80-column	O
VDC	O
in	O
the	O
C128	O
,	O
which	O
had	O
separate	O
memory	O
for	O
the	O
display	O
that	O
was	O
not	O
being	O
directly	O
accessed	O
by	O
the	O
CPU	O
.	O
</s>
<s>
A	O
smaller	O
speed	O
gain	O
,	O
about	O
35%	O
,	O
was	O
also	O
possible	O
while	O
keeping	O
the	O
VIC	O
display	O
active	O
by	O
switching	O
the	O
CPU	O
to	O
2MHz	O
only	O
while	O
the	O
VIC	O
is	O
drawing	O
the	O
empty	O
border	O
along	O
the	O
top	O
and	O
bottom	O
of	O
the	O
screen	O
,	O
since	O
the	O
VIC	O
performs	O
no	O
RAM	B-Architecture
access	O
during	O
that	O
time	O
.	O
</s>
<s>
The	O
pinout	O
is	O
slightly	O
different	O
than	O
the	O
6510	B-General_Concept
.	O
</s>
<s>
The	O
8502	B-General_Concept
has	O
an	O
extra	O
I/O	O
-pin	O
(	O
the	O
built-in	O
I/O	O
port	O
mapped	O
to	O
addresses	O
0	O
and	O
1	O
is	O
extended	O
from	O
6	O
to	O
7	O
bits	O
)	O
and	O
lacks	O
the	O
ϕ2-pin	O
that	O
the	O
6510	B-General_Concept
had	O
.	O
</s>
<s>
The	O
8502	B-General_Concept
family	O
also	O
includes	O
the	O
MOS	O
7501	O
,	O
8500	O
and	O
8501	O
.	O
</s>
