<s>
The	O
MOS	B-Device
Technology	I-Device
6522	I-Device
Versatile	B-Device
Interface	I-Device
Adapter	I-Device
(	O
VIA	O
)	O
is	O
an	O
integrated	O
circuit	O
that	O
was	O
designed	O
and	O
manufactured	O
by	O
MOS	B-Architecture
Technology	I-Architecture
as	O
an	O
I/O	B-Architecture
port	I-Architecture
controller	O
for	O
the	O
6502	B-General_Concept
family	O
of	O
microprocessors	O
.	O
</s>
<s>
It	O
provides	O
two	O
bidirectional	O
8-bit	O
parallel	O
I/O	B-Architecture
ports	I-Architecture
,	O
two	O
16-bit	O
timers	O
(	O
one	O
of	O
which	O
can	O
also	O
operate	O
as	O
an	O
event	O
counter	O
)	O
,	O
and	O
an	O
8-bit	O
shift	B-General_Concept
register	I-General_Concept
for	O
serial	B-Protocol
communications	I-Protocol
or	O
data	O
conversion	O
between	O
serial	O
and	O
parallel	O
forms	O
.	O
</s>
<s>
The	O
direction	O
of	O
each	O
bit	O
of	O
the	O
two	O
I/O	B-Architecture
ports	I-Architecture
can	O
be	O
individually	O
programmed	O
.	O
</s>
<s>
In	O
addition	O
to	O
being	O
manufactured	O
by	O
MOS	B-Architecture
Technology	I-Architecture
,	O
the	O
6522	B-Device
was	O
second	O
sourced	O
by	O
other	O
companies	O
including	O
Rockwell	O
and	O
Synertek	O
.	O
</s>
<s>
The	O
6522	B-Device
was	O
widely	O
used	O
in	O
computers	O
of	O
the	O
1980s	O
,	O
particularly	O
Commodore	O
's	O
machines	O
,	O
and	O
was	O
also	O
a	O
central	O
part	O
of	O
the	O
designs	O
of	O
the	O
Apple	B-Device
III	I-Device
,	O
Oric-1	O
and	O
Oric	O
Atmos	O
,	O
BBC	B-Device
Micro	I-Device
,	O
Victor	O
9000/Sirius	O
1	O
and	O
Apple	B-Device
Macintosh	I-Device
.	O
</s>
<s>
Video	O
game	O
platforms	O
such	O
as	O
the	O
Vectrex	B-Operating_System
also	O
used	O
the	O
6522	B-Device
,	O
as	O
did	O
the	O
1984	O
through	O
1989	O
Corvette	O
digital	O
dash	O
cluster	O
.	O
</s>
<s>
A	O
high	O
speed	O
,	O
CMOS	B-Device
version	I-Device
,	O
the	O
W65C22	B-Device
,	O
is	O
produced	O
by	O
the	O
Western	O
Design	O
Center	O
(	O
WDC	O
)	O
.	O
</s>
<s>
The	O
VIA	O
contains	O
20	O
I/O	O
lines	O
,	O
which	O
are	O
organised	O
into	O
two	O
8-bit	O
bidirectional	O
ports	O
(	O
or	O
16	O
general-purpose	O
I/O	O
lines	O
)	O
and	O
four	O
control	O
lines	O
(	O
for	O
handshaking	B-Protocol
and	O
interrupt	B-Application
generation	O
)	O
.	O
</s>
<s>
The	O
control	O
lines	O
can	O
be	O
programmed	O
to	O
generate	O
an	O
interrupt	B-Application
when	O
activated	O
(	O
all	O
four	O
)	O
,	O
latch	B-General_Concept
the	O
corresponding	O
I/O	B-Architecture
port	I-Architecture
(	O
CA1	O
and	O
CB1	O
)	O
,	O
automatically	O
generate	O
handshaking	B-Protocol
signals	O
for	O
devices	O
on	O
the	O
I/O	B-Architecture
ports	I-Architecture
,	O
or	O
operate	O
as	O
plain	O
program-controlled	O
outputs	O
(	O
CA2	O
and	O
CB2	O
)	O
.	O
</s>
<s>
CB1	O
and	O
CB2	O
are	O
also	O
used	O
as	O
the	O
clock	O
input	O
and	O
the	O
data	O
line	O
for	O
the	O
shift	B-General_Concept
register	I-General_Concept
,	O
precluding	O
their	O
use	O
for	O
other	O
functions	O
while	O
the	O
shift	B-General_Concept
register	I-General_Concept
is	O
enabled	O
.	O
</s>
<s>
Each	O
can	O
be	O
used	O
in	O
one-shot	O
(	O
monostable	O
)	O
"	O
interval	O
timer	O
"	O
mode	O
;	O
timer	O
1	O
can	O
also	O
be	O
used	O
in	O
"	O
free-running	O
"	O
(	O
divider/square	O
wave	O
)	O
mode	O
,	O
in	O
which	O
the	O
timer	O
is	O
automatically	O
reloaded	O
with	O
the	O
initial	O
count	O
when	O
it	O
reaches	O
zero	O
,	O
and	O
timer	O
2	O
can	O
also	O
be	O
used	O
in	O
"	O
pulse	O
counting	O
"	O
mode	O
,	O
in	O
which	O
the	O
timer	O
will	O
count	O
the	O
high-to-low	O
state	O
transitions	O
of	O
pin	O
PB6	O
(	O
the	O
7th	O
bit	O
of	O
parallel	O
I/O	B-Architecture
port	I-Architecture
B	O
)	O
.	O
</s>
<s>
In	O
the	O
one-shot	O
mode	O
,	O
each	O
timer	O
continues	O
free-running	O
so	O
that	O
the	O
time	O
since	O
zero	O
was	O
reached	O
can	O
be	O
determined	O
,	O
but	O
no	O
further	O
interrupt	B-Application
is	O
issued	O
until	O
the	O
timer	O
is	O
restarted	O
.	O
</s>
<s>
Each	O
timer	O
can	O
generate	O
an	O
interrupt	B-Application
when	O
it	O
reaches	O
zero	O
,	O
and	O
timer	O
1	O
can	O
also	O
output	O
pulses	O
(	O
in	O
the	O
interval	O
timer	O
mode	O
)	O
or	O
square	O
waves	O
(	O
in	O
the	O
free-running	O
mode	O
)	O
on	O
pin	O
PB7	O
(	O
the	O
8th	O
bit	O
of	O
port	O
B	O
)	O
.	O
</s>
<s>
Timer	O
2	O
can	O
be	O
used	O
to	O
provide	O
the	O
clock	O
frequency	O
for	O
the	O
shift	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
A	O
useful	O
feature	O
of	O
the	O
free-running	O
mode	O
is	O
that	O
the	O
16-bit	O
counter	O
latch	B-General_Concept
can	O
be	O
loaded	O
with	O
a	O
new	O
count	O
without	O
reloading	O
the	O
counter	O
,	O
so	O
that	O
it	O
will	O
load	O
the	O
new	O
count	O
only	O
after	O
the	O
current	O
count	O
reaches	O
zero	O
,	O
seamlessly	O
changing	O
the	O
output	O
frequency	O
.	O
</s>
<s>
This	O
feature	O
of	O
timer	O
1	O
,	O
combined	O
with	O
its	O
ability	O
to	O
output	O
to	O
pin	O
PB7	O
,	O
can	O
be	O
used	O
to	O
generate	O
complex	O
waveforms	O
,	O
for	O
example	O
pulse-width	B-Algorithm
modulation	I-Algorithm
signals	O
,	O
frequency	O
sweeps	O
,	O
or	O
bi-phase	O
or	O
FM-encoded	O
serial	O
bit	O
streams	O
.	O
</s>
<s>
The	O
VIA	O
's	O
shift	B-General_Concept
register	I-General_Concept
is	O
bidirectional	O
,	O
8	O
bits	O
wide	O
,	O
and	O
can	O
run	O
from	O
either	O
a	O
timer-generated	O
clock	O
(	O
from	O
timer	O
2	O
)	O
,	O
the	O
CPU	O
clock	O
,	O
or	O
an	O
external	O
source	O
on	O
line	O
CB1	O
.	O
</s>
<s>
The	O
serial	O
input/output	O
is	O
on	O
line	O
,	O
and	O
can	O
also	O
be	O
programmed	O
to	O
output	O
a	O
bit	O
clock	O
for	O
external	O
clocked	B-Architecture
serial	I-Architecture
devices	O
.	O
</s>
<s>
The	O
NMOS	O
6522	B-Device
has	O
an	O
open	O
drain	O
IRQ	O
output	O
that	O
may	O
be	O
used	O
in	O
wired-OR	O
interrupt	B-Application
circuits	O
.	O
</s>
<s>
The	O
WDC	O
W65C22S	O
,	O
in	O
contrast	O
,	O
has	O
a	O
totem	O
pole	O
IRQ	O
output	O
that	O
must	O
be	O
isolated	O
from	O
a	O
wired-OR	O
circuit	O
by	O
a	O
Schottky	O
diode	O
,	O
due	O
to	O
the	O
fact	O
that	O
the	O
totem	O
pole	O
output	O
actively	O
drives	O
the	O
IRQ	O
pin	O
high	O
when	O
the	O
W65C22S	O
is	O
not	O
interrupting	B-Application
.	O
</s>
<s>
As	O
a	O
workaround	O
,	O
put	O
the	O
external	O
clock	O
signal	O
into	O
the	O
input	O
of	O
a	O
74AC74	O
flip-flop	B-General_Concept
,	O
run	O
the	O
flop	O
's	O
output	O
to	O
the	O
6522	B-Device
's	O
pin	O
,	O
and	O
clock	O
the	O
flip-flop	B-General_Concept
with	O
ϕ0	O
or	O
ϕ2	O
.	O
</s>
<s>
The	O
serial	O
shift	B-General_Concept
register	I-General_Concept
bug	O
was	O
corrected	O
in	O
the	O
California	O
Micro	O
Devices	O
CMD	O
G65SC22	O
,	O
the	O
Western	O
Design	O
Center	O
W65C22	B-Device
and	O
in	O
the	O
MOS	B-Device
6526	I-Device
,	O
the	O
latter	O
device	O
which	O
Commodore	O
used	O
in	O
place	O
of	O
the	O
6522	B-Device
from	O
the	O
Commodore	O
64	O
onwards	O
.	O
</s>
<s>
Aside	O
from	O
the	O
aforementioned	O
shift	B-General_Concept
register	I-General_Concept
bug	O
,	O
there	O
was	O
a	O
potential	O
register	O
corruption	O
problem	O
that	O
usually	O
only	O
occurred	O
in	O
systems	O
using	O
the	O
6522	B-Device
with	O
a	O
microprocessor	O
having	O
a	O
non-6502	O
bus	B-General_Concept
architecture	O
,	O
such	O
as	O
a	O
Motorola	B-Device
68000	I-Device
.	O
</s>
<s>
If	O
the	O
address	O
lines	O
changed	O
while	O
chip	B-Architecture
select	I-Architecture
was	O
low	O
(	O
inactive	O
)	O
but	O
the	O
ϕ2	O
clock	O
input	O
was	O
high	O
(	O
active	O
)	O
,	O
register	O
contents	O
could	O
be	O
changed	O
despite	O
the	O
fact	O
that	O
the	O
chip	O
was	O
not	O
selected	O
.	O
</s>
<s>
This	O
was	O
fixed	O
in	O
some	O
but	O
not	O
all	O
of	O
the	O
CMOS	B-Device
versions	O
.	O
</s>
