<s>
The	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MOSFET	B-Architecture
,	O
MOS-FET	B-Architecture
,	O
or	O
MOS	B-Architecture
FET	I-Architecture
)	O
is	O
a	B-General_Concept
type	O
of	O
field-effect	O
transistor	B-Application
(	O
FET	O
)	O
,	O
most	O
commonly	O
fabricated	O
by	O
the	O
controlled	B-Algorithm
oxidation	I-Algorithm
of	O
silicon	O
.	O
</s>
<s>
A	B-General_Concept
metal-insulator-semiconductor	B-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
MISFET	B-Architecture
)	O
is	O
a	B-General_Concept
term	O
almost	O
synonymous	O
with	O
MOSFET	B-Architecture
.	O
</s>
<s>
Another	O
synonym	O
is	O
IGFET	B-Architecture
for	O
insulated-gate	B-Architecture
field-effect	I-Architecture
transistor	I-Architecture
.	O
</s>
<s>
The	O
basic	O
principle	O
of	O
the	O
field-effect	O
transistor	B-Application
was	O
first	O
patented	O
by	O
Julius	O
Edgar	O
Lilienfeld	O
in	O
1925	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.6	O
|Two	O
power	O
MOSFETs	B-Architecture
in	O
D2PAK	B-Algorithm
surface-mount	O
packages	O
.	O
</s>
<s>
Operating	O
as	O
switches	O
,	O
each	O
of	O
these	O
components	O
can	O
sustain	O
a	B-General_Concept
blocking	O
voltage	O
of	O
120V	O
in	O
the	O
off	O
state	O
,	O
and	O
can	O
conduct	O
a	B-General_Concept
con­ti­nuous	O
current	O
of	O
30	O
A	B-General_Concept
in	O
the	O
on	O
state	O
,	O
dissipating	O
up	O
to	O
about	O
100	O
W	O
and	O
controlling	O
a	B-General_Concept
load	O
of	O
over	O
2000	O
W	O
.	O
A	B-General_Concept
matchstick	O
is	O
pictured	O
for	O
scale	O
.	O
</s>
<s>
The	O
main	O
advantage	O
of	O
a	B-General_Concept
MOSFET	B-Architecture
is	O
that	O
it	O
requires	O
almost	O
no	O
input	O
current	O
to	O
control	O
the	O
load	O
current	O
,	O
when	O
compared	O
with	O
bipolar	O
transistors	B-Application
(	O
bipolar	O
junction	O
transistors/BJTs	O
)	O
.	O
</s>
<s>
In	O
an	O
enhancement	B-Algorithm
mode	I-Algorithm
MOSFET	B-Architecture
,	O
voltage	O
applied	O
to	O
the	O
gate	O
terminal	O
increases	O
the	O
conductivity	O
of	O
the	O
device	O
.	O
</s>
<s>
In	O
depletion	B-Algorithm
mode	I-Algorithm
transistors	B-Application
,	O
voltage	O
applied	O
at	O
the	O
gate	O
reduces	O
the	O
conductivity	O
.	O
</s>
<s>
The	O
"	O
metal	O
"	O
in	O
the	O
name	O
MOSFET	B-Architecture
is	O
sometimes	O
a	B-General_Concept
misnomer	O
,	O
because	O
the	O
gate	O
material	O
can	O
be	O
a	B-General_Concept
layer	O
of	O
polysilicon	O
(	O
polycrystalline	O
silicon	O
)	O
.	O
</s>
<s>
Similarly	O
,	O
"	O
oxide	O
"	O
in	O
the	O
name	O
can	O
also	O
be	O
a	B-General_Concept
misnomer	O
,	O
as	O
different	O
dielectric	O
materials	O
are	O
used	O
with	O
the	O
aim	O
of	O
obtaining	O
strong	O
channels	O
with	O
smaller	O
applied	O
voltages	O
.	O
</s>
<s>
The	O
MOSFET	B-Architecture
is	O
by	O
far	O
the	O
most	O
common	O
transistor	B-Application
in	O
digital	O
circuits	O
,	O
as	O
billions	O
may	O
be	O
included	O
in	O
a	B-General_Concept
memory	O
chip	O
or	O
microprocessor	B-Architecture
.	O
</s>
<s>
Since	O
MOSFETs	B-Architecture
can	O
be	O
made	O
with	O
either	O
p-type	O
or	O
n-type	O
semiconductors	O
,	O
complementary	O
pairs	O
of	O
MOS	B-Architecture
transistors	I-Architecture
can	O
be	O
used	O
to	O
make	O
switching	O
circuits	O
with	O
very	O
low	O
power	O
consumption	O
,	O
in	O
the	O
form	O
of	O
CMOS	B-Device
logic	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.6	O
|A	O
cross-section	O
through	O
an	O
nMOSFET	O
when	O
the	O
gate	O
voltage	O
VGS	O
is	O
below	O
the	O
threshold	O
for	O
making	O
a	B-General_Concept
conductive	O
channel	O
;	O
there	O
is	O
little	O
or	O
no	O
conduction	O
between	O
the	O
terminals	O
drain	O
and	O
source	O
;	O
the	O
switch	O
is	O
off	O
.	O
</s>
<s>
When	O
the	O
gate	O
is	O
more	O
positive	O
,	O
it	O
attracts	O
electrons	O
,	O
inducing	O
an	O
n-type	O
conductive	O
channel	O
in	O
the	O
substrate	B-Architecture
below	O
the	O
oxide	O
,	O
which	O
allows	O
electrons	O
to	O
flow	O
between	O
the	O
n-doped	O
terminals	O
;	O
the	O
switch	O
is	O
on	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.6	O
|Simulation	O
of	O
formation	O
of	O
inversion	O
channel	O
(	O
electron	O
density	O
)	O
and	O
attainment	O
of	O
threshold	O
vol­tage	O
(	O
IV	O
)	O
in	O
a	B-General_Concept
nanowire	O
MOSFET	B-Architecture
.	O
</s>
<s>
The	O
basic	O
principle	O
of	O
this	O
kind	O
of	O
transistor	B-Application
was	O
first	O
patented	O
by	O
Julius	O
Edgar	O
Lilienfeld	O
in	O
1925	O
.	O
</s>
<s>
The	O
structure	O
resembling	O
the	O
MOS	B-Architecture
transistor	I-Architecture
was	O
proposed	O
by	O
Bell	O
scientists	O
William	O
Shockley	O
,	O
John	O
Bardeen	O
and	O
Walter	O
Houser	O
Brattain	O
,	O
during	O
their	O
investigation	O
that	O
led	O
to	O
discovery	O
of	O
the	O
transistor	B-Application
effect	O
.	O
</s>
<s>
In	O
1955	O
Carl	O
Frosch	O
and	O
L	O
.	O
Derick	O
accidentally	O
grew	O
a	B-General_Concept
layer	O
of	O
silicon	O
dioxide	O
over	O
the	O
silicon	B-Architecture
wafer	I-Architecture
.	O
</s>
<s>
Further	O
research	O
showed	O
that	O
silicon	O
dioxide	O
could	O
prevent	O
dopants	O
from	O
diffusing	O
into	O
the	O
silicon	B-Architecture
wafer	I-Architecture
.	O
</s>
<s>
In	O
1960s	O
,	O
following	O
this	O
research	O
Mohamed	O
Atalla	O
and	O
Dawon	O
Kahng	O
demonstrated	O
a	B-General_Concept
device	O
that	O
had	O
the	O
structure	O
of	O
a	B-General_Concept
modern	O
MOS	B-Architecture
transistor	I-Architecture
.	O
</s>
<s>
The	O
principles	O
behind	O
the	O
device	O
were	O
the	O
same	O
as	O
the	O
ones	O
that	O
were	O
tried	O
by	O
Bardeen	O
,	O
Shockley	O
and	O
Brattain	O
in	O
their	O
unsuccessful	O
attempt	O
to	O
build	O
a	B-General_Concept
surface	O
field-effect	O
device	O
.	O
</s>
<s>
The	O
device	O
was	O
about	O
100	O
times	O
slower	O
than	O
contemporary	O
bipolar	O
transistors	B-Application
and	O
was	O
initially	O
seen	O
as	O
inferior	O
.	O
</s>
<s>
Nevertheless	O
Kahng	O
pointed	O
out	O
several	O
advantages	O
of	O
the	O
device	O
,	O
notably	O
ease	O
of	O
fabrication	B-Architecture
and	O
its	O
application	O
in	O
integrated	O
circuits	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.2	O
|Photomicrograph	O
of	O
two	O
metal-gate	O
MOSFETs	B-Architecture
in	O
a	B-General_Concept
test	O
pattern	O
.	O
</s>
<s>
Recently	O
,	O
some	O
chip	O
manufacturers	O
,	O
most	O
notably	O
IBM	O
and	O
Intel	O
,	O
have	O
started	O
using	O
an	O
alloy	O
of	O
silicon	O
and	O
germanium	O
(	O
SiGe	O
)	O
in	O
MOSFET	B-Architecture
channels	O
.	O
</s>
<s>
Unfortunately	O
,	O
many	O
semiconductors	O
with	O
better	O
electrical	O
properties	O
than	O
silicon	O
,	O
such	O
as	O
gallium	O
arsenide	O
,	O
do	O
not	O
form	O
good	O
semiconductor-to-insulator	O
interfaces	O
,	O
and	O
thus	O
are	O
not	O
suitable	O
for	O
MOSFETs	B-Architecture
.	O
</s>
<s>
To	O
overcome	O
the	O
increase	O
in	O
power	O
consumption	O
due	O
to	O
gate	O
current	O
leakage	O
,	O
a	B-General_Concept
high-κ	B-Algorithm
dielectric	I-Algorithm
is	O
used	O
instead	O
of	O
silicon	O
dioxide	O
for	O
the	O
gate	O
insulator	O
,	O
while	O
polysilicon	O
is	O
replaced	O
by	O
metal	O
gates	O
(	O
e.g.	O
</s>
<s>
The	O
gate	O
is	O
separated	O
from	O
the	O
channel	O
by	O
a	B-General_Concept
thin	O
insulating	O
layer	O
,	O
traditionally	O
of	O
silicon	O
dioxide	O
and	O
later	O
of	O
silicon	O
oxynitride	O
.	O
</s>
<s>
Some	O
companies	O
have	O
started	O
to	O
introduce	O
a	B-General_Concept
high-κ	B-Algorithm
dielectric	I-Algorithm
and	O
metal	O
gate	O
combination	O
in	O
the	O
45	B-Algorithm
nanometer	I-Algorithm
node	O
.	O
</s>
<s>
When	O
a	B-General_Concept
voltage	O
is	O
applied	O
between	O
the	O
gate	O
and	O
body	O
terminals	O
,	O
the	O
electric	O
field	O
generated	O
penetrates	O
through	O
the	O
oxide	O
and	O
creates	O
an	O
inversion	O
layer	O
or	O
channel	O
at	O
the	O
semiconductor-insulator	O
interface	O
.	O
</s>
<s>
The	O
inversion	O
layer	O
provides	O
a	B-General_Concept
channel	O
through	O
which	O
current	O
can	O
pass	O
between	O
source	O
and	O
drain	O
terminals	O
.	O
</s>
<s>
This	O
is	O
known	O
as	O
enhancement	B-Algorithm
mode	I-Algorithm
.	O
</s>
<s>
The	O
traditional	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
MOS	O
)	O
structure	O
is	O
obtained	O
by	O
growing	O
a	B-General_Concept
layer	O
of	O
silicon	O
dioxide	O
(	O
)	O
on	O
top	O
of	O
a	B-General_Concept
silicon	O
substrate	B-Architecture
,	O
commonly	O
by	O
thermal	B-Algorithm
oxidation	I-Algorithm
and	O
depositing	O
a	B-General_Concept
layer	O
of	O
metal	O
or	O
polycrystalline	O
silicon	O
(	O
the	O
latter	O
is	O
commonly	O
used	O
)	O
.	O
</s>
<s>
As	O
the	O
silicon	O
dioxide	O
is	O
a	B-General_Concept
dielectric	O
material	O
,	O
its	O
structure	O
is	O
equivalent	O
to	O
a	B-General_Concept
planar	O
capacitor	O
,	O
with	O
one	O
of	O
the	O
electrodes	O
replaced	O
by	O
a	B-General_Concept
semiconductor	O
.	O
</s>
<s>
When	O
a	B-General_Concept
voltage	O
is	O
applied	O
across	O
a	B-General_Concept
MOS	O
structure	O
,	O
it	O
modifies	O
the	O
distribution	O
of	O
charges	O
in	O
the	O
semiconductor	O
.	O
</s>
<s>
If	O
we	O
consider	O
a	B-General_Concept
p-type	O
semiconductor	O
(	O
with	O
the	O
density	O
of	O
acceptors	O
,	O
p	O
the	O
density	O
of	O
holes	O
;	O
p	O
=	O
NA	O
in	O
neutral	O
bulk	O
)	O
,	O
a	B-General_Concept
positive	O
voltage	O
,	O
,	O
from	O
gate	O
to	O
body	O
(	O
see	O
figure	O
)	O
creates	O
a	B-General_Concept
depletion	B-Algorithm
layer	I-Algorithm
by	O
forcing	O
the	O
positively	O
charged	O
holes	O
away	O
from	O
the	O
gate-insulator/semiconductor	O
interface	O
,	O
leaving	O
exposed	O
a	B-General_Concept
carrier-free	O
region	O
of	O
immobile	O
,	O
negatively	O
charged	O
acceptor	O
ions	O
(	O
see	O
doping	B-Algorithm
(	O
semiconductor	O
)	O
)	O
.	O
</s>
<s>
If	O
is	O
high	O
enough	O
,	O
a	B-General_Concept
high	O
concentration	O
of	O
negative	O
charge	O
carriers	O
forms	O
in	O
an	O
inversion	O
layer	O
located	O
in	O
a	B-General_Concept
thin	O
layer	O
next	O
to	O
the	O
interface	O
between	O
the	O
semiconductor	O
and	O
the	O
insulator	O
.	O
</s>
<s>
When	O
the	O
voltage	O
between	O
transistor	B-Application
gate	O
and	O
source	O
(	O
VGS	O
)	O
exceeds	O
the	O
threshold	O
voltage	O
(	O
Vth	O
)	O
,	O
the	O
difference	O
is	O
known	O
as	O
overdrive	O
voltage	O
.	O
</s>
<s>
This	O
structure	O
with	O
p-type	O
body	O
is	O
the	O
basis	O
of	O
the	O
n-type	O
MOSFET	B-Architecture
,	O
which	O
requires	O
the	O
addition	O
of	O
n-type	O
source	O
and	O
drain	O
regions	O
.	O
</s>
<s>
The	O
MOS	O
capacitor	O
structure	O
is	O
the	O
heart	O
of	O
the	O
MOSFET	B-Architecture
.	O
</s>
<s>
Consider	O
a	B-General_Concept
MOS	O
capacitor	O
where	O
the	O
silicon	O
base	O
is	O
of	O
p-type	O
.	O
</s>
<s>
If	O
a	B-General_Concept
positive	O
voltage	O
is	O
applied	O
at	O
the	O
gate	O
,	O
holes	O
which	O
are	O
at	O
the	O
surface	O
of	O
the	O
p-type	O
substrate	B-Architecture
will	O
be	O
repelled	O
by	O
the	O
electric	O
field	O
generated	O
by	O
the	O
voltage	O
applied	O
.	O
</s>
<s>
At	O
first	O
,	O
the	O
holes	O
will	O
simply	O
be	O
repelled	O
and	O
what	O
will	O
remain	O
on	O
the	O
surface	O
will	O
be	O
immobile	O
(	O
negative	O
)	O
atoms	O
of	O
the	O
acceptor	O
type	O
,	O
which	O
creates	O
a	B-General_Concept
depletion	B-Algorithm
region	I-Algorithm
on	O
the	O
surface	O
.	O
</s>
<s>
Remember	O
that	O
a	B-General_Concept
hole	O
is	O
created	O
by	O
an	O
acceptor	O
atom	B-Language
,	O
e.g.	O
</s>
<s>
The	O
answer	O
is	O
that	O
what	O
really	O
happens	O
is	O
not	O
that	O
a	B-General_Concept
hole	O
is	O
repelled	O
,	O
but	O
electrons	O
are	O
attracted	O
by	O
the	O
positive	O
field	O
,	O
and	O
fill	O
these	O
holes	O
,	O
creating	O
a	B-General_Concept
depletion	B-Algorithm
region	I-Algorithm
where	O
no	O
charge	O
carriers	O
exist	O
because	O
the	O
electron	O
is	O
now	O
fixed	O
onto	O
the	O
atom	B-Language
and	O
immobile	O
.	O
</s>
<s>
As	O
the	O
voltage	O
at	O
the	O
gate	O
increases	O
,	O
there	O
will	O
be	O
a	B-General_Concept
point	O
at	O
which	O
the	O
surface	O
above	O
the	O
depletion	B-Algorithm
region	I-Algorithm
will	O
be	O
converted	O
from	O
p-type	O
into	O
n-type	O
,	O
as	O
electrons	O
from	O
the	O
bulk	O
area	O
will	O
start	O
to	O
get	O
attracted	O
by	O
the	O
larger	O
electric	O
field	O
.	O
</s>
<s>
The	O
threshold	O
voltage	O
at	O
which	O
this	O
conversion	O
happens	O
is	O
one	O
of	O
the	O
most	O
important	O
parameters	O
in	O
a	B-General_Concept
MOSFET	B-Architecture
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	B-General_Concept
p-type	O
bulk	O
,	O
inversion	O
happens	O
when	O
the	O
intrinsic	O
energy	O
level	O
at	O
the	O
surface	O
becomes	O
smaller	O
than	O
the	O
Fermi	O
level	O
at	O
the	O
surface	O
.	O
</s>
<s>
One	O
can	O
see	O
this	O
from	O
a	B-General_Concept
band	O
diagram	O
.	O
</s>
<s>
Therefore	O
,	O
when	O
the	O
gate	O
voltage	O
is	O
increased	O
in	O
a	B-General_Concept
positive	O
sense	O
(	O
for	O
the	O
given	O
example	O
)	O
,	O
this	O
will	O
"	O
bend	O
"	O
the	O
intrinsic	O
energy	O
level	O
band	O
so	O
that	O
it	O
will	O
curve	O
downwards	O
towards	O
the	O
valence	O
band	O
.	O
</s>
<s>
If	O
the	O
Fermi	O
level	O
lies	O
closer	O
to	O
the	O
valence	O
band	O
(	O
for	O
p-type	O
)	O
,	O
there	O
will	O
be	O
a	B-General_Concept
point	O
when	O
the	O
Intrinsic	O
level	O
will	O
start	O
to	O
cross	O
the	O
Fermi	O
level	O
and	O
when	O
the	O
voltage	O
reaches	O
the	O
threshold	O
voltage	O
,	O
the	O
intrinsic	O
level	O
does	O
cross	O
the	O
Fermi	O
level	O
,	O
and	O
that	O
is	O
what	O
is	O
known	O
as	O
inversion	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.5	O
|Channel	O
formation	O
in	O
nMOS	O
MOSFET	B-Architecture
shown	O
as	O
band	O
diagram	O
:	O
Top	O
panels	O
:	O
An	O
applied	O
gate	O
voltage	O
bends	O
bands	O
,	O
depleting	O
holes	O
from	O
surface	O
(	O
left	O
)	O
.	O
</s>
<s>
The	O
charge	O
inducing	O
the	O
bending	O
is	O
balanced	O
by	O
a	B-General_Concept
layer	O
of	O
negative	O
acceptor-ion	O
charge	O
(	O
right	O
)	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.5	O
|C	O
–	O
V	O
profile	O
for	O
a	B-General_Concept
bulk	O
MOSFET	B-Architecture
with	O
different	O
oxide	O
thickness	O
.	O
</s>
<s>
A	B-General_Concept
MOSFET	B-Architecture
is	O
based	O
on	O
the	O
modulation	O
of	O
charge	O
concentration	O
by	O
a	B-General_Concept
MOS	O
capacitance	O
between	O
a	B-General_Concept
body	O
electrode	O
and	O
a	B-General_Concept
gate	O
electrode	O
located	O
above	O
the	O
body	O
and	O
insulated	O
from	O
all	O
other	O
device	O
regions	O
by	O
a	B-General_Concept
gate	O
dielectric	O
layer	O
.	O
</s>
<s>
If	O
dielectrics	O
other	O
than	O
an	O
oxide	O
are	O
employed	O
,	O
the	O
device	O
may	O
be	O
referred	O
to	O
as	O
a	B-General_Concept
metal-insulator-semiconductor	O
FET	O
(	O
MISFET	B-Architecture
)	O
.	O
</s>
<s>
Compared	O
to	O
the	O
MOS	O
capacitor	O
,	O
the	O
MOSFET	B-Architecture
includes	O
two	O
additional	O
terminals	O
(	O
source	O
and	O
drain	O
)	O
,	O
each	O
connected	O
to	O
individual	O
highly	B-Algorithm
doped	I-Algorithm
regions	O
that	O
are	O
separated	O
by	O
the	O
body	O
region	O
.	O
</s>
<s>
The	O
source	O
and	O
drain	O
(	O
unlike	O
the	O
body	O
)	O
are	O
highly	B-Algorithm
doped	I-Algorithm
as	O
signified	O
by	O
a	B-General_Concept
"	O
+	O
"	O
sign	O
after	O
the	O
type	O
of	O
doping	B-Algorithm
.	O
</s>
<s>
If	O
the	O
MOSFET	B-Architecture
is	O
an	O
n-channel	O
or	O
nMOS	B-Architecture
FET	I-Architecture
,	O
then	O
the	O
source	O
and	O
drain	O
are	O
n+	O
regions	O
and	O
the	O
body	O
is	O
a	B-General_Concept
p	O
region	O
.	O
</s>
<s>
If	O
the	O
MOSFET	B-Architecture
is	O
a	B-General_Concept
p-channel	O
or	O
pMOS	B-Architecture
FET	I-Architecture
,	O
then	O
the	O
source	O
and	O
drain	O
are	O
p+	O
regions	O
and	O
the	O
body	O
is	O
a	B-General_Concept
n	O
region	O
.	O
</s>
<s>
The	O
occupancy	O
of	O
the	O
energy	O
bands	O
in	O
a	B-General_Concept
semiconductor	O
is	O
set	O
by	O
the	O
position	O
of	O
the	O
Fermi	O
level	O
relative	O
to	O
the	O
semiconductor	O
energy-band	O
edges	O
.	O
</s>
<s>
This	O
conducting	O
channel	O
extends	O
between	O
the	O
source	O
and	O
the	O
drain	O
,	O
and	O
current	O
is	O
conducted	O
through	O
it	O
when	O
a	B-General_Concept
voltage	O
is	O
applied	O
between	O
the	O
two	O
electrodes	O
.	O
</s>
<s>
Increasing	O
the	O
voltage	O
on	O
the	O
gate	O
leads	O
to	O
a	B-General_Concept
higher	O
electron	O
density	O
in	O
the	O
inversion	O
layer	O
and	O
therefore	O
increases	O
the	O
current	O
flow	O
between	O
the	O
source	O
and	O
drain	O
.	O
</s>
<s>
For	O
gate	O
voltages	O
below	O
the	O
threshold	O
value	O
,	O
the	O
channel	O
is	O
lightly	O
populated	O
,	O
and	O
only	O
a	B-General_Concept
very	O
small	O
subthreshold	O
leakage	O
current	O
can	O
flow	O
between	O
the	O
source	O
and	O
the	O
drain	O
.	O
</s>
<s>
When	O
a	B-General_Concept
negative	O
gate-source	O
voltage	O
(	O
positive	O
source-gate	O
)	O
is	O
applied	O
,	O
it	O
creates	O
a	B-General_Concept
p-channel	O
at	O
the	O
surface	O
of	O
the	O
n	O
region	O
,	O
analogous	O
to	O
the	O
n-channel	O
case	O
,	O
but	O
with	O
opposite	O
polarities	O
of	O
charges	O
and	O
voltages	O
.	O
</s>
<s>
When	O
a	B-General_Concept
voltage	O
less	O
negative	O
than	O
the	O
threshold	O
value	O
(	O
a	B-General_Concept
negative	O
voltage	O
for	O
the	O
p-channel	O
)	O
is	O
applied	O
between	O
gate	O
and	O
source	O
,	O
the	O
channel	O
disappears	O
and	O
only	O
a	B-General_Concept
very	O
small	O
subthreshold	O
current	O
can	O
flow	O
between	O
the	O
source	O
and	O
the	O
drain	O
.	O
</s>
<s>
The	O
device	O
may	O
comprise	O
a	B-General_Concept
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
device	O
in	O
which	O
a	B-General_Concept
buried	B-Algorithm
oxide	I-Algorithm
is	O
formed	O
below	O
a	B-General_Concept
thin	O
semiconductor	O
layer	O
.	O
</s>
<s>
If	O
the	O
channel	O
region	O
between	O
the	O
gate	O
dielectric	O
and	O
the	O
buried	B-Algorithm
oxide	I-Algorithm
region	O
is	O
very	O
thin	O
,	O
the	O
channel	O
is	O
referred	O
to	O
as	O
an	O
ultrathin	O
channel	O
region	O
with	O
the	O
source	O
and	O
drain	O
regions	O
formed	O
on	O
either	O
side	O
in	O
or	O
above	O
the	O
thin	O
semiconductor	O
layer	O
.	O
</s>
<s>
right|thumb|upright	O
=	O
1.2	O
|Example	O
application	O
of	O
an	O
n-channel	O
MOSFET	B-Architecture
.	O
</s>
<s>
The	O
operation	O
of	O
a	B-General_Concept
MOSFET	B-Architecture
can	O
be	O
separated	O
into	O
three	O
different	O
modes	O
,	O
depending	O
on	O
the	O
voltages	O
at	O
the	O
terminals	O
.	O
</s>
<s>
In	O
the	O
following	O
discussion	O
,	O
a	B-General_Concept
simplified	O
algebraic	O
model	O
is	O
used	O
.	O
</s>
<s>
Modern	O
MOSFET	B-Architecture
characteristics	O
are	O
more	O
complex	O
than	O
the	O
algebraic	O
model	O
presented	O
here	O
.	O
</s>
<s>
For	O
an	O
enhancement-mode	B-Algorithm
,	O
n-channel	O
MOSFET	B-Architecture
,	O
the	O
three	O
operational	O
modes	O
are	O
:	O
</s>
<s>
According	O
to	O
the	O
basic	O
threshold	O
model	O
,	O
the	O
transistor	B-Application
is	O
turned	O
off	O
,	O
and	O
there	O
is	O
no	O
conduction	O
between	O
drain	O
and	O
source	O
.	O
</s>
<s>
A	B-General_Concept
more	O
accurate	O
model	O
considers	O
the	O
effect	O
of	O
thermal	O
energy	O
on	O
the	O
Fermi	O
–	O
Dirac	O
distribution	O
of	O
electron	O
energies	O
which	O
allow	O
some	O
of	O
the	O
more	O
energetic	O
electrons	O
at	O
the	O
source	O
to	O
enter	O
the	O
channel	O
and	O
flow	O
to	O
the	O
drain	O
.	O
</s>
<s>
This	O
results	O
in	O
a	B-General_Concept
subthreshold	O
current	O
that	O
is	O
an	O
exponential	O
function	O
of	O
gate-source	O
voltage	O
.	O
</s>
<s>
While	O
the	O
current	O
between	O
drain	O
and	O
source	O
should	O
ideally	O
be	O
zero	O
when	O
the	O
transistor	B-Application
is	O
being	O
used	O
as	O
a	B-General_Concept
turned-off	O
switch	O
,	O
there	O
is	O
a	B-General_Concept
weak-inversion	O
current	O
,	O
sometimes	O
called	O
subthreshold	O
leakage	O
.	O
</s>
<s>
with	O
=	O
capacitance	O
of	O
the	O
depletion	B-Algorithm
layer	I-Algorithm
and	O
=	O
capacitance	O
of	O
the	O
oxide	O
layer	O
.	O
</s>
<s>
In	O
a	B-General_Concept
long-channel	O
device	O
,	O
there	O
is	O
no	O
drain	O
voltage	O
dependence	O
of	O
the	O
current	O
once	O
,	O
but	O
as	O
channel	O
length	O
is	O
reduced	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
introduces	O
drain	O
voltage	O
dependence	O
that	O
depends	O
in	O
a	B-General_Concept
complex	O
way	O
upon	O
the	O
device	O
geometry	O
(	O
for	O
example	O
,	O
the	O
channel	O
doping	B-Algorithm
,	O
the	O
junction	O
doping	B-Algorithm
and	O
so	O
on	O
)	O
.	O
</s>
<s>
Frequently	O
,	O
threshold	O
voltage	O
Vth	O
for	O
this	O
mode	O
is	O
defined	O
as	O
the	O
gate	O
voltage	O
at	O
which	O
a	B-General_Concept
selected	O
value	O
of	O
current	O
ID0	O
occurs	O
,	O
for	O
example	O
,	O
ID0	O
=	O
1μA	O
,	O
which	O
may	O
not	O
be	O
the	O
same	O
Vth-value	O
used	O
in	O
the	O
equations	O
for	O
the	O
following	O
modes	O
.	O
</s>
<s>
By	O
working	O
in	O
the	O
weak-inversion	O
region	O
,	O
the	O
MOSFETs	B-Architecture
in	O
these	O
circuits	O
deliver	O
the	O
highest	O
possible	O
transconductance-to-current	O
ratio	O
,	O
namely	O
:	O
,	O
almost	O
that	O
of	O
a	B-General_Concept
bipolar	O
transistor	B-Application
.	O
</s>
<s>
The	O
subthreshold	O
I	O
–	O
V	O
curve	O
depends	O
exponentially	O
upon	O
threshold	O
voltage	O
,	O
introducing	O
a	B-General_Concept
strong	O
dependence	O
on	O
any	O
manufacturing	O
variation	O
that	O
affects	O
threshold	O
voltage	O
;	O
for	O
example	O
:	O
variations	O
in	O
oxide	O
thickness	O
,	O
junction	O
depth	O
,	O
or	O
body	O
doping	B-Algorithm
that	O
change	O
the	O
degree	O
of	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
.	O
</s>
<s>
The	O
transistor	B-Application
is	O
turned	O
on	O
,	O
and	O
a	B-General_Concept
channel	O
has	O
been	O
created	O
which	O
allows	O
current	O
between	O
the	O
drain	O
and	O
the	O
source	O
.	O
</s>
<s>
The	O
MOSFET	B-Architecture
operates	O
like	O
a	B-General_Concept
resistor	O
,	O
controlled	O
by	O
the	O
gate	O
voltage	O
relative	O
to	O
both	O
the	O
source	O
and	O
drain	O
voltages	O
.	O
</s>
<s>
The	O
switch	O
is	O
turned	O
on	O
,	O
and	O
a	B-General_Concept
channel	O
has	O
been	O
created	O
,	O
which	O
allows	O
current	O
between	O
the	O
drain	O
and	O
source	O
.	O
</s>
<s>
Since	O
the	O
drain	O
voltage	O
is	O
higher	O
than	O
the	O
source	O
voltage	O
,	O
the	O
electrons	O
spread	O
out	O
,	O
and	O
conduction	O
is	O
not	O
through	O
a	B-General_Concept
narrow	O
channel	O
but	O
through	O
a	B-General_Concept
broader	O
,	O
two	O
-	O
or	O
three-dimensional	O
current	O
distribution	O
extending	O
away	O
from	O
the	O
interface	O
and	O
deeper	O
in	O
the	O
substrate	B-Architecture
.	O
</s>
<s>
The	O
onset	O
of	O
this	O
region	O
is	O
also	O
known	O
as	O
pinch-off	B-Algorithm
to	O
indicate	O
the	O
lack	O
of	O
channel	O
region	O
near	O
the	O
drain	O
.	O
</s>
<s>
The	O
additional	O
factor	O
involving	O
λ	O
,	O
the	O
channel-length	O
modulation	O
parameter	O
,	O
models	O
current	O
dependence	O
on	O
drain	O
voltage	O
due	O
to	O
the	O
Early	O
effect	O
,	O
or	O
channel	B-Algorithm
length	I-Algorithm
modulation	I-Algorithm
.	O
</s>
<s>
According	O
to	O
this	O
equation	O
,	O
a	B-General_Concept
key	O
design	O
parameter	O
,	O
the	O
MOSFET	B-Architecture
transconductance	B-Algorithm
is	O
:	O
</s>
<s>
where	O
the	O
combination	O
Vov	O
=	O
VGS−	O
Vth	O
is	O
called	O
the	O
overdrive	O
voltage	O
,	O
and	O
where	O
VDSsat	O
=	O
VGS−	O
Vth	O
accounts	O
for	O
a	B-General_Concept
small	O
discontinuity	O
in	O
which	O
would	O
otherwise	O
appear	O
at	O
the	O
transition	O
between	O
the	O
triode	O
and	O
saturation	O
regions	O
.	O
</s>
<s>
Another	O
key	O
design	O
parameter	O
is	O
the	O
MOSFET	B-Architecture
output	O
resistance	O
rout	O
given	O
by	O
:	O
</s>
<s>
In	O
addition	O
,	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
increases	O
off-state	O
(	O
cutoff	O
)	O
current	O
and	O
requires	O
an	O
increase	O
in	O
threshold	O
voltage	O
to	O
compensate	O
,	O
which	O
in	O
turn	O
reduces	O
the	O
saturation	O
current	O
.	O
</s>
<s>
The	O
occupancy	O
of	O
the	O
energy	O
bands	O
in	O
a	B-General_Concept
semiconductor	O
is	O
set	O
by	O
the	O
position	O
of	O
the	O
Fermi	O
level	O
relative	O
to	O
the	O
semiconductor	O
energy-band	O
edges	O
.	O
</s>
<s>
Application	O
of	O
a	B-General_Concept
source-to-substrate	O
reverse	O
bias	O
of	O
the	O
source-body	O
pn-junction	O
introduces	O
a	B-General_Concept
split	O
between	O
the	O
Fermi	O
levels	O
for	O
electrons	O
and	O
holes	O
,	O
moving	O
the	O
Fermi	O
level	O
for	O
the	O
channel	O
further	O
from	O
the	O
band	O
edge	O
,	O
lowering	O
the	O
occupancy	O
of	O
the	O
channel	O
.	O
</s>
<s>
The	O
body	O
effect	O
upon	O
the	O
channel	O
can	O
be	O
described	O
using	O
a	B-General_Concept
modification	O
of	O
the	O
threshold	O
voltage	O
,	O
approximated	O
by	O
the	O
following	O
equation	O
:	O
</s>
<s>
where	O
VTB	O
is	O
the	O
threshold	O
voltage	O
with	O
substrate	B-Architecture
bias	O
present	O
,	O
and	O
VT0	O
is	O
the	O
zero-VSB	O
value	O
of	O
threshold	O
voltage	O
,	O
is	O
the	O
body	O
effect	O
parameter	O
,	O
and	O
2φB	O
is	O
the	O
approximate	O
potential	O
drop	O
between	O
surface	O
and	O
bulk	O
across	O
the	O
depletion	B-Algorithm
layer	I-Algorithm
when	O
and	O
gate	O
bias	O
is	O
sufficient	O
to	O
ensure	O
that	O
a	B-General_Concept
channel	O
is	O
present	O
.	O
</s>
<s>
As	O
this	O
equation	O
shows	O
,	O
a	B-General_Concept
reverse	O
bias	O
causes	O
an	O
increase	O
in	O
threshold	O
voltage	O
VTB	O
and	O
therefore	O
demands	O
a	B-General_Concept
larger	O
gate	O
voltage	O
before	O
the	O
channel	O
populates	O
.	O
</s>
<s>
The	O
body	O
can	O
be	O
operated	O
as	O
a	B-General_Concept
second	O
gate	O
,	O
and	O
is	O
sometimes	O
referred	O
to	O
as	O
the	O
"	O
back	O
gate	O
"	O
;	O
the	O
body	O
effect	O
is	O
sometimes	O
called	O
the	O
"	O
back-gate	O
effect	O
"	O
.	O
</s>
<s>
A	B-General_Concept
variety	O
of	O
symbols	O
are	O
used	O
for	O
the	O
MOSFET	B-Architecture
.	O
</s>
<s>
The	O
basic	O
design	O
is	O
generally	O
a	B-General_Concept
line	O
for	O
the	O
channel	O
with	O
the	O
source	O
and	O
drain	O
leaving	O
it	O
at	O
right	O
angles	O
and	O
then	O
bending	O
back	O
at	O
right	O
angles	O
into	O
the	O
same	O
direction	O
as	O
the	O
channel	O
.	O
</s>
<s>
Sometimes	O
three	O
line	O
segments	O
are	O
used	O
for	O
enhancement	B-Algorithm
mode	I-Algorithm
and	O
a	B-General_Concept
solid	O
line	O
for	O
depletion	B-Algorithm
mode	I-Algorithm
(	O
see	O
depletion	B-Algorithm
and	I-Algorithm
enhancement	I-Algorithm
modes	I-Algorithm
)	O
.	O
</s>
<s>
Arrows	O
always	O
point	O
from	O
P	O
to	O
N	O
,	O
so	O
an	O
NMOS	O
(	O
N-channel	O
in	O
P-well	O
or	O
P-substrate	O
)	O
has	O
the	O
arrow	O
pointing	O
in	O
(	O
from	O
the	O
bulk	O
to	O
the	O
channel	O
)	O
.	O
</s>
<s>
If	O
the	O
bulk	O
is	O
connected	O
to	O
the	O
source	O
(	O
as	O
is	O
generally	O
the	O
case	O
with	O
discrete	O
devices	O
)	O
it	O
is	O
sometimes	O
angled	O
to	O
meet	O
up	O
with	O
the	O
source	O
leaving	O
the	O
transistor	B-Application
.	O
</s>
<s>
If	O
the	O
bulk	O
is	O
not	O
shown	O
(	O
as	O
is	O
often	O
the	O
case	O
in	O
IC	O
design	O
as	O
they	O
are	O
generally	O
common	O
bulk	O
)	O
an	O
inversion	O
symbol	O
is	O
sometimes	O
used	O
to	O
indicate	O
PMOS	O
,	O
alternatively	O
an	O
arrow	O
on	O
the	O
source	O
may	O
be	O
used	O
in	O
the	O
same	O
way	O
as	O
for	O
bipolar	O
transistors	B-Application
(	O
out	O
for	O
nMOS	O
,	O
in	O
for	O
pMOS	O
)	O
.	O
</s>
<s>
Comparison	O
of	O
enhancement-mode	B-Algorithm
and	O
depletion-mode	B-Algorithm
MOSFET	B-Architecture
symbols	O
,	O
along	O
with	O
JFET	O
symbols	O
.	O
</s>
<s>
For	O
enhancement-mode	B-Algorithm
and	O
depletion-mode	B-Algorithm
MOSFET	B-Architecture
symbols	O
(	O
in	O
columns	O
two	O
and	O
five	O
)	O
,	O
the	O
source	O
terminal	O
is	O
the	O
one	O
connected	O
to	O
the	O
triangle	O
.	O
</s>
<s>
However	O
,	O
these	O
symbols	O
are	O
often	O
drawn	O
with	O
a	B-General_Concept
"	O
T	O
"	O
shaped	O
gate	O
(	O
as	O
elsewhere	O
on	O
this	O
page	O
)	O
,	O
so	O
it	O
is	O
the	O
triangle	O
which	O
must	O
be	O
relied	O
upon	O
to	O
indicate	O
the	O
source	O
terminal	O
.	O
</s>
<s>
This	O
is	O
a	B-General_Concept
typical	O
configuration	O
,	O
but	O
by	O
no	O
means	O
the	O
only	O
important	O
configuration	O
.	O
</s>
<s>
In	O
general	O
,	O
the	O
MOSFET	B-Architecture
is	O
a	B-General_Concept
four-terminal	O
device	O
,	O
and	O
in	O
integrated	O
circuits	O
many	O
of	O
the	O
MOSFETs	B-Architecture
share	O
a	B-General_Concept
body	O
connection	O
,	O
not	O
necessarily	O
connected	O
to	O
the	O
source	O
terminals	O
of	O
all	O
the	O
transistors	B-Application
.	O
</s>
<s>
Digital	O
integrated	O
circuits	O
such	O
as	O
microprocessors	B-Architecture
and	O
memory	O
devices	O
contain	O
thousands	O
to	O
millions	O
to	O
billions	O
of	O
integrated	O
MOSFET	B-Architecture
transistors	B-Application
on	O
each	O
device	O
,	O
providing	O
the	O
basic	O
switching	O
functions	O
required	O
to	O
implement	O
logic	O
gates	O
and	O
data	O
storage	O
.	O
</s>
<s>
Radio-frequency	O
amplifiers	O
up	O
to	O
the	O
UHF	O
spectrum	O
use	O
MOSFET	B-Architecture
transistors	B-Application
as	O
analog	O
signal	O
and	O
power	O
amplifiers	O
.	O
</s>
<s>
Radio	O
systems	O
also	O
use	O
MOSFETs	B-Architecture
as	O
oscillators	O
,	O
or	O
mixers	O
to	O
convert	O
frequencies	O
.	O
</s>
<s>
Following	O
the	O
development	O
of	O
clean	O
rooms	O
to	O
reduce	O
contamination	O
to	O
levels	O
never	O
before	O
thought	O
necessary	O
,	O
and	O
of	O
photolithography	B-Algorithm
and	O
the	O
planar	B-Algorithm
process	I-Algorithm
to	O
allow	O
circuits	O
to	O
be	O
made	O
in	O
very	O
few	O
steps	O
,	O
the	O
Si	O
–	O
SiO2	O
system	O
possessed	O
the	O
technical	O
attractions	O
of	O
low	O
cost	O
of	O
production	O
(	O
on	O
a	B-General_Concept
per	O
circuit	O
basis	O
)	O
and	O
ease	O
of	O
integration	O
.	O
</s>
<s>
Largely	O
because	O
of	O
these	O
two	O
factors	O
,	O
the	O
MOSFET	B-Architecture
has	O
become	O
the	O
most	O
widely	O
used	O
type	O
of	O
transistor	B-Application
in	O
the	O
Institution	O
of	O
Engineering	O
and	O
Technology	O
(	O
IET	O
)	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
method	O
of	O
coupling	O
two	O
complementary	O
MOSFETs	B-Architecture
(	O
P-channel	O
and	O
N-channel	O
)	O
into	O
one	O
high/low	O
switch	O
,	O
known	O
as	O
CMOS	B-Device
,	O
means	O
that	O
digital	O
circuits	O
dissipate	O
very	O
little	O
power	O
except	O
when	O
actually	O
switched	O
.	O
</s>
<s>
The	O
earliest	B-General_Concept
microprocessors	I-General_Concept
starting	O
in	O
1970	O
were	O
all	O
MOS	O
microprocessors	B-Architecture
;	O
i.e.	O
,	O
fabricated	O
entirely	O
from	O
PMOS	B-Algorithm
logic	I-Algorithm
or	O
fabricated	O
entirely	O
from	O
NMOS	B-Algorithm
logic	I-Algorithm
.	O
</s>
<s>
In	O
the	O
1970s	O
,	O
MOS	O
microprocessors	B-Architecture
were	O
often	O
contrasted	O
with	O
CMOS	B-Device
microprocessors	B-Architecture
and	O
bipolar	O
bit-slice	O
processors	O
.	O
</s>
<s>
The	O
MOSFET	B-Architecture
is	O
used	O
in	O
digital	O
complementary	O
metal	B-Architecture
–	I-Architecture
oxide	I-Architecture
–	I-Architecture
semiconductor	I-Architecture
(	O
CMOS	B-Device
)	O
logic	O
,	O
which	O
uses	O
p	O
-	O
and	O
n-channel	O
MOSFETs	B-Architecture
as	O
building	O
blocks	O
.	O
</s>
<s>
Overheating	O
is	O
a	B-General_Concept
major	O
concern	O
in	O
integrated	O
circuits	O
since	O
ever	O
more	O
transistors	B-Application
are	O
packed	O
into	O
ever	O
smaller	O
chips	O
.	O
</s>
<s>
CMOS	B-Device
logic	O
reduces	O
power	O
consumption	O
because	O
no	O
current	O
flows	O
(	O
ideally	O
)	O
,	O
and	O
thus	O
no	O
power	O
is	O
consumed	O
,	O
except	O
when	O
the	O
inputs	O
to	O
logic	O
gates	O
are	O
being	O
switched	O
.	O
</s>
<s>
CMOS	B-Device
accomplishes	O
this	O
current	O
reduction	O
by	O
complementing	O
every	O
nMOSFET	O
with	O
a	B-General_Concept
pMOSFET	O
and	O
connecting	O
both	O
gates	O
and	O
both	O
drains	O
together	O
.	O
</s>
<s>
A	B-General_Concept
high	O
voltage	O
on	O
the	O
gates	O
will	O
cause	O
the	O
nMOSFET	O
to	O
conduct	O
and	O
the	O
pMOSFET	O
not	O
to	O
conduct	O
and	O
a	B-General_Concept
low	O
voltage	O
on	O
the	O
gates	O
causes	O
the	O
reverse	O
.	O
</s>
<s>
During	O
the	O
switching	O
time	O
as	O
the	O
voltage	O
goes	O
from	O
one	O
state	O
to	O
another	O
,	O
both	O
MOSFETs	B-Architecture
will	O
conduct	O
briefly	O
.	O
</s>
<s>
The	O
growth	O
of	O
digital	O
technologies	O
like	O
the	O
microprocessor	B-Architecture
has	O
provided	O
the	O
motivation	O
to	O
advance	O
MOSFET	B-Architecture
technology	O
faster	O
than	O
any	O
other	O
type	O
of	O
silicon-based	O
transistor	B-Application
.	O
</s>
<s>
A	B-General_Concept
big	O
advantage	O
of	O
MOSFETs	B-Architecture
for	O
digital	O
switching	O
is	O
that	O
the	O
oxide	O
layer	O
between	O
the	O
gate	O
and	O
the	O
channel	O
prevents	O
DC	O
current	O
from	O
flowing	O
through	O
the	O
gate	O
,	O
further	O
reducing	O
power	O
consumption	O
and	O
giving	O
a	B-General_Concept
very	O
large	O
input	O
impedance	O
.	O
</s>
<s>
The	O
insulating	O
oxide	O
between	O
the	O
gate	O
and	O
channel	O
effectively	O
isolates	O
a	B-General_Concept
MOSFET	B-Architecture
in	O
one	O
logic	O
stage	O
from	O
earlier	O
and	O
later	O
stages	O
,	O
which	O
allows	O
a	B-General_Concept
single	O
MOSFET	B-Architecture
output	O
to	O
drive	O
a	B-General_Concept
considerable	O
number	O
of	O
MOSFET	B-Architecture
inputs	O
.	O
</s>
<s>
Bipolar	O
transistor-based	O
logic	O
(	O
such	O
as	O
TTL	B-General_Concept
)	O
does	O
not	O
have	O
such	O
a	B-General_Concept
high	O
fanout	O
capacity	O
.	O
</s>
<s>
That	O
extent	O
is	O
defined	O
by	O
the	O
operating	O
frequency	O
:	O
as	O
frequencies	O
increase	O
,	O
the	O
input	O
impedance	O
of	O
the	O
MOSFETs	B-Architecture
decreases	O
.	O
</s>
<s>
The	O
MOSFET	B-Architecture
's	O
advantages	O
in	O
digital	O
circuits	O
do	O
not	O
translate	O
into	O
supremacy	O
in	O
all	O
analog	O
circuits	O
.	O
</s>
<s>
The	O
two	O
types	O
of	O
circuit	O
draw	O
upon	O
different	O
features	O
of	O
transistor	B-Application
behavior	O
.	O
</s>
<s>
The	O
JFET	O
and	O
bipolar	O
junction	O
transistor	B-Application
(	O
BJT	O
)	O
are	O
preferred	O
for	O
accurate	O
matching	O
(	O
of	O
adjacent	O
devices	O
in	O
integrated	O
circuits	O
)	O
,	O
higher	O
transconductance	B-Algorithm
and	O
certain	O
temperature	O
characteristics	O
which	O
simplify	O
keeping	O
performance	O
predictable	O
as	O
circuit	O
temperature	O
varies	O
.	O
</s>
<s>
Nevertheless	O
,	O
MOSFETs	B-Architecture
are	O
widely	O
used	O
in	O
many	O
types	O
of	O
analog	O
circuits	O
because	O
of	O
their	O
own	O
advantages	O
(	O
zero	O
gate	O
current	O
,	O
high	O
and	O
adjustable	O
output	O
impedance	O
and	O
improved	O
robustness	O
vs.	O
BJTs	O
which	O
can	O
be	O
permanently	O
degraded	O
by	O
even	O
lightly	O
breaking	O
down	O
the	O
emitter-base	O
)	O
.	O
</s>
<s>
The	O
characteristics	O
and	O
performance	O
of	O
many	O
analog	O
circuits	O
can	O
be	O
scaled	O
up	O
or	O
down	O
by	O
changing	O
the	O
sizes	O
(	O
length	O
and	O
width	O
)	O
of	O
the	O
MOSFETs	B-Architecture
used	O
.	O
</s>
<s>
By	O
comparison	O
,	O
in	O
bipolar	O
transistors	B-Application
follow	O
a	B-General_Concept
different	O
scaling	O
law	O
.	O
</s>
<s>
MOSFETs	B-Architecture
 '	O
ideal	O
characteristics	O
regarding	O
gate	O
current	O
(	O
zero	O
)	O
and	O
drain-source	O
offset	O
voltage	O
(	O
zero	O
)	O
also	O
make	O
them	O
nearly	O
ideal	O
switch	O
elements	O
,	O
and	O
also	O
make	O
switched	B-Algorithm
capacitor	I-Algorithm
analog	O
circuits	O
practical	O
.	O
</s>
<s>
In	O
their	O
linear	O
region	O
,	O
MOSFETs	B-Architecture
can	O
be	O
used	O
as	O
precision	O
resistors	O
,	O
which	O
can	O
have	O
a	B-General_Concept
much	O
higher	O
controlled	O
resistance	O
than	O
BJTs	O
.	O
</s>
<s>
In	O
high	O
power	O
circuits	O
,	O
MOSFETs	B-Architecture
sometimes	O
have	O
the	O
advantage	O
of	O
not	O
suffering	O
from	O
thermal	O
runaway	O
as	O
BJTs	O
do	O
.	O
</s>
<s>
This	O
means	O
that	O
complete	O
analog	O
circuits	O
can	O
be	O
made	O
on	O
a	B-General_Concept
silicon	O
chip	O
in	O
a	B-General_Concept
much	O
smaller	O
space	O
and	O
with	O
simpler	O
fabrication	B-Architecture
techniques	O
.	O
</s>
<s>
MOSFETS	B-Architecture
are	O
ideally	O
suited	O
to	O
switch	O
inductive	O
loads	O
because	O
of	O
tolerance	O
to	O
inductive	O
kickback	O
.	O
</s>
<s>
Some	O
ICs	O
combine	O
analog	O
and	O
digital	O
MOSFET	B-Architecture
circuitry	O
on	O
a	B-General_Concept
single	O
mixed-signal	O
integrated	O
circuit	O
,	O
making	O
the	O
needed	O
board	O
space	O
even	O
smaller	O
.	O
</s>
<s>
This	O
creates	O
a	B-General_Concept
need	O
to	O
isolate	O
the	O
analog	O
circuits	O
from	O
the	O
digital	O
circuits	O
on	O
a	B-General_Concept
chip	O
level	O
,	O
leading	O
to	O
the	O
use	O
of	O
isolation	O
rings	O
and	O
silicon	B-Algorithm
on	I-Algorithm
insulator	I-Algorithm
(	O
SOI	O
)	O
.	O
</s>
<s>
Since	O
MOSFETs	B-Architecture
require	O
more	O
space	O
to	O
handle	O
a	B-General_Concept
given	O
amount	O
of	O
power	O
than	O
a	B-General_Concept
BJT	O
,	O
fabrication	B-Architecture
processes	O
can	O
incorporate	O
BJTs	O
and	O
MOSFETs	B-Architecture
into	O
a	B-General_Concept
single	O
device	O
.	O
</s>
<s>
Mixed-transistor	O
devices	O
are	O
called	O
bi-FETs	O
(	O
bipolar	O
FETs	O
)	O
if	O
they	O
contain	O
just	O
one	O
BJT-FET	O
and	O
BiCMOS	B-General_Concept
(	O
bipolar-CMOS	O
)	O
if	O
they	O
contain	O
complementary	O
BJT-FETs	O
.	O
</s>
<s>
MOSFET	B-Architecture
analog	O
switches	O
use	O
the	O
MOSFET	B-Architecture
to	O
pass	O
analog	O
signals	O
when	O
on	O
,	O
and	O
as	O
a	B-General_Concept
high	O
impedance	O
when	O
off	O
.	O
</s>
<s>
Signals	O
flow	O
in	O
both	O
directions	O
across	O
a	B-General_Concept
MOSFET	B-Architecture
switch	O
.	O
</s>
<s>
In	O
this	O
application	O
,	O
the	O
drain	O
and	O
source	O
of	O
a	B-General_Concept
MOSFET	B-Architecture
exchange	O
places	O
depending	O
on	O
the	O
relative	O
voltages	O
of	O
the	O
source/drain	O
electrodes	O
.	O
</s>
<s>
The	O
source	O
is	O
the	O
more	O
negative	O
side	O
for	O
an	O
N-MOS	B-Algorithm
or	O
the	O
more	O
positive	O
side	O
for	O
a	B-General_Concept
P-MOS	B-Algorithm
.	O
</s>
<s>
This	O
analog	O
switch	O
uses	O
a	B-General_Concept
four-terminal	O
simple	O
MOSFET	B-Architecture
of	O
either	O
P	O
or	O
N	O
type	O
.	O
</s>
<s>
Whenever	O
the	O
gate	O
voltage	O
exceeds	O
the	O
source	O
voltage	O
by	O
at	O
least	O
a	B-General_Concept
threshold	O
voltage	O
,	O
the	O
MOSFET	B-Architecture
conducts	O
.	O
</s>
<s>
The	O
higher	O
the	O
voltage	O
,	O
the	O
more	O
the	O
MOSFET	B-Architecture
can	O
conduct	O
.	O
</s>
<s>
An	O
N-MOS	B-Algorithm
switch	O
passes	O
all	O
voltages	O
less	O
than	O
V	O
−	O
V	O
.	O
When	O
the	O
switch	O
is	O
conducting	O
,	O
it	O
typically	O
operates	O
in	O
the	O
linear	O
(	O
or	O
ohmic	O
)	O
mode	O
of	O
operation	O
,	O
since	O
the	O
source	O
and	O
drain	O
voltages	O
will	O
typically	O
be	O
nearly	O
equal	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
a	B-General_Concept
P-MOS	B-Algorithm
,	O
the	O
body	O
is	O
connected	O
to	O
the	O
most	O
positive	O
voltage	O
,	O
and	O
the	O
gate	O
is	O
brought	O
to	O
a	B-General_Concept
lower	O
potential	O
to	O
turn	O
the	O
switch	O
on	O
.	O
</s>
<s>
The	O
P-MOS	B-Algorithm
switch	O
passes	O
all	O
voltages	O
higher	O
than	O
V	O
−	O
V	O
(	O
threshold	O
voltage	O
V	O
is	O
negative	O
in	O
the	O
case	O
of	O
enhancement-mode	B-Algorithm
P-MOS	B-Algorithm
)	O
.	O
</s>
<s>
This	O
"	O
complementary	O
"	O
or	O
CMOS	B-Device
type	O
of	O
switch	O
uses	O
one	O
P-MOS	B-Algorithm
and	O
one	O
N-MOS	B-Algorithm
FET	O
to	O
counteract	O
the	O
limitations	O
of	O
the	O
single-type	O
switch	O
.	O
</s>
<s>
The	O
FETs	O
have	O
their	O
drains	O
and	O
sources	O
connected	O
in	O
parallel	O
,	O
the	O
body	O
of	O
the	O
P-MOS	B-Algorithm
is	O
connected	O
to	O
the	O
high	O
potential	O
(	O
VDD	O
)	O
and	O
the	O
body	O
of	O
the	O
N-MOS	B-Algorithm
is	O
connected	O
to	O
the	O
low	O
potential	O
(	O
gnd	O
)	O
.	O
</s>
<s>
To	O
turn	O
the	O
switch	O
on	O
,	O
the	O
gate	O
of	O
the	O
P-MOS	B-Algorithm
is	O
driven	O
to	O
the	O
low	O
potential	O
and	O
the	O
gate	O
of	O
the	O
N-MOS	B-Algorithm
is	O
driven	O
to	O
the	O
high	O
potential	O
.	O
</s>
<s>
For	O
voltages	O
between	O
VDD	O
−	O
Vtn	O
and	O
gnd	O
−	O
Vtp	O
,	O
both	O
FETs	O
conduct	O
the	O
signal	O
;	O
for	O
voltages	O
less	O
than	O
gnd	O
−	O
Vtp	O
,	O
the	O
N-MOS	B-Algorithm
conducts	O
alone	O
;	O
and	O
for	O
voltages	O
greater	O
than	O
VDD	O
−	O
Vtn	O
,	O
the	O
P-MOS	B-Algorithm
conducts	O
alone	O
.	O
</s>
<s>
Also	O
,	O
the	O
P-MOS	B-Algorithm
is	O
typically	O
two	O
to	O
three	O
times	O
wider	O
than	O
the	O
N-MOS	B-Algorithm
,	O
so	O
the	O
switch	O
will	O
be	O
balanced	O
for	O
speed	O
in	O
the	O
two	O
directions	O
.	O
</s>
<s>
Tri-state	B-Device
circuitry	I-Device
sometimes	O
incorporates	O
a	B-General_Concept
CMOS	B-Device
MOSFET	B-Architecture
switch	O
on	O
its	O
output	O
to	O
provide	O
for	O
a	B-General_Concept
low-ohmic	O
,	O
full-range	O
output	O
when	O
on	O
,	O
and	O
a	B-General_Concept
high-ohmic	O
,	O
mid-level	O
signal	O
when	O
off	O
.	O
</s>
<s>
The	O
primary	O
criterion	O
for	O
the	O
gate	O
material	O
is	O
that	O
it	O
is	O
a	B-General_Concept
good	O
conductor	O
.	O
</s>
<s>
Highly	B-Algorithm
doped	I-Algorithm
polycrystalline	O
silicon	O
is	O
an	O
acceptable	O
but	O
certainly	O
not	O
ideal	O
conductor	O
,	O
and	O
also	O
suffers	O
from	O
some	O
more	O
technical	O
deficiencies	O
in	O
its	O
role	O
as	O
the	O
standard	O
gate	O
material	O
.	O
</s>
<s>
Because	O
polysilicon	O
is	O
a	B-General_Concept
semiconductor	O
,	O
its	O
work	O
function	O
can	O
be	O
modulated	O
by	O
adjusting	O
the	O
type	O
and	O
level	O
of	O
doping	B-Algorithm
.	O
</s>
<s>
By	O
contrast	O
,	O
the	O
work	O
functions	O
of	O
metals	O
are	O
not	O
easily	O
modulated	O
,	O
so	O
tuning	O
the	O
work	O
function	O
to	O
obtain	O
low	O
threshold	O
voltages	O
(	O
LVT	O
)	O
becomes	O
a	B-General_Concept
significant	O
challenge	O
.	O
</s>
<s>
In	O
the	O
MOSFET	B-Architecture
IC	B-Architecture
fabrication	I-Architecture
process	O
,	O
it	O
is	O
preferable	O
to	O
deposit	O
the	O
gate	O
material	O
prior	O
to	O
certain	O
high-temperature	O
steps	O
in	O
order	O
to	O
make	O
better-performing	O
transistors	B-Application
.	O
</s>
<s>
Such	O
high	O
temperature	O
steps	O
would	O
melt	O
some	O
metals	O
,	O
limiting	O
the	O
types	O
of	O
metal	O
that	O
can	O
be	O
used	O
in	O
a	B-General_Concept
metal-gate-based	O
process	O
.	O
</s>
<s>
Polysilicon	O
is	O
not	O
a	B-General_Concept
great	O
conductor	O
(	O
approximately	O
1000	O
times	O
more	O
resistive	O
than	O
metals	O
)	O
which	O
reduces	O
the	O
signal	O
propagation	O
speed	O
through	O
the	O
material	O
.	O
</s>
<s>
The	O
resistivity	O
can	O
be	O
lowered	O
by	O
increasing	O
the	O
level	O
of	O
doping	B-Algorithm
,	O
but	O
even	O
highly	B-Algorithm
doped	I-Algorithm
polysilicon	O
is	O
not	O
as	O
conductive	O
as	O
most	O
metals	O
.	O
</s>
<s>
To	O
improve	O
conductivity	O
further	O
,	O
sometimes	O
a	B-General_Concept
high-temperature	O
metal	O
such	O
as	O
tungsten	B-Application
,	O
titanium	O
,	O
cobalt	B-Algorithm
,	O
and	O
more	O
recently	O
nickel	O
is	O
alloyed	O
with	O
the	O
top	O
layers	O
of	O
the	O
polysilicon	O
.	O
</s>
<s>
Such	O
a	B-General_Concept
blended	O
material	O
is	O
called	O
silicide	O
.	O
</s>
<s>
The	O
process	O
in	O
which	O
silicide	O
is	O
formed	O
on	O
both	O
the	O
gate	O
electrode	O
and	O
the	O
source	O
and	O
drain	O
regions	O
is	O
sometimes	O
called	O
salicide	B-Algorithm
,	O
self-aligned	O
silicide	O
.	O
</s>
<s>
When	O
the	O
transistors	B-Application
are	O
extremely	O
scaled	O
down	O
,	O
it	O
is	O
necessary	O
to	O
make	O
the	O
gate	O
dielectric	O
layer	O
very	O
thin	O
,	O
around	O
1nm	O
in	O
state-of-the-art	O
technologies	O
.	O
</s>
<s>
A	B-General_Concept
phenomenon	O
observed	O
here	O
is	O
the	O
so-called	O
poly	O
depletion	O
,	O
where	O
a	B-General_Concept
depletion	B-Algorithm
layer	I-Algorithm
is	O
formed	O
in	O
the	O
gate	O
polysilicon	O
layer	O
next	O
to	O
the	O
gate	O
dielectric	O
when	O
the	O
transistor	B-Application
is	O
in	O
the	O
inversion	O
.	O
</s>
<s>
To	O
avoid	O
this	O
problem	O
,	O
a	B-General_Concept
metal	O
gate	O
is	O
desired	O
.	O
</s>
<s>
A	B-General_Concept
variety	O
of	O
metal	O
gates	O
such	O
as	O
tantalum	O
,	O
tungsten	B-Application
,	O
tantalum	O
nitride	O
,	O
and	O
titanium	O
nitride	O
are	O
used	O
,	O
usually	O
in	O
conjunction	O
with	O
high-κ	B-Algorithm
dielectrics	I-Algorithm
.	O
</s>
<s>
An	O
alternative	O
is	O
to	O
use	O
fully	O
silicided	O
polysilicon	O
gates	O
,	O
a	B-General_Concept
process	O
known	O
as	O
FUSI	O
.	O
</s>
<s>
Present	O
high	O
performance	O
CPUs	O
use	O
metal	O
gate	O
technology	O
,	O
together	O
with	O
high-κ	B-Algorithm
dielectrics	I-Algorithm
,	O
a	B-General_Concept
combination	O
known	O
as	O
high-κ	B-Algorithm
,	O
metal	O
gate	O
(	O
HKMG	B-Algorithm
)	O
.	O
</s>
<s>
The	O
disadvantages	O
of	O
metal	O
gates	O
are	O
overcome	O
by	O
a	B-General_Concept
few	O
techniques	O
:	O
</s>
<s>
The	O
threshold	O
voltage	O
is	O
tuned	O
by	O
including	O
a	B-General_Concept
thin	O
"	O
work	O
function	O
metal	O
"	O
layer	O
between	O
the	O
high-κ	B-Algorithm
dielectric	I-Algorithm
and	O
the	O
main	O
metal	O
.	O
</s>
<s>
High-κ	B-Algorithm
dielectrics	I-Algorithm
are	O
now	O
well	O
studied	O
,	O
and	O
their	O
defects	O
are	O
understood	O
.	O
</s>
<s>
HKMG	B-Algorithm
processes	O
exist	O
that	O
do	O
not	O
require	O
the	O
metals	O
to	O
experience	O
high	O
temperature	O
anneals	O
;	O
other	O
processes	O
select	O
metals	O
that	O
can	O
survive	O
the	O
annealing	O
step	O
.	O
</s>
<s>
As	O
devices	O
are	O
made	O
smaller	O
,	O
insulating	O
layers	O
are	O
made	O
thinner	O
,	O
often	O
through	O
steps	O
of	O
thermal	B-Algorithm
oxidation	I-Algorithm
or	O
localised	O
oxidation	O
of	O
silicon	O
(	O
LOCOS	B-Application
)	O
.	O
</s>
<s>
To	O
reduce	O
the	O
resulting	O
leakage	O
current	O
,	O
the	O
insulator	O
can	O
be	O
made	O
thinner	O
by	O
choosing	O
a	B-General_Concept
material	O
with	O
a	B-General_Concept
higher	O
dielectric	O
constant	O
.	O
</s>
<s>
From	O
this	O
law	O
it	O
appears	O
the	O
same	O
charge	O
can	O
be	O
maintained	O
in	O
the	O
channel	O
at	O
a	B-General_Concept
lower	O
field	O
provided	O
κ	O
is	O
increased	O
.	O
</s>
<s>
This	O
equation	O
shows	O
the	O
gate	O
voltage	O
will	O
not	O
increase	O
when	O
the	O
insulator	O
thickness	O
increases	O
,	O
provided	O
κ	O
increases	O
to	O
keep	O
tins	O
/	O
κ	O
=	O
constant	O
(	O
see	O
the	O
article	O
on	O
high-κ	B-Algorithm
dielectrics	I-Algorithm
for	O
more	O
detail	O
,	O
and	O
the	O
section	O
in	O
this	O
article	O
on	O
gate-oxide	O
leakage	O
)	O
.	O
</s>
<s>
The	O
insulator	O
in	O
a	B-General_Concept
MOSFET	B-Architecture
is	O
a	B-General_Concept
dielectric	O
which	O
can	O
in	O
any	O
event	O
be	O
silicon	O
oxide	O
,	O
formed	O
by	O
LOCOS	B-Application
but	O
many	O
other	O
dielectric	O
materials	O
are	O
employed	O
.	O
</s>
<s>
The	O
generic	O
term	O
for	O
the	O
dielectric	O
is	O
gate	O
dielectric	O
since	O
the	O
dielectric	O
lies	O
directly	O
below	O
the	O
gate	O
electrode	O
and	O
above	O
the	O
channel	O
of	O
the	O
MOSFET	B-Architecture
.	O
</s>
<s>
thumb|upright	O
=	O
1.2	O
|MOSFET	O
showing	O
shallow	O
junction	O
extensions	O
,	O
raised	O
source	O
and	O
drain	O
and	O
halo	O
implant	O
.	O
</s>
<s>
The	O
drain	B-Algorithm
induced	I-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
of	O
the	O
threshold	O
voltage	O
and	O
channel	B-Algorithm
length	I-Algorithm
modulation	I-Algorithm
effects	O
upon	O
I-V	O
curves	O
are	O
reduced	O
by	O
using	O
shallow	O
junction	O
extensions	O
.	O
</s>
<s>
In	O
addition	O
,	O
halo	O
doping	B-Algorithm
can	O
be	O
used	O
,	O
that	O
is	O
,	O
the	O
addition	O
of	O
very	O
thin	O
heavily	O
doped	O
regions	O
of	O
the	O
same	O
doping	B-Algorithm
type	O
as	O
the	O
body	O
tight	O
against	O
the	O
junction	O
walls	O
to	O
limit	O
the	O
extent	O
of	O
depletion	B-Algorithm
regions	I-Algorithm
.	O
</s>
<s>
These	O
various	O
features	O
of	O
junction	O
design	O
are	O
shown	O
(	O
with	O
artistic	B-License
license	I-License
)	O
in	O
the	O
figure	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.2	O
|MOSFET	O
version	O
of	O
gain-boosted	O
current	O
mirror	O
;	O
M1	O
and	O
M2	O
are	O
in	O
active	O
mode	O
,	O
while	O
M3	O
and	O
M4	O
are	O
in	O
Ohmic	O
mode	O
,	O
and	O
act	O
like	O
resistors	O
.	O
</s>
<s>
The	O
operational	O
amplifier	O
provides	O
feedback	O
that	O
maintains	O
a	B-General_Concept
high	O
output	O
resistance	O
.	O
</s>
<s>
Over	O
the	O
past	O
decades	O
,	O
the	O
MOSFET	B-Architecture
(	O
as	O
used	O
for	O
digital	O
logic	O
)	O
has	O
continually	O
been	O
scaled	O
down	O
in	O
size	O
;	O
typical	O
MOSFET	B-Architecture
channel	O
lengths	O
were	O
once	O
several	O
micrometres	O
,	O
but	O
modern	O
integrated	O
circuits	O
are	O
incorporating	O
MOSFETs	B-Architecture
with	O
channel	O
lengths	O
of	O
tens	O
of	O
nanometers	O
.	O
</s>
<s>
Intel	O
began	O
production	O
of	O
a	B-General_Concept
process	O
featuring	O
a	B-General_Concept
32nm	O
feature	O
size	O
(	O
with	O
the	O
channel	O
being	O
even	O
shorter	O
)	O
in	O
late	O
2009	O
.	O
</s>
<s>
The	O
semiconductor	O
industry	O
maintains	O
a	B-General_Concept
"	O
roadmap	O
"	O
,	O
the	O
ITRS	O
,	O
which	O
sets	O
the	O
pace	O
for	O
MOSFET	B-Architecture
development	O
.	O
</s>
<s>
Historically	O
,	O
the	O
difficulties	O
with	O
decreasing	O
the	O
size	O
of	O
the	O
MOSFET	B-Architecture
have	O
been	O
associated	O
with	O
the	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
process	O
,	O
the	O
need	O
to	O
use	O
very	O
low	O
voltages	O
,	O
and	O
with	O
poorer	O
electrical	O
performance	O
necessitating	O
circuit	O
redesign	O
and	O
innovation	O
(	O
small	O
MOSFETs	B-Architecture
exhibit	O
higher	O
leakage	O
currents	O
and	O
lower	O
output	O
resistance	O
)	O
.	O
</s>
<s>
Smaller	O
MOSFETs	B-Architecture
are	O
desirable	O
for	O
several	O
reasons	O
.	O
</s>
<s>
The	O
main	O
reason	O
to	O
make	O
transistors	B-Application
smaller	O
is	O
to	O
pack	O
more	O
and	O
more	O
devices	O
in	O
a	B-General_Concept
given	O
chip	O
area	O
.	O
</s>
<s>
This	O
results	O
in	O
a	B-General_Concept
chip	O
with	O
the	O
same	O
functionality	O
in	O
a	B-General_Concept
smaller	O
area	O
,	O
or	O
chips	O
with	O
more	O
functionality	O
in	O
the	O
same	O
area	O
.	O
</s>
<s>
Since	O
fabrication	B-Architecture
costs	O
for	O
a	B-General_Concept
semiconductor	B-Architecture
wafer	I-Architecture
are	O
relatively	O
fixed	O
,	O
the	O
cost	O
per	O
integrated	O
circuits	O
is	O
mainly	O
related	O
to	O
the	O
number	O
of	O
chips	O
that	O
can	O
be	O
produced	O
per	O
wafer	B-Architecture
.	O
</s>
<s>
Hence	O
,	O
smaller	O
ICs	O
allow	O
more	O
chips	O
per	O
wafer	B-Architecture
,	O
reducing	O
the	O
price	O
per	O
chip	O
.	O
</s>
<s>
In	O
fact	O
,	O
over	O
the	O
past	O
30	O
years	O
the	O
number	O
of	O
transistors	B-Application
per	O
chip	O
has	O
been	O
doubled	O
every	O
2	O
–	O
3	O
years	O
once	O
a	B-General_Concept
new	O
technology	O
node	O
is	O
introduced	O
.	O
</s>
<s>
For	O
example	O
,	O
the	O
number	O
of	O
MOSFETs	B-Architecture
in	O
a	B-General_Concept
microprocessor	B-Architecture
fabricated	O
in	O
a	B-General_Concept
45	B-Algorithm
nm	I-Algorithm
technology	O
can	O
well	O
be	O
twice	O
as	O
many	O
as	O
in	O
a	B-General_Concept
65	B-Algorithm
nm	I-Algorithm
chip	O
.	O
</s>
<s>
This	O
doubling	O
of	O
transistor	B-Application
density	O
was	O
first	O
observed	O
by	O
Gordon	O
Moore	O
in	O
1965	O
and	O
is	O
commonly	O
referred	O
to	O
as	O
Moore	O
's	O
law	O
.	O
</s>
<s>
It	O
is	O
also	O
expected	O
that	O
smaller	O
transistors	B-Application
switch	O
faster	O
.	O
</s>
<s>
For	O
example	O
,	O
one	O
approach	O
to	O
size	O
reduction	O
is	O
a	B-General_Concept
scaling	O
of	O
the	O
MOSFET	B-Architecture
that	O
requires	O
all	O
device	O
dimensions	O
to	O
reduce	O
proportionally	O
.	O
</s>
<s>
When	O
they	O
are	O
scaled	O
down	O
by	O
equal	O
factors	O
,	O
the	O
transistor	B-Application
channel	O
resistance	O
does	O
not	O
change	O
,	O
while	O
gate	O
capacitance	O
is	O
cut	O
by	O
that	O
factor	O
.	O
</s>
<s>
Hence	O
,	O
the	O
RC	O
delay	O
of	O
the	O
transistor	B-Application
scales	O
with	O
a	B-General_Concept
similar	O
factor	O
.	O
</s>
<s>
While	O
this	O
has	O
been	O
traditionally	O
the	O
case	O
for	O
the	O
older	O
technologies	O
,	O
for	O
the	O
state-of-the-art	O
MOSFETs	B-Architecture
reduction	O
of	O
the	O
transistor	B-Application
dimensions	O
does	O
not	O
necessarily	O
translate	O
to	O
higher	O
chip	O
speed	O
because	O
the	O
delay	O
due	O
to	O
interconnections	O
is	O
more	O
significant	O
.	O
</s>
<s>
Producing	O
MOSFETs	B-Architecture
with	O
channel	O
lengths	O
much	O
smaller	O
than	O
a	B-General_Concept
micrometre	O
is	O
a	B-General_Concept
challenge	O
,	O
and	O
the	O
difficulties	O
of	O
semiconductor	B-Architecture
device	I-Architecture
fabrication	I-Architecture
are	O
always	O
a	B-General_Concept
limiting	O
factor	O
in	O
advancing	O
integrated	O
circuit	O
technology	O
.	O
</s>
<s>
Though	O
processes	O
such	O
as	O
ALD	O
have	O
improved	O
fabrication	B-Architecture
for	O
small	O
components	O
,	O
the	O
small	O
size	O
of	O
the	O
MOSFET	B-Architecture
(	O
less	O
than	O
a	B-General_Concept
few	O
tens	O
of	O
nanometers	O
)	O
has	O
created	O
operational	O
problems	O
:	O
</s>
<s>
As	O
MOSFET	B-Architecture
geometries	O
shrink	O
,	O
the	O
voltage	O
that	O
can	O
be	O
applied	O
to	O
the	O
gate	O
must	O
be	O
reduced	O
to	O
maintain	O
reliability	B-Algorithm
.	O
</s>
<s>
To	O
maintain	O
performance	O
,	O
the	O
threshold	O
voltage	O
of	O
the	O
MOSFET	B-Architecture
has	O
to	O
be	O
reduced	O
as	O
well	O
.	O
</s>
<s>
As	O
threshold	O
voltage	O
is	O
reduced	O
,	O
the	O
transistor	B-Application
cannot	O
be	O
switched	O
from	O
complete	O
turn-off	O
to	O
complete	O
turn-on	O
with	O
the	O
limited	O
voltage	O
swing	O
available	O
;	O
the	O
circuit	O
design	O
is	O
a	B-General_Concept
compromise	O
between	O
strong	O
current	O
in	O
the	O
on	O
case	O
and	O
low	O
current	O
in	O
the	O
off	O
case	O
,	O
and	O
the	O
application	O
determines	O
whether	O
to	O
favor	O
one	O
over	O
the	O
other	O
.	O
</s>
<s>
The	O
gate	O
oxide	O
,	O
which	O
serves	O
as	O
insulator	O
between	O
the	O
gate	O
and	O
channel	O
,	O
should	O
be	O
made	O
as	O
thin	O
as	O
possible	O
to	O
increase	O
the	O
channel	O
conductivity	O
and	O
performance	O
when	O
the	O
transistor	B-Application
is	O
on	O
and	O
to	O
reduce	O
subthreshold	O
leakage	O
when	O
the	O
transistor	B-Application
is	O
off	O
.	O
</s>
<s>
However	O
,	O
with	O
current	O
gate	O
oxides	O
with	O
a	B-General_Concept
thickness	O
of	O
around	O
1.2nm	O
(	O
which	O
in	O
silicon	O
is	O
~	O
5atoms	O
thick	O
)	O
the	O
quantum	O
mechanical	O
phenomenon	O
of	O
electron	O
tunneling	O
occurs	O
between	O
the	O
gate	O
and	O
channel	O
,	O
leading	O
to	O
increased	O
power	O
consumption	O
.	O
</s>
<s>
Silicon	O
dioxide	O
however	O
has	O
a	B-General_Concept
modest	O
dielectric	O
constant	O
.	O
</s>
<s>
Increasing	O
the	O
dielectric	O
constant	O
of	O
the	O
gate	O
dielectric	O
allows	O
a	B-General_Concept
thicker	O
layer	O
while	O
maintaining	O
a	B-General_Concept
high	O
capacitance	O
(	O
capacitance	O
is	O
proportional	O
to	O
dielectric	O
constant	O
and	O
inversely	O
proportional	O
to	O
dielectric	O
thickness	O
)	O
.	O
</s>
<s>
All	O
else	O
equal	O
,	O
a	B-General_Concept
higher	O
dielectric	O
thickness	O
reduces	O
the	O
quantum	O
tunneling	O
current	O
through	O
the	O
dielectric	O
between	O
the	O
gate	O
and	O
the	O
channel	O
.	O
</s>
<s>
Insulators	O
that	O
have	O
a	B-General_Concept
larger	O
dielectric	O
constant	O
than	O
silicon	O
dioxide	O
(	O
referred	O
to	O
as	O
high-κ	B-Algorithm
dielectrics	I-Algorithm
)	O
,	O
such	O
as	O
group	O
IVb	O
metal	O
silicates	O
e.g.	O
</s>
<s>
hafnium	O
and	O
zirconium	O
silicates	O
and	O
oxides	O
are	O
being	O
used	O
to	O
reduce	O
the	O
gate	O
leakage	O
from	O
the	O
45	B-Algorithm
nanometer	I-Algorithm
technology	O
node	O
onwards	O
.	O
</s>
<s>
As	O
the	O
insulating	O
dielectric	O
is	O
made	O
thinner	O
,	O
the	O
electric	O
field	O
strength	O
within	O
it	O
goes	O
up	O
for	O
a	B-General_Concept
fixed	O
voltage	O
.	O
</s>
<s>
To	O
make	O
devices	O
smaller	O
,	O
junction	O
design	O
has	O
become	O
more	O
complex	O
,	O
leading	O
to	O
higher	O
doping	B-Algorithm
levels	O
,	O
shallower	O
junctions	O
,	O
"	O
halo	O
"	O
doping	B-Algorithm
and	O
so	O
forth	O
,	O
all	O
to	O
decrease	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
(	O
see	O
the	O
section	O
on	O
junction	O
design	O
)	O
.	O
</s>
<s>
Heavier	O
doping	B-Algorithm
is	O
also	O
associated	O
with	O
thinner	O
depletion	B-Algorithm
layers	I-Algorithm
and	O
more	O
recombination	O
centers	O
that	O
result	O
in	O
increased	O
leakage	O
current	O
,	O
even	O
without	O
lattice	O
damage	O
.	O
</s>
<s>
Drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
(	O
DIBL	B-Algorithm
)	O
and	O
VT	O
roll	O
off	O
:	O
Because	O
of	O
the	O
short-channel	O
effect	O
,	O
channel	O
formation	O
is	O
not	O
entirely	O
done	O
by	O
the	O
gate	O
,	O
but	O
now	O
the	O
drain	O
and	O
source	O
also	O
affect	O
the	O
channel	O
formation	O
.	O
</s>
<s>
As	O
the	O
channel	O
length	O
decreases	O
,	O
the	O
depletion	B-Algorithm
regions	I-Algorithm
of	O
the	O
source	O
and	O
drain	O
come	O
closer	O
together	O
and	O
make	O
the	O
threshold	O
voltage	O
(	O
VT	O
)	O
a	B-General_Concept
function	O
of	O
the	O
length	O
of	O
the	O
channel	O
.	O
</s>
<s>
As	O
we	O
increase	O
the	O
VDS	O
,	O
the	O
depletion	B-Algorithm
regions	I-Algorithm
increase	O
in	O
size	O
,	O
and	O
a	B-General_Concept
considerable	O
amount	O
of	O
charge	O
is	O
depleted	O
by	O
the	O
VDS	O
.	O
</s>
<s>
This	O
effect	O
is	O
called	O
drain	B-Algorithm
induced	I-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
(	O
DIBL	B-Algorithm
)	O
.	O
</s>
<s>
For	O
analog	O
operation	O
,	O
good	O
gain	O
requires	O
a	B-General_Concept
high	O
MOSFET	B-Architecture
output	O
impedance	O
,	O
which	O
is	O
to	O
say	O
,	O
the	O
MOSFET	B-Architecture
current	O
should	O
vary	O
only	O
slightly	O
with	O
the	O
applied	O
drain-to-source	O
voltage	O
.	O
</s>
<s>
As	O
devices	O
are	O
made	O
smaller	O
,	O
the	O
influence	O
of	O
the	O
drain	O
competes	O
more	O
successfully	O
with	O
that	O
of	O
the	O
gate	O
due	O
to	O
the	O
growing	O
proximity	O
of	O
these	O
two	O
electrodes	O
,	O
increasing	O
the	O
sensitivity	O
of	O
the	O
MOSFET	B-Architecture
current	O
to	O
the	O
drain	O
voltage	O
.	O
</s>
<s>
To	O
counteract	O
the	O
resulting	O
decrease	O
in	O
output	O
resistance	O
,	O
circuits	O
are	O
made	O
more	O
complex	O
,	O
either	O
by	O
requiring	O
more	O
devices	O
,	O
for	O
example	O
the	O
cascode	O
and	O
cascade	O
amplifiers	O
,	O
or	O
by	O
feedback	O
circuitry	O
using	O
operational	O
amplifiers	O
,	O
for	O
example	O
a	B-General_Concept
circuit	O
like	O
that	O
in	O
the	O
adjacent	O
figure	O
.	O
</s>
<s>
The	O
transconductance	B-Algorithm
of	O
the	O
MOSFET	B-Architecture
decides	O
its	O
gain	O
and	O
is	O
proportional	O
to	O
hole	O
or	O
electron	O
mobility	O
(	O
depending	O
on	O
device	O
type	O
)	O
,	O
at	O
least	O
for	O
low	O
drain	O
voltages	O
.	O
</s>
<s>
As	O
MOSFET	B-Architecture
size	O
is	O
reduced	O
,	O
the	O
fields	O
in	O
the	O
channel	O
increase	O
and	O
the	O
dopant	O
impurity	O
levels	O
increase	O
.	O
</s>
<s>
Both	O
changes	O
reduce	O
the	O
carrier	O
mobility	O
,	O
and	O
hence	O
the	O
transconductance	B-Algorithm
.	O
</s>
<s>
As	O
channel	O
lengths	O
are	O
reduced	O
without	O
proportional	O
reduction	O
in	O
drain	O
voltage	O
,	O
raising	O
the	O
electric	O
field	O
in	O
the	O
channel	O
,	O
the	O
result	O
is	O
velocity	O
saturation	O
of	O
the	O
carriers	O
,	O
limiting	O
the	O
current	O
and	O
the	O
transconductance	B-Algorithm
.	O
</s>
<s>
However	O
,	O
with	O
transistors	B-Application
becoming	O
smaller	O
and	O
more	O
transistors	B-Application
being	O
placed	O
on	O
the	O
chip	O
,	O
interconnect	O
capacitance	O
(	O
the	O
capacitance	O
of	O
the	O
metal-layer	O
connections	O
between	O
different	O
parts	O
of	O
the	O
chip	O
)	O
is	O
becoming	O
a	B-General_Concept
large	O
percentage	O
of	O
capacitance	O
.	O
</s>
<s>
The	O
ever-increasing	O
density	O
of	O
MOSFETs	B-Architecture
on	O
an	O
integrated	O
circuit	O
creates	O
problems	O
of	O
substantial	O
localized	O
heat	O
generation	O
that	O
can	O
impair	O
circuit	O
operation	O
.	O
</s>
<s>
Circuits	O
operate	O
more	O
slowly	O
at	O
high	O
temperatures	O
,	O
and	O
have	O
reduced	O
reliability	B-Algorithm
and	O
shorter	O
lifetimes	O
.	O
</s>
<s>
Heat	O
sinks	O
and	O
other	O
cooling	O
devices	O
and	O
methods	O
are	O
now	O
required	O
for	O
many	O
integrated	O
circuits	O
including	O
microprocessors	B-Architecture
.	O
</s>
<s>
Power	O
MOSFETs	B-Architecture
are	O
at	O
risk	O
of	O
thermal	O
runaway	O
.	O
</s>
<s>
As	O
their	O
on-state	O
resistance	O
rises	O
with	O
temperature	O
,	O
if	O
the	O
load	O
is	O
approximately	O
a	B-General_Concept
constant-current	O
load	O
then	O
the	O
power	O
loss	O
rises	O
correspondingly	O
,	O
generating	O
further	O
heat	O
.	O
</s>
<s>
With	O
MOSFETs	B-Architecture
becoming	O
smaller	O
,	O
the	O
number	O
of	O
atoms	O
in	O
the	O
silicon	O
that	O
produce	O
many	O
of	O
the	O
transistor	B-Application
's	O
properties	O
is	O
becoming	O
fewer	O
,	O
with	O
the	O
result	O
that	O
control	O
of	O
dopant	O
numbers	O
and	O
placement	O
is	O
more	O
erratic	O
.	O
</s>
<s>
During	O
chip	O
manufacturing	O
,	O
random	O
process	B-Algorithm
variations	I-Algorithm
affect	O
all	O
transistor	B-Application
dimensions	O
:	O
length	O
,	O
width	O
,	O
junction	O
depths	O
,	O
oxide	O
thickness	O
etc.	O
,	O
and	O
become	O
a	B-General_Concept
greater	O
percentage	O
of	O
overall	O
transistor	B-Application
size	O
as	O
the	O
transistor	B-Application
shrinks	O
.	O
</s>
<s>
The	O
transistor	B-Application
characteristics	O
become	O
less	O
certain	O
,	O
more	O
statistical	O
.	O
</s>
<s>
The	O
random	O
nature	O
of	O
manufacture	O
means	O
we	O
do	O
not	O
know	O
which	O
particular	O
example	O
MOSFETs	B-Architecture
actually	O
will	O
end	O
up	O
in	O
a	B-General_Concept
particular	O
instance	O
of	O
the	O
circuit	O
.	O
</s>
<s>
This	O
uncertainty	O
forces	O
a	B-General_Concept
less	O
optimal	O
design	O
because	O
the	O
design	O
must	O
work	O
for	O
a	B-General_Concept
great	O
variety	O
of	O
possible	O
component	O
MOSFETs	B-Architecture
.	O
</s>
<s>
See	O
process	B-Algorithm
variation	I-Algorithm
,	O
design	O
for	O
manufacturability	O
,	O
reliability	B-Algorithm
engineering	O
,	O
and	O
statistical	O
process	O
control	O
.	O
</s>
<s>
The	O
dual-gate	O
MOSFET	B-Architecture
has	O
a	B-General_Concept
tetrode	O
configuration	O
,	O
where	O
both	O
gates	O
control	O
the	O
current	O
in	O
the	O
device	O
.	O
</s>
<s>
It	O
is	O
commonly	O
used	O
for	O
small-signal	O
devices	O
in	O
radio	O
frequency	O
applications	O
where	O
biasing	O
the	O
drain-side	O
gate	O
at	O
constant	O
potential	O
reduces	O
the	O
gain	O
loss	O
caused	O
by	O
Miller	O
effect	O
,	O
replacing	O
two	O
separate	O
transistors	B-Application
in	O
cascode	O
configuration	O
.	O
</s>
<s>
Vacuum-tube	O
tetrodes	O
,	O
using	O
a	B-General_Concept
screen	O
grid	O
,	O
exhibit	O
much	O
lower	O
grid-plate	O
capacitance	O
and	O
much	O
higher	O
output	O
impedance	O
and	O
voltage	O
gains	O
than	O
triode	O
vacuum	O
tubes	O
.	O
</s>
<s>
Tetrode	O
transistors	B-Application
(	O
whether	O
bipolar	O
junction	O
or	O
field-effect	O
)	O
do	O
not	O
exhibit	O
improvements	O
of	O
such	O
a	B-General_Concept
great	O
degree	O
.	O
</s>
<s>
The	O
FinFET	O
is	O
a	B-General_Concept
double-gate	O
silicon-on-insulator	B-Algorithm
device	O
,	O
one	O
of	O
a	B-General_Concept
number	O
of	O
geometries	O
being	O
introduced	O
to	O
mitigate	O
the	O
effects	O
of	O
short	O
channels	O
and	O
reduce	O
drain-induced	B-Algorithm
barrier	I-Algorithm
lowering	I-Algorithm
.	O
</s>
<s>
A	B-General_Concept
thin	O
insulating	O
oxide	O
layer	O
on	O
either	O
side	O
of	O
the	O
fin	O
separates	O
it	O
from	O
the	O
gate	O
.	O
</s>
<s>
SOI	O
FinFETs	O
with	O
a	B-General_Concept
thick	O
oxide	O
on	O
top	O
of	O
the	O
fin	O
are	O
called	O
double-gate	O
and	O
those	O
with	O
a	B-General_Concept
thin	O
oxide	O
on	O
top	O
as	O
well	O
as	O
on	O
the	O
sides	O
are	O
called	O
triple-gate	O
FinFETs	O
.	O
</s>
<s>
There	O
are	O
depletion-mode	B-Algorithm
MOSFET	B-Architecture
devices	O
,	O
which	O
are	O
less	O
commonly	O
used	O
than	O
the	O
standard	O
enhancement-mode	B-Algorithm
devices	O
already	O
described	O
.	O
</s>
<s>
These	O
are	O
MOSFET	B-Architecture
devices	O
that	O
are	O
doped	O
so	O
that	O
a	B-General_Concept
channel	O
exists	O
even	O
with	O
zero	O
voltage	O
from	O
gate	O
to	O
source	O
.	O
</s>
<s>
To	O
control	O
the	O
channel	O
,	O
a	B-General_Concept
negative	O
voltage	O
is	O
applied	O
to	O
the	O
gate	O
(	O
for	O
an	O
n-channel	O
device	O
)	O
,	O
depleting	O
the	O
channel	O
,	O
which	O
reduces	O
the	O
current	O
flow	O
through	O
the	O
device	O
.	O
</s>
<s>
In	O
essence	O
,	O
the	O
depletion-mode	B-Algorithm
device	O
is	O
equivalent	O
to	O
a	B-General_Concept
normally	O
closed	O
(	O
on	O
)	O
switch	O
,	O
while	O
the	O
enhancement-mode	B-Algorithm
device	O
is	O
equivalent	O
to	O
a	B-General_Concept
normally	O
open	O
(	O
off	O
)	O
switch	O
.	O
</s>
<s>
Depletion-mode	B-Algorithm
MOSFET	B-Architecture
families	O
include	O
BF960	O
by	O
Siemens	O
and	O
Telefunken	O
,	O
and	O
the	O
BF980	O
in	O
the	O
1980s	O
by	O
Philips	O
(	O
later	O
to	O
become	O
NXP	O
Semiconductors	O
)	O
,	O
whose	O
derivatives	O
are	O
still	O
used	O
in	O
AGC	O
and	O
RF	O
mixer	O
front-ends	O
.	O
</s>
<s>
Metal-insulator-semiconductor	O
field-effect-transistor	O
,	O
or	O
MISFET	B-Architecture
,	O
is	O
a	B-General_Concept
more	O
general	O
term	O
than	O
MOSFET	B-Architecture
and	O
a	B-General_Concept
synonym	O
to	O
insulated-gate	B-Architecture
field-effect	I-Architecture
transistor	I-Architecture
(	O
IGFET	B-Architecture
)	O
.	O
</s>
<s>
All	O
MOSFETs	B-Architecture
are	O
MISFETs	B-Architecture
,	O
but	O
not	O
all	O
MISFETs	B-Architecture
are	O
MOSFETs	B-Architecture
.	O
</s>
<s>
The	O
gate	O
dielectric	O
insulator	O
in	O
a	B-General_Concept
MISFET	B-Architecture
is	O
silicon	O
dioxide	O
in	O
a	B-General_Concept
MOSFET	B-Architecture
,	O
but	O
other	O
materials	O
can	O
also	O
be	O
employed	O
.	O
</s>
<s>
The	O
gate	O
dielectric	O
lies	O
directly	O
below	O
the	O
gate	O
electrode	O
and	O
above	O
the	O
channel	O
of	O
the	O
MISFET	B-Architecture
.	O
</s>
<s>
The	O
term	O
metal	O
is	O
historically	O
used	O
for	O
the	O
gate	O
material	O
,	O
even	O
though	O
now	O
it	O
is	O
usually	O
highly	B-Algorithm
doped	I-Algorithm
polysilicon	O
or	O
some	O
other	O
non-metal	O
.	O
</s>
<s>
Organic	O
insulators	O
(	O
e.g.	O
,	O
undoped	O
trans-polyacetylene	O
;	O
cyanoethyl	O
pullulan	O
,	O
CEP	O
)	O
,	O
for	O
organic-based	O
FETs	O
.	O
</s>
<s>
For	O
devices	O
of	O
equal	O
current	O
driving	O
capability	O
,	O
n-channel	O
MOSFETs	B-Architecture
can	O
be	O
made	O
smaller	O
than	O
p-channel	O
MOSFETs	B-Architecture
,	O
due	O
to	O
p-channel	O
charge	O
carriers	O
(	O
holes	O
)	O
having	O
lower	O
mobility	O
than	O
do	O
n-channel	O
charge	O
carriers	O
(	O
electrons	O
)	O
,	O
and	O
producing	O
only	O
one	O
type	O
of	O
MOSFET	B-Architecture
on	O
a	B-General_Concept
silicon	O
substrate	B-Architecture
is	O
cheaper	O
and	O
technically	O
simpler	O
.	O
</s>
<s>
These	O
were	O
the	O
driving	O
principles	O
in	O
the	O
design	O
of	O
NMOS	B-Algorithm
logic	I-Algorithm
which	O
uses	O
n-channel	O
MOSFETs	B-Architecture
exclusively	O
.	O
</s>
<s>
However	O
,	O
neglecting	O
leakage	O
current	O
,	O
unlike	O
CMOS	B-Device
logic	O
,	O
NMOS	B-Algorithm
logic	I-Algorithm
consumes	O
power	O
even	O
when	O
no	O
switching	O
is	O
taking	O
place	O
.	O
</s>
<s>
With	O
advances	O
in	O
technology	O
,	O
CMOS	B-Device
logic	O
displaced	O
NMOS	B-Algorithm
logic	I-Algorithm
in	O
the	O
mid-1980s	O
to	O
become	O
the	O
preferred	O
process	O
for	O
digital	O
chips	O
.	O
</s>
<s>
thumb|upright	O
=	O
1.2	O
|Cross	O
section	O
of	O
a	B-General_Concept
power	O
MOSFET	B-Architecture
,	O
with	O
square	O
cells	O
.	O
</s>
<s>
Power	O
MOSFETs	B-Architecture
have	O
a	B-General_Concept
different	O
structure	O
.	O
</s>
<s>
Using	O
a	B-General_Concept
vertical	O
structure	O
,	O
it	O
is	O
possible	O
for	O
the	O
transistor	B-Application
to	O
sustain	O
both	O
high	O
blocking	O
voltage	O
and	O
high	O
current	O
.	O
</s>
<s>
The	O
voltage	O
rating	O
of	O
the	O
transistor	B-Application
is	O
a	B-General_Concept
function	O
of	O
the	O
doping	B-Algorithm
and	O
thickness	O
of	O
the	O
N-epitaxial	O
layer	O
(	O
see	O
cross	O
section	O
)	O
,	O
while	O
the	O
current	O
rating	O
is	O
a	B-General_Concept
function	O
of	O
the	O
channel	O
width	O
(	O
the	O
wider	O
the	O
channel	O
,	O
the	O
higher	O
the	O
current	O
)	O
.	O
</s>
<s>
In	O
a	B-General_Concept
planar	O
structure	O
,	O
the	O
current	O
and	O
breakdown	O
voltage	O
ratings	O
are	O
both	O
a	B-General_Concept
function	O
of	O
the	O
channel	O
dimensions	O
(	O
respectively	O
width	O
and	O
length	O
of	O
the	O
channel	O
)	O
,	O
resulting	O
in	O
inefficient	O
use	O
of	O
the	O
"	O
silicon	O
estate	O
"	O
.	O
</s>
<s>
Power	O
MOSFETs	B-Architecture
with	O
lateral	O
structure	O
are	O
mainly	O
used	O
in	O
high-end	O
audio	O
amplifiers	O
and	O
high-power	O
PA	O
systems	O
.	O
</s>
<s>
Their	O
advantage	O
is	O
a	B-General_Concept
better	O
behaviour	O
in	O
the	O
saturated	O
region	O
(	O
corresponding	O
to	O
the	O
linear	O
region	O
of	O
a	B-General_Concept
bipolar	O
transistor	B-Application
)	O
than	O
the	O
vertical	O
MOSFETs	B-Architecture
.	O
</s>
<s>
Vertical	O
MOSFETs	B-Architecture
are	O
designed	O
for	O
switching	O
applications	O
.	O
</s>
<s>
There	O
are	O
LDMOS	O
(	O
lateral	O
double-diffused	O
metal	B-Architecture
oxide	I-Architecture
semiconductor	I-Architecture
)	O
and	O
VDMOS	O
(	O
vertical	O
double-diffused	O
metal	B-Architecture
oxide	I-Architecture
semiconductor	I-Architecture
)	O
.	O
</s>
<s>
Most	O
power	O
MOSFETs	B-Architecture
are	O
made	O
using	O
this	O
technology	O
.	O
</s>
<s>
One	O
of	O
the	O
design	O
approaches	O
for	O
making	O
a	B-General_Concept
radiation-hardened-by-design	O
(	O
RHBD	O
)	O
device	O
is	O
enclosed-layout-transistor	O
(	O
ELT	O
)	O
.	O
</s>
<s>
Normally	O
,	O
the	O
gate	O
of	O
the	O
MOSFET	B-Architecture
surrounds	O
the	O
drain	O
,	O
which	O
is	O
placed	O
in	O
the	O
center	O
of	O
the	O
ELT	O
.	O
</s>
<s>
The	O
source	O
of	O
the	O
MOSFET	B-Architecture
surrounds	O
the	O
gate	O
.	O
</s>
<s>
Another	O
RHBD	O
MOSFET	B-Architecture
is	O
called	O
H-Gate	O
.	O
</s>
<s>
Both	O
of	O
these	O
transistors	B-Application
have	O
very	O
low	O
leakage	O
currents	O
with	O
respect	O
to	O
radiation	O
.	O
</s>
<s>
However	O
,	O
they	O
are	O
large	O
in	O
size	O
and	O
take	O
up	O
more	O
space	O
on	O
silicon	O
than	O
a	B-General_Concept
standard	O
MOSFET	B-Architecture
.	O
</s>
<s>
In	O
older	O
STI	O
(	O
shallow	O
trench	O
isolation	O
)	O
designs	O
,	O
radiation	O
strikes	O
near	O
the	O
silicon	O
oxide	O
region	O
cause	O
the	O
channel	O
inversion	O
at	O
the	O
corners	O
of	O
the	O
standard	O
MOSFET	B-Architecture
due	O
to	O
accumulation	O
of	O
radiation	O
induced	O
trapped	O
charges	O
.	O
</s>
<s>
If	O
the	O
charges	O
are	O
large	O
enough	O
,	O
the	O
accumulated	O
charges	O
affect	O
STI	O
surface	O
edges	O
along	O
the	O
channel	O
near	O
the	O
channel	O
interface	O
(	O
gate	O
)	O
of	O
the	O
standard	O
MOSFET	B-Architecture
.	O
</s>
<s>
This	O
causes	O
a	B-General_Concept
device	O
channel	O
inversion	O
to	O
occur	O
along	O
the	O
channel	O
edges	O
,	O
creating	O
an	O
off-state	O
leakage	O
path	O
.	O
</s>
<s>
Subsequently	O
,	O
the	O
device	O
turns	O
on	O
;	O
this	O
process	O
severely	O
degrades	O
the	O
reliability	B-Algorithm
of	O
circuits	O
.	O
</s>
<s>
The	O
ELT	O
offers	O
many	O
advantages	O
,	O
including	O
an	O
improvement	O
of	O
reliability	B-Algorithm
by	O
reducing	O
unwanted	O
surface	O
inversion	O
at	O
the	O
gate	O
edges	O
which	O
occurs	O
in	O
the	O
standard	O
MOSFET	B-Architecture
.	O
</s>
<s>
Since	O
the	O
gate	O
edges	O
are	O
enclosed	O
in	O
ELT	O
,	O
there	O
is	O
no	O
gate	O
oxide	O
edge	O
(	O
STI	O
at	O
gate	O
interface	O
)	O
,	O
and	O
thus	O
the	O
transistor	B-Application
off-state	O
leakage	O
is	O
reduced	O
very	O
much	O
.	O
</s>
<s>
They	O
are	O
radiation	O
(	O
high-speed	O
atomic	O
particles	O
like	O
proton	B-Application
and	O
neutron	O
,	O
solar	O
flare	O
magnetic	O
energy	O
dissipation	O
in	O
Earth	O
's	O
space	O
,	O
energetic	O
cosmic	O
rays	O
like	O
X-ray	B-Library
,	O
gamma	O
ray	O
etc	O
.	O
)	O
</s>
<s>
These	O
special	O
electronics	O
are	O
designed	O
by	O
applying	O
different	O
techniques	O
using	O
RHBD	O
MOSFETs	B-Architecture
to	O
ensure	O
safe	O
space	O
journeys	O
and	O
safe	O
space-walks	O
of	O
astronauts	O
.	O
</s>
