<s>
Since	O
1985	O
,	O
many	O
processors	O
implementing	O
some	O
version	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
have	O
been	O
designed	O
and	O
used	O
widely	O
.	O
</s>
<s>
The	O
first	O
MIPS	B-Device
microprocessor	O
,	O
the	O
R2000	B-Device
,	O
was	O
announced	O
in	O
1985	O
.	O
</s>
<s>
New	O
instructions	O
were	O
added	O
to	O
retrieve	O
the	O
results	O
from	O
this	O
unit	O
back	O
to	O
the	O
processor	B-General_Concept
register	I-General_Concept
file	O
;	O
these	O
result-retrieving	O
instructions	O
were	O
interlocked	B-General_Concept
.	O
</s>
<s>
The	O
R2000	B-Device
could	O
be	O
booted	O
either	O
big-endian	O
or	O
little-endian	O
.	O
</s>
<s>
It	O
had	O
thirty-one	O
32-bit	O
general	O
purpose	O
registers	O
,	O
but	O
no	O
status	B-General_Concept
register	I-General_Concept
(	O
condition	B-General_Concept
code	I-General_Concept
register	I-General_Concept
(	O
CCR	O
)	O
,	O
the	O
designers	O
considered	O
it	O
a	O
potential	O
bottleneck	O
)	O
,	O
a	O
feature	O
it	O
shares	O
with	O
the	O
AMD	B-General_Concept
29000	I-General_Concept
,	O
the	O
DEC	B-Device
Alpha	I-Device
,	O
and	O
RISC-V	B-Device
.	O
</s>
<s>
Unlike	O
other	O
registers	O
,	O
the	O
program	B-General_Concept
counter	I-General_Concept
is	O
not	O
directly	O
accessible	O
.	O
</s>
<s>
The	O
R2000	B-Device
also	O
had	O
support	O
for	O
up	O
to	O
four	O
co-processors	O
,	O
one	O
of	O
which	O
was	O
built	O
into	O
the	O
main	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
and	O
handled	O
exceptions	O
,	O
traps	O
and	O
memory	O
management	O
,	O
while	O
the	O
other	O
three	O
were	O
left	O
for	O
other	O
uses	O
.	O
</s>
<s>
One	O
of	O
these	O
could	O
be	O
filled	O
by	O
the	O
optional	O
R2010	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
,	O
which	O
had	O
thirty-two	O
32-bit	O
registers	O
that	O
could	O
be	O
used	O
as	O
sixteen	O
64-bit	B-Device
registers	O
for	O
double-precision	O
.	O
</s>
<s>
The	O
R3000	B-Device
succeeded	O
the	O
R2000	B-Device
in	O
1988	O
,	O
adding	O
32KB	O
(	O
soon	O
raised	O
to	O
64KB	O
)	O
caches	O
for	O
instructions	O
and	O
data	O
,	O
and	O
support	O
for	O
shared-memory	O
multiprocessing	B-Operating_System
in	O
the	O
form	O
of	O
a	O
cache	B-General_Concept
coherence	I-General_Concept
protocol	O
.	O
</s>
<s>
While	O
there	O
were	O
flaws	O
in	O
the	O
R3000s	B-Device
multiprocessing	B-Operating_System
support	O
,	O
it	O
was	O
successfully	O
used	O
in	O
several	O
successful	O
multiprocessor	B-Operating_System
computers	O
.	O
</s>
<s>
The	O
R3000	B-Device
also	O
included	O
a	O
built-in	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
(	O
MMU	O
)	O
,	O
a	O
common	O
feature	O
on	O
CPUs	O
of	O
the	O
era	O
.	O
</s>
<s>
The	O
R3000	B-Device
,	O
like	O
the	O
R2000	B-Device
,	O
could	O
be	O
paired	O
with	O
a	O
R3010	B-Device
FPU	O
.	O
</s>
<s>
The	O
R3000	B-Device
was	O
the	O
first	O
successful	O
MIPS	B-Device
design	O
in	O
the	O
market	O
,	O
and	O
eventually	O
over	O
one	O
million	O
were	O
made	O
.	O
</s>
<s>
A	O
faster	O
version	O
of	O
the	O
R3000	B-Device
running	O
up	O
to	O
40MHz	O
,	O
the	O
R3000A	B-Device
delivered	O
a	O
performance	O
of	O
32	O
million	O
instructions	O
per	O
second	O
(	O
MIPS	B-Device
)	O
,	O
or	O
VAX	O
Unit	O
of	O
Performance	O
(	O
VUPs	O
)	O
.	O
</s>
<s>
The	O
MIPS	B-Device
R3000A-compatible	O
R3051	B-Device
running	O
at	O
33.8688MHz	O
was	O
the	O
processor	O
used	O
in	O
the	O
Sony	B-Device
PlayStation	I-Device
though	O
it	O
did	O
n't	O
have	O
FPU	O
or	O
MMU	O
.	O
</s>
<s>
Third-party	O
designs	O
include	O
Performance	O
Semiconductor	O
's	O
R3400	B-Device
and	O
IDT	O
's	O
R3500	B-Device
,	O
both	O
of	O
them	O
were	O
R3000As	B-Device
with	O
an	O
integrated	O
R3010	B-Device
FPU	O
.	O
</s>
<s>
Toshiba	O
's	O
R3900	B-Device
was	O
a	O
virtually	O
first	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
(	O
SoC	B-Architecture
)	O
for	O
the	O
early	O
handheld	B-Operating_System
PCs	I-Operating_System
that	O
ran	O
Windows	B-Operating_System
CE	I-Operating_System
.	O
</s>
<s>
A	O
radiation-hardened	O
variant	O
for	O
outer	O
space	O
use	O
,	O
the	O
Mongoose-V	B-General_Concept
,	O
is	O
a	O
R3000	B-Device
with	O
an	O
integrated	O
R3010	B-Device
FPU	O
.	O
</s>
<s>
The	O
R4000	B-General_Concept
series	O
,	O
released	O
in	O
1991	O
,	O
extended	O
MIPS	B-Device
to	O
a	O
full	O
64-bit	B-Device
word	O
design	O
,	O
moved	O
the	O
FPU	O
onto	O
the	O
main	O
die	O
to	O
form	O
a	O
single-chip	O
microprocessor	O
,	O
and	O
had	O
a	O
then	O
high	O
clock	O
rate	O
of	O
100MHz	O
at	O
introduction	O
.	O
</s>
<s>
The	O
high	O
clock	O
rates	O
were	O
achieved	O
through	O
the	O
method	O
of	O
deep	B-General_Concept
pipelining	I-General_Concept
(	O
called	O
super-pipelining	O
then	O
)	O
.	O
</s>
<s>
The	O
improved	O
R4400	B-General_Concept
followed	O
in	O
1993	O
.	O
</s>
<s>
It	O
had	O
larger	O
16KB	O
primary	O
caches	O
,	O
largely	O
bug-free	O
64-bit	B-Device
operation	O
,	O
and	O
support	O
for	O
a	O
larger	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
MIPS	B-Device
,	O
now	O
a	O
division	O
of	O
Silicon	O
Graphics	O
(	O
SGI	O
)	O
named	O
MTI	O
,	O
designed	O
the	O
low-cost	O
R4200	B-Device
,	O
the	O
basis	O
for	O
the	O
even	O
cheaper	O
R4300i	O
.	O
</s>
<s>
A	O
derivative	O
of	O
this	O
microprocessor	O
,	O
the	O
NEC	O
VR4300	O
,	O
was	O
used	O
in	O
the	O
Nintendo	B-Operating_System
64	I-Operating_System
game	O
console	O
.	O
</s>
<s>
Quantum	O
Effect	O
Devices	O
(	O
QED	O
)	O
,	O
a	O
separate	O
company	O
started	O
by	O
former	O
MIPS	B-Device
employees	O
,	O
designed	O
the	O
R4600	B-Device
Orion	O
,	O
the	O
R4700	B-Device
Orion	O
,	O
the	O
R4650	B-Device
and	O
the	O
R5000	B-General_Concept
.	O
</s>
<s>
Where	O
the	O
R4000	B-General_Concept
had	O
pushed	O
clock	O
frequency	O
and	O
sacrificed	O
cache	B-General_Concept
capacity	O
,	O
the	O
QED	O
designs	O
emphasized	O
large	O
caches	O
which	O
could	O
be	O
accessed	O
in	O
just	O
two	O
cycles	O
and	O
efficient	O
use	O
of	O
silicon	O
area	O
.	O
</s>
<s>
The	O
R4600	B-Device
and	O
R4700	B-Device
were	O
used	O
in	O
low-cost	O
versions	O
of	O
the	O
SGI	B-Operating_System
Indy	I-Operating_System
workstation	B-Device
as	O
well	O
as	O
the	O
first	O
MIPS-based	O
Cisco	O
routers	O
,	O
such	O
as	O
the	O
36x0	O
and	O
7x00-series	O
routers	O
.	O
</s>
<s>
The	O
R4650	B-Device
was	O
used	O
in	O
the	O
original	O
WebTV	B-Device
set-top	O
boxes	O
(	O
now	O
Microsoft	O
TV	O
)	O
.	O
</s>
<s>
The	O
R5000	B-General_Concept
FPU	O
had	O
more	O
flexible	O
single	O
precision	O
floating-point	O
scheduling	O
than	O
the	O
R4000	B-General_Concept
,	O
and	O
as	O
a	O
result	O
,	O
R5000-based	O
SGI	O
Indys	O
had	O
much	O
better	O
graphics	O
performance	O
than	O
similarly	O
clocked	O
R4400	B-General_Concept
Indys	O
with	O
the	O
same	O
graphics	O
hardware	O
.	O
</s>
<s>
SGI	O
gave	O
the	O
old	O
graphics	O
board	O
a	O
new	O
name	O
when	O
it	O
was	O
combined	O
with	O
R5000	B-General_Concept
,	O
to	O
emphasize	O
the	O
improvement	O
.	O
</s>
<s>
QED	O
later	O
designed	O
the	O
RM7000	O
and	O
RM9000	O
family	O
of	O
devices	O
for	O
embedded	B-Architecture
system	I-Architecture
markets	O
like	O
computer	B-Architecture
networking	I-Architecture
and	O
laser	O
printers	O
.	O
</s>
<s>
QED	O
was	O
acquired	O
by	O
the	O
semiconductor	O
manufacturer	O
PMC-Sierra	O
in	O
August	O
2000	O
,	O
the	O
latter	O
company	O
continuing	O
to	O
invest	O
in	O
the	O
MIPS	B-Device
architecture	I-Device
.	O
</s>
<s>
The	O
RM7000	O
included	O
an	O
integrated	O
256KB	O
L2	O
cache	B-General_Concept
and	O
a	O
controller	O
for	O
optional	O
L3	O
cache	B-General_Concept
.	O
</s>
<s>
The	O
RM9xx0	O
were	O
a	O
family	O
of	O
SOC	B-Architecture
devices	O
which	O
included	O
northbridge	B-Device
peripherals	O
such	O
as	O
memory	B-General_Concept
controller	I-General_Concept
,	O
PCI	B-Protocol
controller	O
,	O
Gigabit	O
Ethernet	O
controller	O
and	O
fast	O
I/O	B-General_Concept
such	O
as	O
a	O
HyperTransport	B-Device
port	O
.	O
</s>
<s>
The	O
R8000	B-General_Concept
(	O
1994	O
)	O
was	O
the	O
first	O
superscalar	B-General_Concept
MIPS	B-Device
design	O
,	O
able	O
to	O
execute	O
two	O
integer	O
or	O
floating	O
point	O
and	O
two	O
memory	O
instructions	O
per	O
cycle	O
.	O
</s>
<s>
The	O
design	O
was	O
spread	O
over	O
six	O
chips	O
:	O
an	O
integer	O
unit	O
(	O
with	O
16KB	O
instruction	O
and	O
16KB	O
data	B-General_Concept
caches	I-General_Concept
)	O
,	O
a	O
floating-point	B-General_Concept
unit	I-General_Concept
,	O
three	O
fully-custom	O
secondary	B-General_Concept
cache	I-General_Concept
tag	O
RAMs	O
(	O
two	O
for	O
secondary	B-General_Concept
cache	I-General_Concept
accesses	O
,	O
one	O
for	O
bus	O
snooping	O
)	O
,	O
and	O
a	O
cache	B-General_Concept
controller	O
ASIC	O
.	O
</s>
<s>
The	O
design	O
had	O
two	O
fully	O
pipelined	B-General_Concept
double	O
precision	O
multiply-add	O
units	O
,	O
which	O
could	O
stream	O
data	O
from	O
the	O
4MB	O
off-chip	O
secondary	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
R8000	B-General_Concept
powered	O
SGI	O
's	O
POWER	B-Application
Challenge	I-Application
servers	O
in	O
the	O
mid-1990s	O
and	O
later	O
became	O
available	O
in	O
the	O
POWER	O
Indigo2	O
workstation	B-Device
.	O
</s>
<s>
The	O
R8000	B-General_Concept
was	O
sold	O
for	O
only	O
a	O
year	O
and	O
remains	O
fairly	O
rare	O
.	O
</s>
<s>
In	O
1995	O
,	O
the	O
R10000	B-General_Concept
was	O
released	O
.	O
</s>
<s>
This	O
processor	O
was	O
a	O
single-chip	O
design	O
,	O
ran	O
at	O
a	O
higher	O
clock	O
frequency	O
than	O
the	O
R8000	B-General_Concept
,	O
and	O
had	O
larger	O
32KB	O
primary	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
.	O
</s>
<s>
It	O
was	O
also	O
superscalar	B-General_Concept
,	O
but	O
its	O
major	O
innovation	O
was	O
out-of-order	B-General_Concept
execution	I-General_Concept
.	O
</s>
<s>
Even	O
with	O
one	O
memory	O
pipeline	O
and	O
simpler	O
FPU	O
,	O
the	O
vastly	O
improved	O
integer	O
performance	O
,	O
lower	O
price	O
,	O
and	O
higher	O
density	O
made	O
the	O
R10000	B-General_Concept
preferable	O
for	O
most	O
customers	O
.	O
</s>
<s>
Some	O
later	O
designs	O
have	O
been	O
based	O
upon	O
R10000	B-General_Concept
core	O
.	O
</s>
<s>
The	O
R12000	B-General_Concept
used	O
a	O
0.25	O
micrometre	O
process	O
to	O
shrink	O
the	O
chip	O
and	O
achieve	O
higher	O
clock	O
rates	O
.	O
</s>
<s>
The	O
revised	O
R14000	B-General_Concept
allowed	O
higher	O
clock	O
rates	O
with	O
added	O
support	O
for	O
double	O
data	O
rate	O
synchronous	O
dynamic	O
random-access	O
memory	O
(	O
DDR	O
SDRAM	O
)	O
static	B-Architecture
random	I-Architecture
access	I-Architecture
memory	I-Architecture
(	O
SRAM	O
)	O
in	O
the	O
off-chip	O
cache	B-General_Concept
.	O
</s>
<s>
Later	O
iterations	O
are	O
named	O
R16000	B-General_Concept
and	O
R16000A	B-General_Concept
,	O
and	O
feature	O
higher	O
clock	O
rates	O
and	O
smaller	O
die	O
manufacturing	O
compared	O
with	O
before	O
.	O
</s>
<s>
Other	O
members	O
of	O
the	O
MIPS	B-Device
family	O
include	O
the	O
R6000	B-Device
,	O
an	O
emitter-coupled	B-General_Concept
logic	I-General_Concept
(	O
ECL	O
)	O
implementation	O
produced	O
by	O
Bipolar	O
Integrated	O
Technology	O
.	O
</s>
<s>
The	O
R6000	B-Device
introduced	O
the	O
MIPS	B-Device
II	O
architecture	O
.	O
</s>
<s>
Its	O
translation	B-Architecture
lookaside	I-Architecture
buffer	I-Architecture
(	O
TLB	O
)	O
and	O
cache	B-General_Concept
architecture	O
are	O
different	O
from	O
all	O
other	O
members	O
of	O
the	O
MIPS	B-Device
family	O
.	O
</s>
<s>
The	O
R6000	B-Device
did	O
not	O
deliver	O
the	O
promised	O
performance	O
benefits	O
,	O
and	O
although	O
it	O
saw	O
some	O
use	O
in	O
Control	O
Data	O
machines	O
,	O
it	O
quickly	O
disappeared	O
from	O
the	O
mainstream	O
market	O
.	O
</s>
<s>
In	O
1981	O
,	O
John	O
L	O
.	O
Hennessy	O
began	O
the	O
Microprocessor	B-General_Concept
without	I-General_Concept
Interlocked	I-General_Concept
Pipeline	I-General_Concept
Stages	I-General_Concept
(	O
MIPS	B-Device
)	O
project	O
at	O
Stanford	O
University	O
to	O
investigate	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
technology	O
.	O
</s>
<s>
The	O
results	O
of	O
his	O
research	O
convinced	O
him	O
of	O
the	O
future	O
commercial	O
potential	O
of	O
the	O
technology	O
,	O
and	O
in	O
1984	O
,	O
he	O
took	O
a	O
sabbatical	O
to	O
found	O
MIPS	B-Device
Computer	O
Systems	O
.	O
</s>
<s>
The	O
company	O
designed	O
a	O
new	O
architecture	O
that	O
was	O
also	O
named	O
MIPS	B-Device
,	O
and	O
introduced	O
the	O
first	O
MIPS	B-Device
implementation	O
,	O
the	O
R2000	B-Device
,	O
in	O
1985	O
.	O
</s>
<s>
The	O
R2000	B-Device
was	O
improved	O
,	O
and	O
the	O
design	O
was	O
introduced	O
as	O
the	O
R3000	B-Device
in	O
1988	O
.	O
</s>
<s>
These	O
32-bit	O
CPUs	O
formed	O
the	O
basis	O
of	O
their	O
company	O
through	O
the	O
1980s	O
,	O
used	O
primarily	O
in	O
Silicon	O
Graphics	O
 '	O
(	O
SGI	O
)	O
series	O
of	O
workstations	B-Device
and	O
later	O
Digital	O
Equipment	O
Corporation	O
DECstation	O
workstations	B-Device
and	O
servers	O
.	O
</s>
<s>
The	O
SGI	O
commercial	O
designs	O
deviated	O
from	O
Stanford	B-General_Concept
MIPS	I-General_Concept
by	O
implementing	O
most	O
of	O
the	O
interlocks	B-General_Concept
in	O
hardware	O
,	O
supplying	O
full	O
multiply	O
and	O
divide	O
instructions	O
(	O
among	O
others	O
)	O
.	O
</s>
<s>
The	O
designs	O
were	O
guided	O
,	O
in	O
part	O
,	O
by	O
software	O
architect	O
Earl	O
Killian	O
who	O
designed	O
the	O
MIPS	B-Device
III	O
64-bit	B-Device
instruction-set	O
extension	O
,	O
and	O
led	O
the	O
work	O
on	O
the	O
R4000	B-General_Concept
microarchitecture	O
.	O
</s>
<s>
In	O
1991	O
MIPS	B-Device
released	O
the	O
first	O
64-bit	B-Device
microprocessor	I-Device
,	O
the	O
R4000	B-General_Concept
.	O
</s>
<s>
However	O
,	O
MIPS	B-Device
had	O
financial	O
difficulties	O
while	O
bringing	O
it	O
to	O
market	O
.	O
</s>
<s>
The	O
design	O
was	O
so	O
important	O
to	O
SGI	O
,	O
at	O
the	O
time	O
one	O
of	O
MIPS	B-Device
 '	O
few	O
major	O
customers	O
,	O
that	O
SGI	O
bought	O
the	O
company	O
in	O
1992	O
to	O
guarantee	O
the	O
design	O
would	O
not	O
be	O
lost	O
.	O
</s>
<s>
The	O
new	O
SGI	O
subsidiary	O
was	O
named	O
MIPS	B-Device
Technologies	O
.	O
</s>
<s>
In	O
the	O
early	O
1990s	O
,	O
MIPS	B-Device
began	O
to	O
license	O
their	O
designs	O
to	O
third-party	O
vendors	O
.	O
</s>
<s>
This	O
proved	O
fairly	O
successful	O
due	O
to	O
the	O
simplicity	O
of	O
the	O
core	O
,	O
which	O
allowed	O
it	O
to	O
have	O
many	O
uses	O
that	O
would	O
have	O
formerly	O
used	O
much	O
less	O
able	O
complex	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
CISC	O
)	O
designs	O
of	O
similar	O
gate	B-Algorithm
count	I-Algorithm
and	O
price	O
;	O
the	O
two	O
are	O
strongly	O
related	O
:	O
the	O
price	O
of	O
a	O
CPU	O
is	O
generally	O
related	O
to	O
the	O
number	O
of	O
gates	O
and	O
the	O
number	O
of	O
external	O
pins	O
.	O
</s>
<s>
Sun	O
Microsystems	O
attempted	O
to	O
enjoy	O
similar	O
success	O
by	O
licensing	O
their	O
SPARC	B-Architecture
core	O
but	O
was	O
not	O
nearly	O
as	O
successful	O
.	O
</s>
<s>
By	O
the	O
late	O
1990s	O
,	O
MIPS	B-Device
was	O
a	O
powerhouse	O
in	O
the	O
embedded	B-Architecture
processor	I-Architecture
field	O
.	O
</s>
<s>
According	O
to	O
MIPS	B-Device
Technologies	O
Inc.	O
,	O
there	O
was	O
an	O
exponential	O
growth	O
,	O
with	O
48-million	O
MIPS-based	O
CPU	O
shipments	O
and	O
49%	O
of	O
total	O
RISC	B-Architecture
CPU	O
market	O
share	O
in	O
1997	O
.	O
</s>
<s>
MIPS	B-Device
was	O
so	O
successful	O
that	O
SGI	O
spun	O
off	O
MIPS	B-Device
Technologies	O
in	O
1998	O
.	O
</s>
<s>
In	O
2000s	O
fully	O
half	O
of	O
MIPS	B-Device
's	O
income	O
came	O
from	O
licensing	O
their	O
designs	O
,	O
while	O
much	O
of	O
the	O
rest	O
came	O
from	O
contract	O
design	O
work	O
on	O
cores	O
for	O
third	O
parties	O
.	O
</s>
<s>
In	O
1999	O
,	O
MIPS	B-Device
Technologies	O
replaced	O
the	O
previous	O
versions	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
with	O
two	O
architectures	O
,	O
the	O
32-bit	O
MIPS32	O
(	O
based	O
on	O
MIPS	B-Device
II	O
with	O
some	O
added	O
features	O
from	O
MIPS	B-Device
III	O
,	O
MIPS	B-Device
IV	O
,	O
and	O
MIPS	B-Device
V	O
)	O
and	O
the	O
64-bit	B-Device
MIPS64	O
(	O
based	O
on	O
MIPS	B-Device
V	O
)	O
for	O
licensing	O
.	O
</s>
<s>
Today	O
,	O
the	O
MIPS	B-Device
cores	O
are	O
one	O
of	O
the	O
most-used	O
"	O
heavyweight	O
"	O
cores	O
in	O
the	O
market	O
for	O
computer-like	O
devices	O
:	O
handheld	B-Operating_System
PCs	I-Operating_System
,	O
set-top	O
boxes	O
,	O
etc	O
.	O
</s>
<s>
Since	O
the	O
MIPS	B-Device
architecture	I-Device
is	O
licensable	O
,	O
it	O
has	O
attracted	O
several	O
processor	O
start-up	O
companies	O
over	O
the	O
years	O
.	O
</s>
<s>
One	O
of	O
the	O
first	O
start-ups	O
to	O
design	O
MIPS	B-General_Concept
processors	I-General_Concept
was	O
Quantum	O
Effect	O
Devices	O
(	O
see	O
next	O
section	O
)	O
.	O
</s>
<s>
The	O
MIPS	B-Device
design	O
team	O
that	O
designed	O
the	O
R4300i	O
started	O
the	O
company	O
SandCraft	O
,	O
which	O
designed	O
the	O
R5432	O
for	O
NEC	O
and	O
later	O
produced	O
the	O
SR71000	O
,	O
one	O
of	O
the	O
first	O
out-of-order	B-General_Concept
execution	I-General_Concept
processors	O
for	O
the	O
embedded	O
market	O
.	O
</s>
<s>
The	O
original	O
DEC	O
StrongARM	B-Device
team	O
eventually	O
split	O
into	O
two	O
MIPS-based	O
start-ups	O
:	O
SiByte	O
which	O
produced	O
the	O
SB-1250	O
,	O
one	O
of	O
the	O
first	O
high-performance	O
MIPS-based	O
systems-on-a-chip	B-Architecture
(	O
SOC	B-Architecture
)	O
;	O
while	O
Alchemy	B-Device
Semiconductor	I-Device
(	O
later	O
acquired	O
by	O
AMD	O
)	O
produced	O
the	O
Au-1000	O
SoC	B-Architecture
for	O
low-power	O
uses	O
.	O
</s>
<s>
Lexra	O
used	O
a	O
MIPS-like	O
architecture	O
and	O
added	O
DSP	O
extensions	O
for	O
the	O
audio	O
chip	O
market	O
and	O
multithreading	B-General_Concept
support	O
for	O
the	O
networking	O
market	O
.	O
</s>
<s>
The	O
first	O
was	O
quickly	O
resolved	O
when	O
Lexra	O
promised	O
not	O
to	O
advertise	O
their	O
processors	O
as	O
MIPS-compatible	O
.	O
</s>
<s>
The	O
second	O
(	O
about	O
MIPS	B-Device
patent	O
4814976	O
for	O
handling	O
unaligned	O
memory	O
access	O
)	O
was	O
protracted	O
,	O
hurt	O
both	O
companies	O
 '	O
business	O
,	O
and	O
culminated	O
in	O
MIPS	B-Device
Technologies	O
giving	O
Lexra	O
a	O
free	O
license	O
and	O
a	O
large	O
cash	O
payment	O
.	O
</s>
<s>
Two	O
companies	O
have	O
emerged	O
that	O
specialize	O
in	O
building	O
multi-core	B-Architecture
processor	I-Architecture
devices	O
using	O
the	O
MIPS	B-Device
architecture	I-Device
.	O
</s>
<s>
Cavium	O
,	O
originally	O
a	O
security	O
processor	O
vendor	O
also	O
produced	O
devices	O
with	O
eight	O
CPU	B-Architecture
cores	I-Architecture
,	O
and	O
later	O
up	O
to	O
32	O
cores	O
,	O
for	O
the	O
same	O
markets	O
.	O
</s>
<s>
Both	O
of	O
these	O
firms	O
designed	O
their	O
cores	O
in-house	O
,	O
only	O
licensing	O
the	O
architecture	O
instead	O
of	O
buying	O
cores	O
from	O
MIPS	B-Device
.	O
</s>
<s>
Among	O
the	O
manufacturers	O
which	O
have	O
made	O
computer	B-Device
workstation	I-Device
systems	O
using	O
MIPS	B-General_Concept
processors	I-General_Concept
are	O
SGI	O
,	O
MIPS	B-Device
Computer	O
Systems	O
,	O
Inc.	O
,	O
Whitechapel	B-Device
Workstations	I-Device
,	O
Olivetti	O
,	O
Siemens-Nixdorf	O
,	O
Acer	O
,	O
Digital	O
Equipment	O
Corporation	O
,	O
NEC	O
,	O
and	O
DeskStation	O
.	O
</s>
<s>
Operating	B-General_Concept
systems	I-General_Concept
ported	O
to	O
the	O
architecture	O
include	O
SGI	O
's	O
IRIX	B-Operating_System
,	O
Microsoft	O
's	O
Windows	B-Device
NT	I-Device
(	O
through	O
v4.0	O
)	O
,	O
Windows	B-Operating_System
CE	I-Operating_System
,	O
Linux	B-Application
,	O
FreeBSD	B-Operating_System
,	O
NetBSD	B-Device
,	O
OpenBSD	B-Operating_System
,	O
UNIX	B-Operating_System
System	I-Operating_System
V	I-Operating_System
,	O
SINIX	B-Operating_System
,	O
QNX	B-Operating_System
,	O
and	O
MIPS	B-Device
Computer	O
Systems	O
 '	O
own	O
RISC/os	B-Operating_System
.	O
</s>
<s>
In	O
the	O
early	O
1990s	O
,	O
speculation	O
occurred	O
that	O
MIPS	B-Device
and	O
other	O
powerful	O
RISC	B-Architecture
processors	I-Architecture
would	O
overtake	O
the	O
Intel	B-Device
IA-32	I-Device
architecture	O
.	O
</s>
<s>
This	O
was	O
encouraged	O
by	O
the	O
support	O
of	O
the	O
first	O
two	O
versions	O
of	O
Microsoft	O
's	O
Windows	B-Device
NT	I-Device
for	O
Alpha	B-Device
,	O
MIPS	B-Device
and	O
PowerPC	B-Architecture
,	O
and	O
to	O
a	O
lesser	O
extent	O
the	O
Clipper	B-General_Concept
architecture	I-General_Concept
and	O
SPARC	B-Architecture
.	O
</s>
<s>
However	O
,	O
as	O
Intel	O
quickly	O
released	O
faster	O
versions	O
of	O
their	O
Pentium	B-General_Concept
class	O
CPUs	O
,	O
Microsoft	B-Device
Windows	I-Device
NT	I-Device
v4.0	O
dropped	O
support	O
for	O
anything	O
but	O
IA-32	B-Device
and	O
Alpha	B-Device
.	O
</s>
<s>
With	O
SGI	O
's	O
decision	O
to	O
transition	O
to	O
the	O
Itanium	B-General_Concept
and	O
IA-32	B-Device
architectures	O
in	O
2007	O
(	O
following	O
a	O
2006	O
Chapter	O
11	O
bankruptcy	O
)	O
and	O
2009	O
acquisition	O
by	O
Rackable	O
Systems	O
,	O
Inc.	O
,	O
support	O
ended	O
for	O
the	O
MIPS/IRIX	O
consumer	O
market	O
in	O
December	O
,	O
2013	O
as	O
originally	O
scheduled	O
.	O
</s>
<s>
Through	O
the	O
1990s	O
,	O
the	O
MIPS	B-Device
architecture	I-Device
was	O
widely	O
adopted	O
by	O
the	O
embedded	O
market	O
,	O
including	O
for	O
use	O
in	O
computer	B-Architecture
networking	I-Architecture
,	O
telecommunications	O
,	O
video	B-Application
arcade	I-Application
games	I-Application
,	O
video	B-Device
game	I-Device
consoles	I-Device
,	O
computer	O
printers	O
,	O
digital	O
set-top	O
boxes	O
,	O
digital	B-Application
televisions	I-Application
,	O
DSL	B-Device
and	O
cable	B-Device
modems	I-Device
,	O
and	O
personal	B-Application
digital	I-Application
assistants	I-Application
.	O
</s>
<s>
The	O
low	O
power-consumption	O
and	O
heat	O
characteristics	O
of	O
embedded	O
MIPS	B-Device
implementations	O
,	O
the	O
wide	O
availability	O
of	O
embedded	O
development	O
tools	O
,	O
and	O
knowledge	O
about	O
the	O
architecture	O
means	O
use	O
of	O
MIPS	B-Device
microprocessors	O
in	O
embedded	O
roles	O
is	O
likely	O
to	O
remain	O
common	O
.	O
</s>
<s>
In	O
recent	O
years	O
most	O
of	O
the	O
technology	O
used	O
in	O
the	O
various	O
MIPS	B-Device
generations	O
has	O
been	O
offered	O
as	O
semiconductor	B-Architecture
intellectual	I-Architecture
property	I-Architecture
cores	I-Architecture
(	O
IP	B-Architecture
cores	I-Architecture
)	O
,	O
as	O
building	O
blocks	O
for	O
embedded	B-Architecture
processor	I-Architecture
designs	O
.	O
</s>
<s>
Both	O
32-bit	O
and	O
64-bit	B-Device
basic	O
cores	O
are	O
offered	O
,	O
known	O
as	O
the	O
4K	O
and	O
5K	O
.	O
</s>
<s>
These	O
cores	O
can	O
be	O
mixed	O
with	O
add-in	O
units	O
such	O
as	O
floating-point	B-General_Concept
units	I-General_Concept
(	O
FPU	O
)	O
,	O
single	B-Device
instruction	I-Device
,	I-Device
multiple	I-Device
data	I-Device
(	O
SIMD	B-Device
)	O
systems	O
,	O
various	O
input/output	B-General_Concept
(	O
I/O	B-General_Concept
)	O
devices	O
,	O
etc	O
.	O
</s>
<s>
MIPS	B-Device
cores	O
have	O
been	O
commercially	O
successful	O
,	O
now	O
having	O
many	O
consumer	O
and	O
industrial	O
uses	O
.	O
</s>
<s>
MIPS	B-Device
cores	O
can	O
be	O
found	O
in	O
newer	O
Cisco	O
,	O
Linksys	O
and	O
Mikrotik	O
's	O
routerboard	O
routers	O
,	O
cable	B-Device
modems	I-Device
and	O
asymmetric	O
digital	O
subscriber	O
line	O
(	O
ADSL	O
)	O
modems	O
,	O
smartcards	O
,	O
laser	O
printer	O
engines	O
,	O
set-top	O
boxes	O
,	O
robots	B-Algorithm
,	O
and	O
hand-held	O
computers	O
.	O
</s>
<s>
In	O
cellphones	O
and	O
PDAs	B-Application
,	O
MIPS	B-Device
has	O
been	O
largely	O
unable	O
to	O
displace	O
the	O
incumbent	O
,	O
competing	O
ARM	B-Architecture
architecture	I-Architecture
.	O
</s>
<s>
MIPS	B-General_Concept
architecture	I-General_Concept
processors	I-General_Concept
include	O
:	O
IDT	O
RC32438	O
;	O
ATI/AMD	O
Xilleon	B-General_Concept
;	O
Alchemy	B-Device
Au1000	O
,	O
1100	O
,	O
1200	O
;	O
Broadcom	O
Sentry5	O
;	O
RMI	O
XLR7xx	O
,	O
Cavium	O
Octeon	O
CN30xx	O
,	O
CN31xx	O
,	O
CN36xx	O
,	O
CN38xx	O
and	O
CN5xxx	O
;	O
Infineon	O
Technologies	O
EasyPort	O
,	O
Amazon	O
,	O
Danube	O
,	O
ADM5120	O
,	O
WildPass	O
,	O
INCA-IP	O
,	O
INCA-IP2	O
;	O
Microchip	O
Technology	O
PIC32	O
;	O
NEC	O
EMMA	O
and	O
EMMA2	O
,	O
NEC	O
VR4181A	O
,	O
VR4121	O
,	O
VR4122	O
,	O
VR4181A	O
,	O
VR4300	O
,	O
VR5432	O
,	O
VR5500	O
;	O
Oak	O
Technologies	O
Generation	O
;	O
PMC-Sierra	O
RM11200	O
;	O
QuickLogic	O
QuickMIPS	O
ESP	O
;	O
Toshiba	O
Donau	O
,	O
Toshiba	O
TMPR492x	O
,	O
TX4925	O
,	O
TX9956	O
,	O
TX7901	O
;	O
KOMDIV-32	B-General_Concept
,	O
KOMDIV-64	B-General_Concept
,	O
ELVEES	B-General_Concept
Multicore	I-General_Concept
from	O
Russia	O
.	O
</s>
<s>
One	O
interesting	O
,	O
less	O
common	O
use	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
is	O
in	O
massive	O
processor	O
count	O
supercomputers	B-Architecture
.	O
</s>
<s>
Silicon	O
Graphics	O
(	O
SGI	O
)	O
refocused	O
its	O
business	O
from	O
desktop	O
graphics	O
workstations	B-Device
to	O
the	O
high-performance	B-Architecture
computing	I-Architecture
market	O
in	O
the	O
early	O
1990s	O
.	O
</s>
<s>
The	O
success	O
of	O
the	O
company	O
's	O
first	O
foray	O
into	O
server	O
systems	O
,	O
the	O
Challenge	B-Application
series	O
based	O
on	O
the	O
R4400	B-General_Concept
and	O
R8000	B-General_Concept
,	O
and	O
later	O
R10000	B-General_Concept
,	O
motivated	O
SGI	O
to	O
form	O
a	O
vastly	O
more	O
powerful	O
system	O
.	O
</s>
<s>
The	O
introduction	O
of	O
the	O
integrated	O
R10000	B-General_Concept
allowed	O
SGI	O
to	O
produce	O
a	O
system	O
,	O
the	O
Origin	B-Application
2000	I-Application
,	O
eventually	O
scalable	O
to	O
1024	O
CPUs	O
using	O
its	O
NUMAlink	B-Architecture
cc-NUMA	O
interconnect	O
.	O
</s>
<s>
The	O
Origin	B-Application
2000	I-Application
begat	O
the	O
Origin	O
3000	O
series	O
which	O
topped	O
out	O
with	O
the	O
same	O
1,024	O
maximum	O
CPU	O
count	O
but	O
using	O
the	O
R14000	B-General_Concept
and	O
R16000	B-General_Concept
chips	O
up	O
to	O
700MHz	O
.	O
</s>
<s>
Its	O
MIPS-based	O
supercomputers	B-Architecture
were	O
withdrawn	O
in	O
2005	O
when	O
SGI	O
made	O
the	O
strategic	O
decision	O
to	O
move	O
to	O
Intel	O
's	O
Itanium	B-General_Concept
IA-64	B-General_Concept
architecture	O
.	O
</s>
<s>
A	O
high-performance	B-Architecture
computing	I-Architecture
startup	O
named	O
SiCortex	B-Operating_System
introduced	O
a	O
massively	O
parallel	O
MIPS-based	O
supercomputer	B-Architecture
in	O
2007	O
.	O
</s>
<s>
The	O
most	O
innovative	O
aspect	O
of	O
the	O
system	O
was	O
its	O
multicore	B-Architecture
processing	O
node	O
which	O
integrates	O
six	O
MIPS64	O
cores	O
,	O
a	O
crossbar	O
switch	O
memory	B-General_Concept
controller	I-General_Concept
,	O
interconnect	O
direct	B-General_Concept
memory	I-General_Concept
access	I-General_Concept
(	O
DMA	O
)	O
engine	O
,	O
Gigabit	O
Ethernet	O
and	O
PCI	B-Protocol
Express	O
controllers	O
all	O
on	O
a	O
single	O
chip	O
which	O
consumes	O
only	O
10	O
watts	O
of	O
power	O
,	O
yet	O
has	O
a	O
peak	O
floating	O
point	O
performance	O
of	O
6	O
gigaFLOPS	O
.	O
</s>
<s>
The	O
most	O
powerful	O
configuration	O
,	O
the	O
SC5832	O
,	O
is	O
a	O
single	O
cabinet	O
supercomputer	B-Architecture
consisting	O
of	O
972	O
such	O
node	O
chips	O
for	O
a	O
total	O
of	O
5832	O
MIPS64	O
processor	O
cores	O
and	O
8.2	O
teraFLOPS	O
of	O
peak	O
performance	O
.	O
</s>
<s>
Loongson	B-Language
is	O
a	O
family	O
of	O
MIPS-compatible	O
microprocessors	O
designed	O
by	O
the	O
Chinese	O
Academy	O
of	O
Sciences	O
 '	O
Institute	O
of	O
Computing	O
Technology	O
(	O
ICT	O
)	O
.	O
</s>
<s>
Independently	O
designed	O
by	O
the	O
Chinese	O
,	O
early	O
models	O
lacked	O
support	O
for	O
four	O
instructions	O
that	O
had	O
been	O
patented	O
by	O
MIPS	B-Device
Technologies	O
.	O
</s>
<s>
In	O
June	O
2009	O
,	O
ICT	O
licensed	O
the	O
MIPS32	O
and	O
MIPS64	O
architectures	O
from	O
MIPS	B-Device
Technologies	O
.	O
</s>
<s>
Starting	O
in	O
2006	O
,	O
many	O
companies	O
released	O
Loongson-based	O
computers	O
,	O
including	O
nettops	B-Protocol
and	O
netbooks	B-Device
designed	O
for	O
low-power	O
use	O
.	O
</s>
<s>
In	O
recent	O
years	O
,	O
the	O
Loongson	B-Language
space	O
dedicated	O
chip	O
(	O
1E04/1E0300/1E1000	O
,	O
1F04/1F0300	O
,	O
1J	O
)	O
has	O
been	O
used	O
on	O
3	O
–	O
5	O
Beidou	O
navigation	O
satellites	O
.	O
</s>
<s>
The	O
Dawning	O
6000	O
supercomputer	B-Architecture
,	O
which	O
has	O
a	O
projected	O
performance	O
of	O
over	O
1PFLOPS	O
,	O
will	O
use	O
the	O
Loongson	B-Language
processor	O
.	O
</s>
<s>
By	O
then	O
,	O
Chinese-made	O
high-performance	B-Architecture
computers	I-Architecture
will	O
be	O
expected	O
to	O
achieve	O
two	O
major	O
goals	O
:	O
first	O
,	O
the	O
adoption	O
of	O
domestically	O
made	O
processors	O
;	O
second	O
,	O
the	O
existing	O
cluster-based	O
system	O
structure	O
of	O
high-performance	B-Architecture
computers	I-Architecture
will	O
be	O
changed	O
once	O
performance	O
reaches	O
1PFLOPS	O
.	O
</s>
<s>
Announced	O
in	O
2012	O
,	O
the	O
MIPS	B-Device
Aptiv	O
family	O
includes	O
three	O
32-bit	O
CPU	O
products	O
based	O
on	O
the	O
MIPS32	O
Release	O
3	O
architecture	O
.	O
</s>
<s>
microAptiv	O
is	O
a	O
compact	O
,	O
real-time	O
embedded	B-Architecture
processor	I-Architecture
core	O
with	O
a	O
five-stage	O
pipeline	O
and	O
the	O
microMIPS	O
code	O
compression	O
instruction	O
set	O
.	O
</s>
<s>
microAptiv	O
can	O
be	O
either	O
configured	O
as	O
a	O
microprocessor	O
(	O
microAptiv	O
UP	O
)	O
with	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
and	O
a	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
or	O
as	O
a	O
microcontroller	B-Architecture
(	O
microAptiv	O
UC	O
)	O
with	O
a	O
memory	B-General_Concept
protection	I-General_Concept
unit	I-General_Concept
(	O
MPU	O
)	O
.	O
</s>
<s>
The	O
CPU	O
integrates	O
DSP	O
and	O
SIMD	B-Device
functionality	O
to	O
address	O
signal	O
processing	O
requirements	O
for	O
entry-level	O
embedded	O
segments	O
including	O
industrial	O
control	O
,	O
smart	O
meters	O
,	O
automotive	O
and	O
wired/wireless	O
communications	O
.	O
</s>
<s>
interAptiv	O
is	O
a	O
multiprocessor	B-Operating_System
core	O
leveraging	O
a	O
nine-stage	O
pipeline	O
with	O
multi-threading	O
.	O
</s>
<s>
The	O
core	O
can	O
be	O
used	O
for	O
highly-parallel	O
tasks	O
requiring	O
cost	O
and	O
power	O
optimization	O
,	O
such	O
as	O
smart	O
gateways	O
,	O
baseband	O
processing	O
in	O
LTE	O
user	O
equipment	O
and	O
small	O
cells	O
,	O
solid-state	B-Device
drive	I-Device
(	O
SSD	B-Device
)	O
controllers	O
,	O
and	O
automotive	O
equipment	O
.	O
</s>
<s>
proAptiv	O
is	O
a	O
superscalar	B-General_Concept
,	O
out-of-order	B-General_Concept
processor	I-General_Concept
core	O
that	O
is	O
available	O
in	O
single	O
and	O
multi-core	B-Architecture
product	O
versions	O
.	O
</s>
<s>
Announced	O
in	O
June	O
2013	O
,	O
the	O
MIPS	B-Device
Warrior	O
family	O
includes	O
multiple	O
32-bit	O
and	O
64-bit	B-Device
CPU	I-Device
products	O
based	O
on	O
the	O
MIPS	B-Device
Release	O
5	O
and	O
6	O
architectures	O
.	O
</s>
<s>
32-bit	O
MIPS	B-Device
cores	O
for	O
embedded	O
and	O
microcontroller	B-Architecture
uses	O
:	O
</s>
<s>
MIPS	B-Device
M5100	O
and	O
MIPS	B-Device
M5150	O
cores	O
(	O
MIPS32	O
Release	O
5	O
)	O
:	O
five-stage	O
pipeline	O
architecture	O
,	O
microMIPS	O
ISA	O
,	O
the	O
MIPS	B-Device
DSP	O
Module	O
r2	O
,	O
fast	O
interrupt	O
handling	O
,	O
advanced	O
debug/profiling	O
capabilities	O
and	O
power	O
management	O
.	O
</s>
<s>
64-bit	B-Device
MIPS	B-General_Concept
CPUs	I-General_Concept
for	O
high-performance	O
,	O
low-power	O
embedded	O
uses	O
:	O
</s>
<s>
MIPS	B-Device
I6400	O
multiprocessor	B-Operating_System
core	O
(	O
MIPS64	O
Release	O
6	O
)	O
:	O
simultaneous	O
multi-threading	O
(	O
SMT	O
)	O
,	O
hardware	O
virtualization	O
,	O
128-bit	O
SIMD	B-Device
,	O
advanced	O
power	O
management	O
,	O
multi-context	O
security	O
,	O
extensible	O
to	O
coherent	O
multi-cluster	O
operation	O
.	O
</s>
<s>
32-bit	O
and	O
64-bit	B-Device
MIPS	B-Device
application	O
processors	O
:	O
</s>
<s>
The	O
MIPS	B-Device
rabbit	O
character	O
from	O
Super	B-Application
Mario	I-Application
64	I-Application
was	O
named	O
after	O
the	O
MIPS	B-Device
microprocessor	O
.	O
</s>
