<s>
MIPS	O
(	O
Microprocessor	O
without	O
Interlocked	O
Pipelined	O
Stages	O
)	O
is	O
a	O
family	O
of	O
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
instruction	B-General_Concept
set	I-General_Concept
architectures	I-General_Concept
(	O
ISA	O
)	O
developed	O
by	O
MIPS	O
Computer	O
Systems	O
,	O
now	O
MIPS	O
Technologies	O
,	O
based	O
in	O
the	O
United	O
States	O
.	O
</s>
<s>
There	O
are	O
multiple	O
versions	O
of	O
MIPS	O
:	O
including	O
MIPS	O
I	O
,	O
II	O
,	O
III	O
,	O
IV	O
,	O
and	O
V	O
;	O
as	O
well	O
as	O
five	O
releases	O
of	O
MIPS32/64	O
(	O
for	O
32	O
-	O
and	O
64-bit	B-Device
implementations	O
,	O
respectively	O
)	O
.	O
</s>
<s>
The	O
early	O
MIPS	B-Device
architectures	I-Device
were	O
32-bit	O
;	O
64-bit	B-Device
versions	O
were	O
developed	O
later	O
.	O
</s>
<s>
MIPS32/64	O
primarily	O
differs	O
from	O
MIPS	O
I	O
–	O
V	O
by	O
defining	O
the	O
privileged	O
kernel	O
mode	O
System	O
Control	O
Coprocessor	B-General_Concept
in	O
addition	O
to	O
the	O
user	O
mode	O
architecture	O
.	O
</s>
<s>
The	O
MIPS	B-Device
architecture	I-Device
has	O
several	O
optional	O
extensions	O
.	O
</s>
<s>
MIPS-3D	B-General_Concept
which	O
is	O
a	O
simple	O
set	O
of	O
floating-point	B-Algorithm
SIMD	B-Device
instructions	O
dedicated	O
to	O
common	O
3D	O
tasks	O
,	O
MDMX	B-General_Concept
(	O
MaDMaX	O
)	O
which	O
is	O
a	O
more	O
extensive	O
integer	O
SIMD	B-Device
instruction	B-General_Concept
set	I-General_Concept
using	O
the	O
64-bit	B-Device
floating-point	B-Algorithm
registers	O
,	O
MIPS16e	O
which	O
adds	O
compression	B-Architecture
to	I-Architecture
the	I-Architecture
instruction	I-Architecture
stream	I-Architecture
to	O
make	O
programs	O
take	O
up	O
less	O
room	O
,	O
and	O
MIPS	O
MT	O
,	O
which	O
adds	O
multithreading	B-General_Concept
capability	O
.	O
</s>
<s>
Computer	B-General_Concept
architecture	I-General_Concept
courses	O
in	O
universities	O
and	O
technical	O
schools	O
often	O
study	O
the	O
MIPS	B-Device
architecture	I-Device
.	O
</s>
<s>
The	O
architecture	O
greatly	O
influenced	O
later	O
RISC	B-Architecture
architectures	I-Architecture
such	O
as	O
Alpha	B-Device
.	O
</s>
<s>
In	O
March	O
2021	O
,	O
MIPS	O
announced	O
that	O
the	O
development	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
had	O
ended	O
as	O
the	O
company	O
is	O
making	O
the	O
transition	O
to	O
RISC-V	B-Device
.	O
</s>
<s>
The	O
first	O
version	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
was	O
designed	O
by	O
MIPS	O
Computer	O
Systems	O
for	O
its	O
R2000	B-Device
microprocessor	I-Device
,	O
the	O
first	O
MIPS	O
implementation	O
.	O
</s>
<s>
Both	O
MIPS	O
and	O
the	O
R2000	B-Device
were	O
introduced	O
together	O
in	O
1985	O
.	O
</s>
<s>
MIPS	O
Computer	O
Systems	O
 '	O
R6000	B-Device
microprocessor	O
(	O
1989	O
)	O
was	O
the	O
first	O
MIPS	O
II	O
implementation	O
.	O
</s>
<s>
Designed	O
for	O
servers	O
,	O
the	O
R6000	B-Device
was	O
fabricated	O
and	O
sold	O
by	O
Bipolar	O
Integrated	O
Technology	O
,	O
but	O
was	O
a	O
commercial	O
failure	O
.	O
</s>
<s>
During	O
the	O
mid-1990s	O
,	O
many	O
new	O
32-bit	O
MIPS	B-General_Concept
processors	I-General_Concept
for	O
embedded	B-Architecture
systems	I-Architecture
were	O
MIPS	O
II	O
implementations	O
because	O
the	O
introduction	O
of	O
the	O
64-bit	B-Device
MIPS	O
III	O
architecture	O
in	O
1991	O
left	O
MIPS	O
II	O
as	O
the	O
newest	O
32-bit	O
MIPS	B-Device
architecture	I-Device
until	O
MIPS32	O
was	O
introduced	O
in	O
1999	O
.	O
</s>
<s>
MIPS	O
Computer	O
Systems	O
 '	O
R4000	B-General_Concept
microprocessor	O
(	O
1991	O
)	O
was	O
the	O
first	O
MIPS	O
III	O
implementation	O
.	O
</s>
<s>
It	O
was	O
designed	O
for	O
use	O
in	O
personal	B-Device
,	O
workstation	B-Device
,	O
and	O
server	B-Application
computers	I-Application
.	O
</s>
<s>
MIPS	O
Computer	O
Systems	O
aggressively	O
promoted	O
the	O
MIPS	B-Device
architecture	I-Device
and	O
R4000	B-General_Concept
,	O
establishing	O
the	O
Advanced	B-Device
Computing	I-Device
Environment	I-Device
(	O
ACE	O
)	O
consortium	O
to	O
advance	O
its	O
Advanced	B-Device
RISC	I-Device
Computing	I-Device
(	O
ARC	B-Device
)	O
standard	O
,	O
which	O
aimed	O
to	O
establish	O
MIPS	O
as	O
the	O
dominant	O
personal	B-Device
computing	I-Device
platform	O
.	O
</s>
<s>
ARC	B-Device
found	O
little	O
success	O
in	O
personal	B-Device
computers	I-Device
,	O
but	O
the	O
R4000	B-General_Concept
(	O
and	O
the	O
R4400	B-General_Concept
derivative	O
)	O
were	O
widely	O
used	O
in	O
workstation	B-Device
and	O
server	B-Application
computers	I-Application
,	O
especially	O
by	O
its	O
largest	O
user	O
,	O
Silicon	O
Graphics	O
.	O
</s>
<s>
Other	O
uses	O
of	O
the	O
R4000	B-General_Concept
included	O
high-end	O
embedded	B-Architecture
systems	I-Architecture
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
Quantum	O
Effect	O
Design	O
's	O
R4600	B-Device
(	O
1993	O
)	O
and	O
its	O
derivatives	O
was	O
widely	O
used	O
in	O
high-end	O
embedded	B-Architecture
systems	I-Architecture
and	O
low-end	O
workstations	B-Device
and	O
servers	O
.	O
</s>
<s>
MIPS	O
Technologies	O
 '	O
R4200	B-Device
(	O
1994	O
)	O
,	O
was	O
designed	O
for	O
embedded	B-Architecture
systems	I-Architecture
,	O
laptop	O
,	O
and	O
personal	B-Device
computers	I-Device
.	O
</s>
<s>
A	O
derivative	O
,	O
the	O
R4300i	O
,	O
fabricated	O
by	O
NEC	O
Electronics	O
,	O
was	O
used	O
in	O
the	O
Nintendo	B-Operating_System
64	I-Operating_System
game	O
console	O
.	O
</s>
<s>
The	O
Nintendo	B-Operating_System
64	I-Operating_System
,	O
along	O
with	O
the	O
PlayStation	B-Device
,	O
were	O
among	O
the	O
highest	O
volume	O
users	O
of	O
MIPS	B-General_Concept
architecture	I-General_Concept
processors	I-General_Concept
in	O
the	O
mid-1990s	O
.	O
</s>
<s>
The	O
first	O
MIPS	O
IV	O
implementation	O
was	O
the	O
MIPS	O
Technologies	O
R8000	B-General_Concept
microprocessor	O
chipset	O
(	O
1994	O
)	O
.	O
</s>
<s>
The	O
design	O
of	O
the	O
R8000	B-General_Concept
began	O
at	O
Silicon	O
Graphics	O
,	O
Inc	O
.	O
and	O
it	O
was	O
only	O
used	O
in	O
high-end	O
workstations	B-Device
and	O
servers	O
for	O
scientific	O
and	O
technical	O
applications	O
where	O
high	O
performance	O
on	O
large	O
floating-point	B-Algorithm
workloads	O
was	O
important	O
.	O
</s>
<s>
Later	O
implementations	O
were	O
the	O
MIPS	O
Technologies	O
R10000	B-General_Concept
(	O
1996	O
)	O
and	O
the	O
Quantum	O
Effect	O
Devices	O
R5000	B-General_Concept
(	O
1996	O
)	O
and	O
RM7000	O
(	O
1998	O
)	O
.	O
</s>
<s>
The	O
R10000	B-General_Concept
,	O
fabricated	O
and	O
sold	O
by	O
NEC	O
Electronics	O
and	O
Toshiba	O
,	O
and	O
its	O
derivatives	O
were	O
used	O
by	O
NEC	O
,	O
Pyramid	O
Technology	O
,	O
Silicon	O
Graphics	O
,	O
and	O
Tandem	O
Computers	O
(	O
among	O
others	O
)	O
in	O
workstations	B-Device
,	O
servers	O
,	O
and	O
supercomputers	B-Architecture
.	O
</s>
<s>
The	O
R5000	B-General_Concept
and	O
R7000	O
found	O
use	O
in	O
high-end	O
embedded	B-Architecture
systems	I-Architecture
,	O
personal	B-Device
computers	I-Device
,	O
and	O
low-end	O
workstations	B-Device
and	O
servers	O
.	O
</s>
<s>
A	O
derivative	O
of	O
the	O
R5000	B-General_Concept
from	O
Toshiba	O
,	O
the	O
R5900	O
,	O
was	O
used	O
in	O
Sony	O
Computer	O
Entertainment	O
's	O
Emotion	B-Architecture
Engine	I-Architecture
,	O
which	O
powered	O
its	O
PlayStation	B-Device
2	I-Device
game	O
console	O
.	O
</s>
<s>
Announced	O
on	O
October	O
21	O
,	O
1996	O
,	O
at	O
the	O
Microprocessor	O
Forum	O
1996	O
alongside	O
the	O
MIPS	B-General_Concept
Digital	I-General_Concept
Media	I-General_Concept
Extensions	I-General_Concept
(	O
MDMX	B-General_Concept
)	O
extension	O
,	O
MIPS	O
V	O
was	O
designed	O
to	O
improve	O
the	O
performance	O
of	O
3D	O
graphics	O
transformations	O
.	O
</s>
<s>
In	O
the	O
mid-1990s	O
,	O
a	O
major	O
use	O
of	O
non-embedded	O
MIPS	O
microprocessors	O
were	O
graphics	O
workstations	B-Device
from	O
Silicon	O
Graphics	O
.	O
</s>
<s>
MIPS	O
V	O
was	O
completed	O
by	O
the	O
integer-only	O
MDMX	B-General_Concept
extension	O
to	O
provide	O
a	O
complete	O
system	O
for	O
improving	O
the	O
performance	O
of	O
3D	O
graphics	O
applications	O
.	O
</s>
<s>
While	O
there	O
have	O
not	O
been	O
any	O
MIPS	O
V	O
implementations	O
,	O
MIPS64	O
Release	O
1	O
(	O
1999	O
)	O
was	O
based	O
on	O
MIPS	O
V	O
and	O
retains	O
all	O
of	O
its	O
features	O
as	O
an	O
optional	O
Coprocessor	B-General_Concept
1	O
(	O
FPU	O
)	O
feature	O
called	O
Paired-Single	O
.	O
</s>
<s>
Through	O
MIPS	O
V	O
,	O
each	O
successive	O
version	O
was	O
a	O
strict	O
superset	O
of	O
the	O
previous	O
version	O
,	O
but	O
this	O
property	O
was	O
found	O
to	O
be	O
a	O
problem	O
,	O
and	O
the	O
architecture	O
definition	O
was	O
changed	O
to	O
define	O
a	O
32-bit	O
and	O
a	O
64-bit	B-Device
architecture	I-Device
:	O
MIPS32	O
and	O
MIPS64	O
.	O
</s>
<s>
Philips	O
,	O
LSI	O
Logic	O
,	O
IDT	O
,	O
Raza	O
Microelectronics	O
,	O
Inc.	O
,	O
Cavium	O
,	O
Loongson	B-Language
Technology	I-Language
and	O
Ingenic	B-Device
Semiconductor	I-Device
have	O
since	O
joined	O
them	O
.	O
</s>
<s>
In	O
December	O
2018	O
,	O
Wave	O
Computing	O
,	O
the	O
new	O
owner	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
,	O
announced	O
that	O
MIPS	B-Device
ISA	I-Device
would	O
be	O
open-sourced	O
in	O
a	O
program	O
dubbed	O
the	O
MIPS	O
Open	O
initiative	O
.	O
</s>
<s>
The	O
program	O
was	O
intended	O
to	O
open	O
up	O
access	O
to	O
the	O
most	O
recent	O
versions	O
of	O
both	O
the	O
32-bit	O
and	O
64-bit	B-Device
designs	O
making	O
them	O
available	O
without	O
any	O
licensing	O
or	O
royalty	O
fees	O
as	O
well	O
as	O
granting	O
participants	O
licenses	O
to	O
existing	O
MIPS	O
patents	O
.	O
</s>
<s>
In	O
March	O
2021	O
,	O
Wave	O
Computing	O
announced	O
that	O
the	O
development	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
has	O
ceased	O
.	O
</s>
<s>
The	O
company	O
has	O
joined	O
the	O
RISC-V	B-Device
foundation	I-Device
and	O
future	O
processor	O
designs	O
will	O
be	O
based	O
on	O
the	O
RISC-V	B-Device
architecture	I-Device
.	O
</s>
<s>
In	O
spite	O
of	O
this	O
,	O
some	O
licensees	O
such	O
as	O
Loongson	B-Language
continue	O
with	O
new	O
extension	O
of	O
MIPS-compatible	O
ISAs	O
on	O
their	O
own	O
.	O
</s>
<s>
MIPS	O
is	O
a	O
modular	O
architecture	O
supporting	O
up	O
to	O
four	O
coprocessors	B-General_Concept
(	O
CP0/1/2/3	O
)	O
.	O
</s>
<s>
In	O
MIPS	O
terminology	O
,	O
CP0	O
is	O
the	O
System	O
Control	O
Coprocessor	B-General_Concept
(	O
an	O
essential	O
part	O
of	O
the	O
processor	O
that	O
is	O
implementation-defined	O
in	O
MIPS	O
I	O
–	O
V	O
)	O
,	O
CP1	O
is	O
an	O
optional	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
and	O
CP2/3	O
are	O
optional	O
implementation-defined	O
coprocessors	B-General_Concept
(	O
MIPS	O
III	O
removed	O
CP3	O
and	O
reused	O
its	O
opcodes	O
for	O
other	O
purposes	O
)	O
.	O
</s>
<s>
For	O
example	O
,	O
in	O
the	O
PlayStation	B-Device
video	B-Device
game	I-Device
console	I-Device
,	O
CP2	O
is	O
the	O
Geometry	O
Transformation	O
Engine	O
(	O
GTE	O
)	O
,	O
which	O
accelerates	O
the	O
processing	O
of	O
geometry	O
in	O
3D	O
computer	O
graphics	O
.	O
</s>
<s>
MIPS	O
is	O
a	O
load/store	B-Architecture
architecture	I-Architecture
(	O
also	O
known	O
as	O
a	O
register-register	O
architecture	O
)	O
;	O
except	O
for	O
the	O
load/store	B-General_Concept
instructions	I-General_Concept
used	O
to	O
access	O
memory	B-General_Concept
,	O
all	O
instructions	O
operate	O
on	O
the	O
registers	O
.	O
</s>
<s>
The	O
following	O
are	O
the	O
three	O
formats	O
used	O
for	O
the	O
core	O
instruction	B-General_Concept
set	I-General_Concept
:	O
</s>
<s>
Only	O
one	O
addressing	B-Language
mode	I-Language
is	O
supported	O
:	O
base	O
+	O
displacement	O
.	O
</s>
<s>
All	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
compute	O
the	O
memory	B-General_Concept
address	O
by	O
summing	O
the	O
base	O
with	O
the	O
sign-extended	O
16-bit	O
immediate	O
.	O
</s>
<s>
MIPS	O
I	O
requires	O
all	O
memory	B-General_Concept
accesses	O
to	O
be	O
aligned	O
to	O
their	O
natural	O
word	O
boundaries	O
,	O
otherwise	O
an	O
exception	O
is	O
signaled	O
.	O
</s>
<s>
To	O
support	O
efficient	O
unaligned	O
memory	B-General_Concept
accesses	O
,	O
there	O
are	O
load/store	O
word	O
instructions	O
suffixed	O
by	O
"	O
left	O
"	O
or	O
"	O
right	O
"	O
.	O
</s>
<s>
All	O
load	O
instructions	O
are	O
followed	O
by	O
a	O
load	O
delay	B-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
The	O
instruction	O
in	O
the	O
load	O
delay	B-General_Concept
slot	I-General_Concept
cannot	O
use	O
the	O
data	O
loaded	O
by	O
the	O
load	O
instruction	O
.	O
</s>
<s>
The	O
load	O
delay	B-General_Concept
slot	I-General_Concept
can	O
be	O
filled	O
with	O
an	O
instruction	O
that	O
is	O
not	O
dependent	O
on	O
the	O
load	O
;	O
a	O
nop	O
is	O
substituted	O
if	O
such	O
an	O
instruction	O
cannot	O
be	O
found	O
.	O
</s>
<s>
For	O
multiplication	O
,	O
the	O
high	O
-	O
and	O
low-order	O
halves	O
of	O
the	O
64-bit	B-Device
product	O
is	O
written	O
to	O
HI	O
and	O
LO	O
(	O
respectively	O
)	O
.	O
</s>
<s>
All	O
MIPS	O
I	O
control	O
flow	O
instructions	O
are	O
followed	O
by	O
a	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
Unless	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
is	O
filled	O
by	O
an	O
instruction	O
performing	O
useful	O
work	O
,	O
an	O
nop	O
is	O
substituted	O
.	O
</s>
<s>
Absolute	O
jumps	O
(	O
"	O
Jump	O
"	O
and	O
"	O
Jump	O
and	O
Link	O
"	O
)	O
compute	O
the	O
address	O
to	O
which	O
control	O
is	O
transferred	O
by	O
shifting	O
the	O
26-bit	O
instr_index	O
left	O
by	O
two	O
bits	O
and	O
concatenating	O
the	O
28-bit	O
result	O
with	O
the	O
four	O
high-order	O
bits	O
of	O
the	O
address	O
of	O
the	O
instruction	O
in	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
The	O
address	O
sourced	O
from	O
the	O
GPR	O
must	O
be	O
word-aligned	O
,	O
else	O
an	O
exception	O
is	O
signaled	O
after	O
the	O
instruction	O
in	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
is	O
executed	O
.	O
</s>
<s>
Branch	O
and	O
jump	O
instructions	O
that	O
link	O
(	O
except	O
for	O
"	O
Jump	O
and	O
Link	O
Register	O
"	O
)	O
save	O
the	O
return	B-Language
address	I-Language
to	O
GPR	O
31	O
.	O
</s>
<s>
The	O
"	O
Jump	O
and	O
Link	O
Register	O
"	O
instruction	O
permits	O
the	O
return	B-Language
address	I-Language
to	O
be	O
saved	O
to	O
any	O
writable	O
GPR	O
.	O
</s>
<s>
MIPS	O
has	O
32	O
floating-point	B-Algorithm
registers	O
.	O
</s>
<s>
MIPS	O
II	O
removed	O
the	O
load	O
delay	B-General_Concept
slot	I-General_Concept
and	O
added	O
several	O
sets	O
of	O
instructions	O
.	O
</s>
<s>
For	O
shared-memory	O
multiprocessing	O
,	O
the	O
Synchronize	O
Shared	O
Memory	B-General_Concept
,	O
Load	O
Linked	O
Word	O
,	O
and	O
Store	O
Conditional	O
Word	O
instructions	O
were	O
added	O
.	O
</s>
<s>
All	O
existing	O
branch	O
instructions	O
were	O
given	O
branch-likely	O
versions	O
that	O
executed	O
the	O
instruction	O
in	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
only	O
if	O
the	O
branch	O
is	O
taken	O
.	O
</s>
<s>
These	O
instructions	O
improve	O
performance	O
in	O
certain	O
cases	O
by	O
allowing	O
useful	O
instructions	O
to	O
fill	O
the	O
branch	B-General_Concept
delay	I-General_Concept
slot	I-General_Concept
.	O
</s>
<s>
Doubleword	O
load	B-General_Concept
and	I-General_Concept
store	I-General_Concept
instructions	I-General_Concept
for	O
COP1	O
–	O
3	O
were	O
added	O
.	O
</s>
<s>
Consistent	O
with	O
other	O
memory	B-General_Concept
access	O
instructions	O
,	O
these	O
loads	O
and	O
stores	O
required	O
the	O
doubleword	O
to	O
be	O
naturally	O
aligned	O
.	O
</s>
<s>
The	O
instruction	B-General_Concept
set	I-General_Concept
for	O
the	O
floating	B-Algorithm
point	I-Algorithm
coprocessor	B-General_Concept
also	O
had	O
several	O
instructions	O
added	O
to	O
it	O
.	O
</s>
<s>
An	O
IEEE	O
754-compliant	O
floating-point	B-Algorithm
square	O
root	O
instruction	O
was	O
added	O
.	O
</s>
<s>
A	O
set	O
of	O
instructions	O
that	O
converted	O
single	O
-	O
and	O
double-precision	O
floating-point	B-Algorithm
numbers	I-Algorithm
to	O
32-bit	O
words	O
were	O
added	O
.	O
</s>
<s>
These	O
complemented	O
the	O
existing	O
conversion	O
instructions	O
by	O
allowing	O
the	O
IEEE	O
rounding	O
mode	O
to	O
be	O
specified	O
by	O
the	O
instruction	O
instead	O
of	O
the	O
Floating	B-Algorithm
Point	I-Algorithm
Control	O
and	O
Status	O
Register	O
.	O
</s>
<s>
MIPS	O
III	O
is	O
a	O
backwards-compatible	B-General_Concept
extension	O
of	O
MIPS	O
II	O
that	O
added	O
support	O
for	O
64-bit	B-Device
memory	B-General_Concept
addressing	O
and	O
integer	O
operations	O
.	O
</s>
<s>
The	O
64-bit	B-Device
data	O
type	O
is	O
called	O
a	O
doubleword	O
,	O
and	O
MIPS	O
III	O
extended	O
the	O
general-purpose	O
registers	O
,	O
HI/LO	O
registers	O
,	O
and	O
program	O
counter	O
to	O
64	B-Device
bits	I-Device
to	O
support	O
it	O
.	O
</s>
<s>
In	O
MIPS	O
III	O
it	O
sign-extends	O
words	O
to	O
64	B-Device
bits	I-Device
.	O
</s>
<s>
The	O
R	O
instruction	O
format	O
's	O
inability	O
to	O
specify	O
the	O
full	O
shift	O
distance	O
for	O
64-bit	B-Device
shifts	O
(	O
its	O
5-bit	O
shift	O
amount	O
field	O
is	O
too	O
narrow	O
to	O
specify	O
the	O
shift	O
distance	O
for	O
doublewords	O
)	O
required	O
MIPS	O
III	O
to	O
provide	O
three	O
64-bit	B-Device
versions	O
of	O
each	O
MIPS	O
I	O
shift	O
instruction	O
.	O
</s>
<s>
The	O
first	O
version	O
is	O
a	O
64-bit	B-Device
version	O
of	O
the	O
original	O
shift	O
instructions	O
,	O
used	O
to	O
specify	O
constant	O
shift	O
distances	O
of	O
0	O
–	O
31	O
bits	O
.	O
</s>
<s>
The	O
second	O
version	O
is	O
similar	O
to	O
the	O
first	O
,	O
but	O
adds	O
3210	O
the	O
shift	O
amount	O
field	O
's	O
value	O
so	O
that	O
constant	O
shift	O
distances	O
of	O
32	O
–	O
64	B-Device
bits	I-Device
can	O
be	O
specified	O
.	O
</s>
<s>
This	O
feature	O
only	O
affected	O
the	O
implementation-defined	O
System	O
Control	O
Processor	O
(	O
Coprocessor	B-General_Concept
0	O
)	O
.	O
</s>
<s>
MIPS	O
III	O
removed	O
the	O
Coprocessor	B-General_Concept
3	O
(	O
CP3	O
)	O
support	O
instructions	O
,	O
and	O
reused	O
its	O
opcodes	O
for	O
the	O
new	O
doubleword	O
instructions	O
.	O
</s>
<s>
The	O
remaining	O
coprocessors	B-General_Concept
gained	O
instructions	O
to	O
move	O
doublewords	O
between	O
coprocessor	B-General_Concept
registers	O
and	O
the	O
GPRs	O
.	O
</s>
<s>
The	O
floating	O
general	O
registers	O
(	O
FGRs	O
)	O
were	O
extended	O
to	O
64	B-Device
bits	I-Device
and	O
the	O
requirement	O
for	O
instructions	O
to	O
use	O
even-numbered	O
register	O
only	O
was	O
removed	O
.	O
</s>
<s>
This	O
is	O
incompatible	O
with	O
earlier	O
versions	O
of	O
the	O
architecture	O
;	O
a	O
bit	O
in	O
the	O
floating-point	B-Algorithm
control/status	O
register	O
is	O
used	O
to	O
operate	O
the	O
MIPS	O
III	O
floating-point	B-General_Concept
unit	I-General_Concept
(	O
FPU	O
)	O
in	O
a	O
MIPS	O
I	O
-	O
and	O
II-compatible	O
mode	O
.	O
</s>
<s>
The	O
floating-point	B-Algorithm
control	O
registers	O
were	O
not	O
extended	O
for	O
compatibility	O
.	O
</s>
<s>
The	O
only	O
new	O
floating-point	B-Algorithm
instructions	O
added	O
were	O
those	O
to	O
copy	O
doublewords	O
between	O
the	O
CPU	O
and	O
FPU	O
convert	O
single	O
-	O
and	O
double-precision	O
floating-point	B-Algorithm
numbers	I-Algorithm
into	O
doubleword	O
integers	O
and	O
vice	O
versa	O
.	O
</s>
<s>
MIPS	O
IV	O
was	O
designed	O
to	O
mainly	O
improve	O
floating-point	B-Algorithm
(	O
FP	O
)	O
performance	O
.	O
</s>
<s>
To	O
improve	O
access	O
to	O
operands	O
,	O
an	O
indexed	B-Language
addressing	I-Language
mode	O
(	O
base	O
+	O
index	O
,	O
both	O
sourced	O
from	O
GPRs	O
)	O
for	O
FP	O
loads	O
and	O
stores	O
was	O
added	O
,	O
as	O
were	O
prefetch	B-General_Concept
instructions	I-General_Concept
for	O
performing	O
memory	B-General_Concept
prefetching	O
and	O
specifying	O
cache	O
hints	O
(	O
these	O
supported	O
both	O
the	O
base	O
+	O
offset	O
and	O
base	O
+	O
index	O
addressing	B-Language
modes	I-Language
)	O
.	O
</s>
<s>
To	O
alleviate	O
the	O
bottleneck	O
caused	O
by	O
a	O
single	O
condition	O
bit	O
,	O
seven	O
condition	O
code	O
bits	O
were	O
added	O
to	O
the	O
floating-point	B-Algorithm
control	O
and	O
status	O
register	O
,	O
bringing	O
the	O
total	O
to	O
eight	O
.	O
</s>
<s>
FP	O
comparison	O
and	O
branch	O
instructions	O
were	O
redefined	O
so	O
they	O
could	O
specify	O
which	O
condition	O
bit	O
was	O
written	O
or	O
read	O
(	O
respectively	O
)	O
;	O
and	O
the	O
delay	B-General_Concept
slot	I-General_Concept
in	O
between	O
an	O
FP	O
branch	O
that	O
read	O
the	O
condition	O
bit	O
written	O
to	O
by	O
a	O
prior	O
FP	O
comparison	O
was	O
removed	O
.	O
</s>
<s>
Support	O
for	O
partial	B-General_Concept
predication	I-General_Concept
was	O
added	O
in	O
the	O
form	O
of	O
conditional	B-General_Concept
move	I-General_Concept
instructions	O
for	O
both	O
GPRs	O
and	O
FPRs	O
;	O
and	O
an	O
implementation	O
could	O
choose	O
between	O
having	O
precise	O
or	O
imprecise	O
exceptions	O
for	O
IEEE	O
754	O
traps	O
.	O
</s>
<s>
MIPS	O
V	O
added	O
a	O
new	O
data	O
type	O
,	O
the	O
Paired	O
Single	O
(	O
PS	O
)	O
,	O
which	O
consisted	O
of	O
two	O
single-precision	O
(	O
32-bit	O
)	O
floating-point	B-Algorithm
numbers	I-Algorithm
stored	O
in	O
the	O
existing	O
64-bit	B-Device
floating-point	B-Algorithm
registers	O
.	O
</s>
<s>
Variants	O
of	O
existing	O
floating-point	B-Algorithm
instructions	O
for	O
arithmetic	O
,	O
compare	O
and	O
conditional	B-General_Concept
move	I-General_Concept
were	O
added	O
to	O
operate	O
on	O
this	O
data	O
type	O
in	O
a	O
SIMD	B-Device
fashion	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
instruction	B-General_Concept
set	I-General_Concept
to	O
exploit	O
floating-point	B-Algorithm
SIMD	B-Device
with	O
existing	O
resources	O
.	O
</s>
<s>
The	O
first	O
release	O
of	O
MIPS32	O
,	O
based	O
on	O
MIPS	O
II	O
,	O
added	O
conditional	B-General_Concept
moves	I-General_Concept
,	O
prefetch	B-General_Concept
instructions	I-General_Concept
,	O
and	O
other	O
features	O
from	O
the	O
R4000	B-General_Concept
and	O
R5000	B-General_Concept
families	O
of	O
64-bit	B-Device
processors	I-Device
.	O
</s>
<s>
The	O
MUL	O
and	O
MADD	O
(	O
multiply-add	B-Algorithm
)	O
instructions	O
,	O
previously	O
available	O
in	O
some	O
implementations	O
,	O
were	O
added	O
to	O
the	O
MIPS32	O
and	O
MIPS64	O
specifications	O
,	O
as	O
were	O
cache	B-Architecture
control	I-Architecture
instructions	I-Architecture
.	O
</s>
<s>
a	O
new	O
family	O
of	O
branches	O
with	O
no	O
delay	B-General_Concept
slot	I-General_Concept
:	O
</s>
<s>
index	O
jump	O
instructions	O
with	O
no	O
delay	B-General_Concept
slot	I-General_Concept
designed	O
to	O
support	O
large	O
absolute	O
addresses	O
.	O
</s>
<s>
The	O
microMIPS32/64	O
architectures	O
are	O
supersets	O
of	O
the	O
MIPS32	O
and	O
MIPS64	O
architectures	O
(	O
respectively	O
)	O
designed	O
to	O
replace	O
the	O
MIPS16e	B-Device
ASE	I-Device
.	O
</s>
<s>
These	O
ASEs	O
provide	O
features	O
that	O
improve	O
the	O
efficiency	O
and	O
performance	O
of	O
certain	O
workloads	O
,	O
such	O
as	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
.	O
</s>
<s>
MIPS	O
Digital	B-General_Concept
Signal	I-General_Concept
Processing	I-General_Concept
(	O
DSP	O
)	O
The	O
DSP	O
ASE	O
is	O
an	O
optional	O
extension	O
to	O
the	O
MIPS32/MIPS64	O
Release2	O
and	O
newer	O
instruction	B-General_Concept
sets	I-General_Concept
which	O
can	O
be	O
used	O
to	O
accelerate	O
a	O
large	O
range	O
of	O
"	O
media	O
"	O
computations	O
—	O
particularly	O
audio	O
and	O
video	O
.	O
</s>
<s>
The	O
DSP	O
module	O
comprises	O
a	O
set	O
of	O
instructions	O
and	O
state	O
in	O
the	O
integer	O
pipeline	B-General_Concept
and	O
requires	O
minimal	O
additional	O
logic	O
to	O
implement	O
in	O
MIPS	B-General_Concept
processor	I-General_Concept
cores	O
.	O
</s>
<s>
This	O
revision	O
adds	O
extra	O
instructions	O
to	O
the	O
original	O
ASE	O
,	O
but	O
is	O
otherwise	O
backwards-compatible	B-General_Concept
with	O
it	O
.	O
</s>
<s>
Unlike	O
the	O
bulk	O
of	O
the	O
MIPS	B-Device
architecture	I-Device
,	O
it	O
's	O
a	O
fairly	O
irregular	O
set	O
of	O
operations	O
,	O
many	O
chosen	O
for	O
a	O
particular	O
relevance	O
to	O
some	O
key	O
algorithm	O
.	O
</s>
<s>
The	O
existing	O
integer	O
multiplication	O
and	O
multiply-accumulate	B-Algorithm
instructions	O
,	O
which	O
deliver	O
results	O
into	O
a	O
double-size	O
accumulator	O
(	O
called	O
"	O
hi/lo	O
"	O
and	O
64	B-Device
bits	I-Device
on	O
MIPS32	O
CPUs	O
)	O
.	O
</s>
<s>
The	O
DSP	O
ASE	O
adds	O
three	O
more	O
accumulators	O
,	O
and	O
some	O
different	O
flavours	O
of	O
multiply-accumulate	B-Algorithm
.	O
</s>
<s>
SIMD	B-Device
instructions	O
operating	O
on	O
4	O
x	O
unsigned	O
bytes	O
or	O
2	O
x	O
16-bit	O
values	O
packed	O
into	O
a	O
32-bit	O
register	O
(	O
the	O
64-bit	B-Device
variant	O
of	O
the	O
DSP	O
ASE	O
supports	O
larger	O
vectors	O
,	O
too	O
)	O
.	O
</s>
<s>
SIMD	B-Device
operations	O
are	O
basic	O
arithmetic	O
,	O
shifts	O
and	O
some	O
multiply-accumulate	B-Algorithm
type	O
operations	O
.	O
</s>
<s>
MIPS	O
SIMD	B-Device
architecture	O
(	O
MSA	O
)	O
Instruction	B-General_Concept
set	I-General_Concept
extensions	O
designed	O
to	O
accelerate	O
multimedia	O
.	O
</s>
<s>
MIPS	O
multi-threading	O
Each	O
multi-threaded	O
MIPS	O
core	O
can	O
support	O
up	O
to	O
two	O
VPEs	O
(	O
Virtual	O
Processing	O
Elements	O
)	O
which	O
share	O
a	O
single	O
pipeline	B-General_Concept
as	O
well	O
as	O
other	O
hardware	O
resources	O
.	O
</s>
<s>
However	O
,	O
since	O
each	O
VPE	O
includes	O
a	O
complete	O
copy	O
of	O
the	O
processor	O
state	O
as	O
seen	O
by	O
the	O
software	O
system	O
,	O
each	O
VPE	O
appears	O
as	O
a	O
complete	O
standalone	O
processor	O
to	O
an	O
SMP	B-Operating_System
Linux	B-Application
operating	I-Application
system	I-Application
.	O
</s>
<s>
SmartMIPS	O
SmartMIPS	O
is	O
an	O
Application-Specific	O
Extension	O
(	O
ASE	O
)	O
designed	O
by	O
Gemplus	O
International	O
and	O
MIPS	O
Technologies	O
to	O
improve	O
performance	O
and	O
reduce	O
memory	B-General_Concept
consumption	O
for	O
smart	O
card	O
software	O
.	O
</s>
<s>
MIPS	B-General_Concept
Digital	I-General_Concept
Media	I-General_Concept
eXtension	I-General_Concept
(	O
MDMX	B-General_Concept
)	O
Multimedia	O
application	O
accelerations	O
that	O
were	O
common	O
in	O
the	O
1990s	O
on	O
RISC	B-Architecture
and	O
CISC	O
systems	O
.	O
</s>
<s>
The	O
O32	O
ABI	B-Operating_System
is	O
the	O
most	O
commonly-used	O
ABI	B-Operating_System
,	O
owing	O
to	O
its	O
status	O
as	O
the	O
original	O
System	B-Operating_System
V	I-Operating_System
ABI	B-Operating_System
for	O
MIPS	O
.	O
</s>
<s>
The	O
return	B-Language
value	I-Language
is	O
stored	O
in	O
register	O
;	O
a	O
second	O
return	B-Language
value	I-Language
may	O
be	O
stored	O
in	O
.	O
</s>
<s>
The	O
ABI	B-Operating_System
took	O
shape	O
in	O
1990	O
and	O
was	O
last	O
updated	O
in	O
1994	O
.	O
</s>
<s>
This	O
perceived	O
slowness	O
,	O
along	O
with	O
an	O
antique	O
floating-point	B-Algorithm
model	O
with	O
only	O
16	O
registers	O
,	O
has	O
encouraged	O
the	O
proliferation	O
of	O
many	O
other	O
calling	O
conventions	O
.	O
</s>
<s>
It	O
is	O
only	O
defined	O
for	O
32-bit	O
MIPS	O
,	O
but	O
GCC	B-Application
has	O
created	O
a	O
64-bit	B-Device
variation	O
called	O
O64	O
.	O
</s>
<s>
For	O
64-bit	B-Device
,	O
the	O
N64	B-Operating_System
ABI	B-Operating_System
by	O
Silicon	O
Graphics	O
is	O
most	O
commonly	O
used	O
.	O
</s>
<s>
The	O
most	O
important	O
improvement	O
is	O
that	O
eight	O
registers	O
are	O
now	O
available	O
for	O
argument	O
passing	O
;	O
it	O
also	O
increases	O
the	O
number	O
of	O
floating-point	B-Algorithm
registers	O
to	O
32	O
.	O
</s>
<s>
There	O
is	O
also	O
an	O
ILP32	O
version	O
called	O
N32	O
,	O
which	O
uses	O
32-bit	O
pointers	O
for	O
smaller	O
code	O
,	O
analogous	O
to	O
the	O
x32	B-Application
ABI	I-Application
.	O
</s>
<s>
Both	O
run	O
under	O
the	O
64-bit	B-Device
mode	O
of	O
the	O
CPU	O
.	O
</s>
<s>
The	O
N32	O
and	O
N64	B-Operating_System
ABIs	O
pass	O
the	O
first	O
eight	O
arguments	O
to	O
a	O
function	O
in	O
the	O
registers	O
-	O
;	O
subsequent	O
arguments	O
are	O
passed	O
on	O
the	O
stack	O
.	O
</s>
<s>
The	O
return	B-Language
value	I-Language
(	O
or	O
a	O
pointer	O
to	O
it	O
)	O
is	O
stored	O
in	O
the	O
registers	O
;	O
a	O
second	O
return	B-Language
value	I-Language
may	O
be	O
stored	O
in	O
.	O
</s>
<s>
In	O
both	O
the	O
N32	O
and	O
N64	B-Operating_System
ABIs	O
all	O
registers	O
are	O
considered	O
to	O
be	O
64-bits	B-Device
wide	O
.	O
</s>
<s>
A	O
few	O
attempts	O
have	O
been	O
made	O
to	O
replace	O
O32	O
with	O
a	O
32-bit	O
ABI	B-Operating_System
that	O
resembles	O
N32	O
more	O
.	O
</s>
<s>
EABI	O
inspired	O
MIPS	O
Technologies	O
to	O
propose	O
a	O
more	O
radical	O
"	O
NUBI	O
"	O
ABI	B-Operating_System
additionally	O
reuse	O
argument	O
registers	O
for	O
the	O
return	B-Language
value	I-Language
.	O
</s>
<s>
MIPS	O
EABI	O
is	O
supported	O
by	O
GCC	B-Application
but	O
not	O
LLVM	O
,	O
and	O
neither	O
supports	O
NUBI	O
.	O
</s>
<s>
For	O
all	O
of	O
O32	O
and	O
N32/N64	O
,	O
the	O
return	B-Language
address	I-Language
is	O
stored	O
in	O
a	O
register	O
.	O
</s>
<s>
The	O
function	O
prologue	O
of	O
a	O
(	O
non-leaf	O
)	O
MIPS	O
subroutine	O
pushes	O
the	O
return	B-Language
address	I-Language
(	O
in	O
)	O
to	O
the	O
stack	O
.	O
</s>
<s>
On	O
both	O
O32	O
and	O
N32/N64	O
the	O
stack	O
grows	O
downwards	O
,	O
but	O
the	O
N32/N64	O
ABIs	O
require	O
64-bit	B-Device
alignment	O
for	O
all	O
stack	O
entries	O
.	O
</s>
<s>
The	O
frame	O
pointer	O
(	O
)	O
is	O
optional	O
and	O
in	O
practice	O
rarely	O
used	O
except	O
when	O
the	O
stack	B-General_Concept
allocation	I-General_Concept
in	O
a	O
function	O
is	O
determined	O
at	O
runtime	O
,	O
for	O
example	O
,	O
by	O
calling	O
alloca( )	O
.	O
</s>
<s>
For	O
N32	O
and	O
N64	B-Operating_System
,	O
the	O
return	B-Language
address	I-Language
is	O
typically	O
stored	O
8	O
bytes	O
before	O
the	O
stack	B-General_Concept
pointer	I-General_Concept
although	O
this	O
may	O
be	O
optional	O
.	O
</s>
<s>
For	O
the	O
N32	O
and	O
N64	B-Operating_System
ABIs	O
,	O
a	O
function	O
must	O
preserve	O
the	O
-	O
registers	O
,	O
the	O
global	O
pointer	O
(	O
or	O
)	O
,	O
the	O
stack	B-General_Concept
pointer	I-General_Concept
(	O
or	O
)	O
and	O
the	O
frame	O
pointer	O
(	O
)	O
.	O
</s>
<s>
The	O
O32	O
ABI	B-Operating_System
is	O
the	O
same	O
except	O
the	O
calling	O
function	O
is	O
required	O
to	O
save	O
the	O
register	O
instead	O
of	O
the	O
called	O
function	O
.	O
</s>
<s>
+	O
Registers	O
for	O
N32	O
and	O
N64	B-Operating_System
calling	O
conventions	O
Name	O
Number	O
Use	O
Callee	O
must	O
preserve	O
?	O
</s>
<s>
For	O
example	O
,	O
$	O
s-registers	O
must	O
be	O
saved	O
to	O
the	O
stack	O
by	O
a	O
procedure	O
that	O
needs	O
to	O
use	O
them	O
,	O
and	O
and	O
are	O
always	O
incremented	O
by	O
constants	O
,	O
and	O
decremented	O
back	O
after	O
the	O
procedure	O
is	O
done	O
with	O
them	O
(	O
and	O
the	O
memory	B-General_Concept
they	O
point	O
to	O
)	O
.	O
</s>
<s>
The	O
userspace	O
calling	O
convention	O
of	O
position-independent	O
code	O
on	O
Linux	B-Application
additionally	O
requires	O
that	O
when	O
a	O
function	O
is	O
called	O
the	O
register	O
must	O
contain	O
the	O
address	O
of	O
that	O
function	O
.	O
</s>
<s>
This	O
convention	O
dates	O
back	O
to	O
the	O
System	B-Operating_System
V	I-Operating_System
ABI	B-Operating_System
supplement	O
for	O
MIPS	O
.	O
</s>
<s>
MIPS	B-General_Concept
processors	I-General_Concept
are	O
used	O
in	O
embedded	B-Architecture
systems	I-Architecture
such	O
as	O
residential	B-Application
gateways	I-Application
and	O
routers	B-Protocol
.	O
</s>
<s>
During	O
the	O
1980s	O
and	O
1990s	O
,	O
MIPS	B-General_Concept
processors	I-General_Concept
for	O
personal	B-Device
,	O
workstation	B-Device
,	O
and	O
server	B-Application
computers	I-Application
were	O
used	O
by	O
many	O
companies	O
such	O
as	O
Digital	O
Equipment	O
Corporation	O
,	O
MIPS	O
Computer	O
Systems	O
,	O
NEC	O
,	O
Pyramid	O
Technology	O
,	O
SiCortex	B-Operating_System
,	O
Siemens	O
Nixdorf	O
,	O
Silicon	O
Graphics	O
,	O
and	O
Tandem	O
Computers	O
.	O
</s>
<s>
Historically	O
,	O
video	B-Device
game	I-Device
consoles	I-Device
such	O
as	O
the	O
Nintendo	B-Operating_System
64	I-Operating_System
,	O
Sony	B-Device
PlayStation	I-Device
,	O
PlayStation	B-Device
2	I-Device
,	O
and	O
PlayStation	B-Operating_System
Portable	I-Operating_System
used	O
MIPS	B-General_Concept
processors	I-General_Concept
.	O
</s>
<s>
MIPS	B-General_Concept
processors	I-General_Concept
also	O
used	O
to	O
be	O
popular	O
in	O
supercomputers	B-Architecture
during	O
the	O
1990s	O
,	O
but	O
all	O
such	O
systems	O
have	O
dropped	O
off	O
the	O
TOP500	B-Operating_System
list	O
.	O
</s>
<s>
These	O
uses	O
were	O
complemented	O
by	O
embedded	O
applications	O
at	O
first	O
,	O
but	O
during	O
the	O
1990s	O
,	O
MIPS	O
became	O
a	O
major	O
presence	O
in	O
the	O
embedded	B-Architecture
processor	I-Architecture
market	O
,	O
and	O
by	O
the	O
2000s	O
,	O
most	O
MIPS	B-General_Concept
processors	I-General_Concept
were	O
for	O
these	O
applications	O
.	O
</s>
<s>
In	O
the	O
mid	O
-	O
to	O
late-1990s	O
,	O
it	O
was	O
estimated	O
that	O
one	O
in	O
three	O
RISC	B-Architecture
microprocessors	O
produced	O
was	O
a	O
MIPS	B-General_Concept
processor	I-General_Concept
.	O
</s>
<s>
By	O
the	O
late	O
2010s	O
,	O
MIPS	O
machines	O
were	O
still	O
commonly	O
used	O
in	O
embedded	O
markets	O
,	O
including	O
automotive	O
,	O
wireless	O
router	B-Protocol
,	O
LTE	O
modems	O
(	O
mainly	O
via	O
MediaTek	B-Architecture
)	O
,	O
and	O
microcontrollers	O
(	O
for	O
example	O
the	O
Microchip	O
Technology	O
PIC32M	O
)	O
.	O
</s>
<s>
They	O
have	O
mostly	O
faded	O
out	O
of	O
the	O
personal	B-Device
,	O
server	B-Application
,	O
and	O
application	O
space	O
.	O
</s>
<s>
Open	O
Virtual	O
Platforms	O
(	O
OVP	O
)	O
includes	O
the	O
freely	O
available	O
for	O
non-commercial	O
use	O
simulator	O
OVPsim	B-Application
,	O
a	O
library	O
of	O
models	O
of	O
processors	O
,	O
peripherals	O
and	O
platforms	O
,	O
and	O
APIs	O
which	O
enable	O
users	O
to	O
develop	O
their	O
own	O
models	O
.	O
</s>
<s>
The	O
models	O
in	O
the	O
library	O
are	O
open	O
source	O
,	O
written	O
in	O
C	O
,	O
and	O
include	O
the	O
MIPS	O
4K	O
,	O
24K	O
,	O
34K	O
,	O
74K	O
,	O
1004K	O
,	O
1074K	O
,	O
M14K	O
,	O
microAptiv	O
,	O
interAptiv	O
,	O
proAptiv	O
32-bit	O
cores	O
and	O
the	O
MIPS	O
64-bit	B-Device
5K	O
range	O
of	O
cores	O
.	O
</s>
<s>
Sample	O
MIPS-based	O
platforms	O
include	O
both	O
bare	O
metal	O
environments	O
and	O
platforms	O
for	O
booting	O
unmodified	O
Linux	B-Application
binary	O
images	O
.	O
</s>
<s>
OVPsim	B-Application
is	O
developed	O
and	O
maintained	O
by	O
Imperas	O
and	O
is	O
very	O
fast	O
(	O
hundreds	O
of	O
million	O
of	O
instructions	O
per	O
second	O
)	O
,	O
and	O
built	O
to	O
handle	O
multicore	O
homogeneous	O
and	O
heterogeneous	O
architectures	O
and	O
systems	O
.	O
</s>
<s>
There	O
is	O
a	O
freely	O
available	O
MIPS32	O
simulator	O
(	O
earlier	O
versions	O
simulated	O
only	O
the	O
R2000/R3000	O
)	O
called	O
SPIM	B-Application
for	O
use	O
in	O
education	O
.	O
</s>
<s>
It	O
supports	O
a	O
wide	O
subset	O
of	O
the	O
MIPS64	O
ISA	O
and	O
allows	O
the	O
user	O
to	O
graphically	O
see	O
what	O
happens	O
in	O
the	O
pipeline	B-General_Concept
when	O
an	O
assembly	O
program	O
is	O
run	O
by	O
the	O
CPU	O
.	O
</s>
<s>
QtMips	O
provides	O
simple	O
5-stages	O
pipeline	B-General_Concept
visualization	O
as	O
well	O
as	O
cache	O
principle	O
visualization	O
for	O
basic	O
computer	B-General_Concept
architectures	I-General_Concept
courses	O
.	O
</s>
<s>
Windows	O
,	O
Linux	B-Application
,	O
macOS	B-Application
and	O
online	O
version	O
is	O
available	O
.	O
</s>
<s>
More	O
advanced	O
free	O
emulators	O
are	O
available	O
from	O
the	O
GXemul	O
(	O
formerly	O
known	O
as	O
the	O
mips64emul	O
project	O
)	O
and	O
QEMU	B-Application
projects	O
.	O
</s>
<s>
Commercial	O
simulators	O
are	O
available	O
especially	O
for	O
the	O
embedded	O
use	O
of	O
MIPS	B-General_Concept
processors	I-General_Concept
,	O
for	O
example	O
Wind	O
River	O
Simics	B-Application
(	O
MIPS	O
4Kc	O
and	O
5Kc	O
,	O
PMC	O
RM9000	O
,	O
QED	O
RM7000	O
,	O
Broadcom/Netlogic	O
ec4400	O
,	O
Cavium	O
Octeon	O
I	O
)	O
,	O
Imperas	O
(	O
all	O
MIPS32	O
and	O
MIPS64	O
cores	O
)	O
,	O
VaST	O
Systems	O
(	O
R3000	O
,	O
R4000	B-General_Concept
)	O
,	O
and	O
CoWare	O
(	O
the	O
MIPS4KE	O
,	O
MIPS24K	O
,	O
MIPS25Kf	O
and	O
MIPS34K	O
)	O
.	O
</s>
<s>
The	O
Creator	O
simulator	O
is	O
portable	O
and	O
allows	O
the	O
user	O
to	O
learn	O
various	O
assembly	O
languages	O
of	O
different	O
processors	O
(	O
Creator	O
has	O
examples	O
with	O
an	O
implementation	O
of	O
MIPS32	O
and	O
RISC-V	B-Device
instructions	O
)	O
.	O
</s>
