<s>
Multi-Channel	O
DRAM	O
or	O
MCDRAM	B-Operating_System
(	O
pronounced	O
em	O
cee	O
dee	O
ram	O
)	O
is	O
a	O
3D-stacked	B-Architecture
DRAM	O
that	O
is	O
used	O
in	O
the	O
Intel	B-General_Concept
Xeon	I-General_Concept
Phi	I-General_Concept
processor	O
codenamed	O
Knights	O
Landing	O
.	O
</s>
<s>
It	O
is	O
a	O
version	O
of	O
Hybrid	B-General_Concept
Memory	I-General_Concept
Cube	I-General_Concept
developed	O
in	O
partnership	O
with	O
Micron	O
Technology	O
,	O
and	O
a	O
competitor	O
to	O
High	O
Bandwidth	O
Memory	O
.	O
</s>
<s>
The	O
many	O
cores	O
in	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
processors	O
,	O
along	O
with	O
their	O
associated	O
vector	O
processing	O
units	O
,	O
enable	O
them	O
to	O
consume	O
many	O
more	O
gigabytes	O
per	O
second	O
than	O
traditional	O
DRAM	O
DIMMs	O
can	O
supply	O
.	O
</s>
<s>
The	O
"	O
Multi-channel	O
"	O
part	O
of	O
the	O
MCDRAM	B-Operating_System
full	O
name	O
reflects	O
the	O
cores	O
having	O
many	O
more	O
channels	O
available	O
to	O
access	O
the	O
MCDRAM	B-Operating_System
than	O
processors	O
have	O
to	O
access	O
their	O
attached	O
DIMMs	O
.	O
</s>
<s>
This	O
high	O
channel	O
count	O
leads	O
to	O
MCDRAM	B-Operating_System
's	O
high	O
bandwidth	O
,	O
up	O
to	O
400+	O
GB/s	O
,	O
although	O
the	O
latencies	O
are	O
similar	O
to	O
a	O
DIMM	O
access	O
.	O
</s>
<s>
The	O
application	O
can	O
request	O
pages	O
of	O
virtual	B-Architecture
memory	I-Architecture
to	O
be	O
assigned	O
to	O
either	O
the	O
distant	O
DDR	O
directly	O
,	O
to	O
the	O
portion	O
of	O
DDR	O
that	O
is	O
cached	O
by	O
the	O
MCDRAM	B-Operating_System
,	O
or	O
to	O
the	O
portion	O
of	O
the	O
MCDRAM	B-Operating_System
that	O
is	O
not	O
being	O
used	O
as	O
cache	O
.	O
</s>
