<s>
MAJC	B-General_Concept
(	O
Microprocessor	B-Architecture
Architecture	O
for	O
Java	B-Language
Computing	O
)	O
was	O
a	O
Sun	O
Microsystems	O
multi-core	O
,	O
multithreaded	O
,	O
very	B-General_Concept
long	I-General_Concept
instruction	I-General_Concept
word	I-General_Concept
(	O
VLIW	B-General_Concept
)	O
microprocessor	B-Architecture
design	O
from	O
the	O
mid-to-late	O
1990s	O
.	O
</s>
<s>
Originally	O
called	O
the	O
UltraJava	B-General_Concept
processor	O
,	O
the	O
MAJC	B-General_Concept
processor	O
was	O
targeted	O
at	O
running	O
Java	B-Language
programs	O
,	O
whose	O
"	O
late	O
compiling	O
"	O
allowed	O
Sun	O
to	O
make	O
several	O
favourable	O
design	O
decisions	O
.	O
</s>
<s>
Lessons	O
learned	O
regarding	O
multi-threads	O
on	O
a	O
multi-core	O
processor	O
provided	O
a	O
basis	O
for	O
later	O
OpenSPARC	B-Device
implementations	O
such	O
as	O
the	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
.	O
</s>
<s>
Like	O
other	O
VLIW	B-General_Concept
designs	O
,	O
notably	O
Intel	O
's	O
IA-64	B-General_Concept
(	O
Itanium	O
)	O
,	O
MAJC	B-General_Concept
attempted	O
to	O
improve	O
performance	O
by	O
moving	O
several	O
expensive	O
operations	O
out	O
of	O
the	O
processor	O
and	O
into	O
the	O
related	O
compilers	O
.	O
</s>
<s>
In	O
general	O
,	O
VLIW	B-General_Concept
designs	O
attempt	O
to	O
eliminate	O
the	O
instruction	O
scheduler	O
,	O
which	O
often	O
represents	O
a	O
relatively	O
large	O
amount	O
of	O
the	O
overall	O
processor	O
's	O
transistor	O
budget	O
.	O
</s>
<s>
With	O
this	O
portion	O
of	O
the	O
CPU	O
removed	O
to	O
software	O
,	O
those	O
transistors	O
can	O
be	O
used	O
for	O
other	O
purposes	O
,	O
often	O
to	O
add	O
additional	O
functional	B-General_Concept
units	I-General_Concept
to	O
process	O
more	O
instructions	O
at	O
once	O
,	O
or	O
to	O
increase	O
the	O
amount	O
of	O
cache	B-General_Concept
memory	I-General_Concept
to	O
reduce	O
the	O
amount	O
of	O
time	O
spent	O
waiting	O
for	O
data	O
to	O
arrive	O
from	O
the	O
much	O
slower	O
main	O
memory	O
.	O
</s>
<s>
Although	O
MAJC	B-General_Concept
shared	O
these	O
general	O
concepts	O
,	O
it	O
was	O
unlike	O
other	O
VLIW	B-General_Concept
designs	O
,	O
and	O
processors	O
in	O
general	O
,	O
in	O
a	O
number	O
of	O
specific	O
details	O
.	O
</s>
<s>
Most	O
processors	O
include	O
a	O
number	O
of	O
separate	O
"	O
subprocessors	O
"	O
known	O
as	O
functional	B-General_Concept
units	I-General_Concept
that	O
are	O
tuned	O
to	O
operating	O
on	O
a	O
particular	O
type	O
of	O
data	O
.	O
</s>
<s>
For	O
instance	O
,	O
a	O
modern	O
CPU	O
typically	O
has	O
two	O
or	O
three	O
functional	B-General_Concept
units	I-General_Concept
dedicated	O
to	O
processing	O
integer	O
data	O
and	O
logic	O
instructions	O
,	O
known	O
as	O
ALUs	O
,	O
while	O
other	O
units	O
handle	O
floating-point	B-Algorithm
numbers	I-Algorithm
,	O
the	O
FPUs	O
,	O
or	O
multimedia	O
data	O
,	O
SIMD	B-Device
.	O
</s>
<s>
MAJC	B-General_Concept
instead	O
used	O
a	O
single	O
multi-purpose	O
functional	B-General_Concept
unit	I-General_Concept
which	O
could	O
process	O
any	O
sort	O
of	O
data	O
.	O
</s>
<s>
But	O
on	O
the	O
other	O
hand	O
,	O
these	O
general-purpose	O
units	O
also	O
meant	O
that	O
you	O
did	O
not	O
end	O
up	O
with	O
large	O
portions	O
of	O
the	O
CPU	O
being	O
unused	O
because	O
the	O
program	O
just	O
happened	O
to	O
be	O
doing	O
many	O
(	O
for	O
example	O
)	O
floating	B-Algorithm
point	I-Algorithm
calculations	O
at	O
that	O
particular	O
point	O
in	O
time	O
.	O
</s>
<s>
Another	O
difference	O
is	O
that	O
MAJC	B-General_Concept
allowed	O
for	O
variable-length	O
"	O
instruction	B-Language
packets	I-Language
"	O
,	O
which	O
under	O
VLIW	B-General_Concept
contain	O
a	O
number	O
of	O
instructions	O
that	O
the	O
compiler	O
has	O
determined	O
can	O
be	O
run	O
at	O
the	O
same	O
time	O
.	O
</s>
<s>
Most	O
VLIW	B-General_Concept
architectures	O
use	O
fixed-length	O
packets	O
and	O
when	O
they	O
cannot	O
find	O
an	O
instruction	O
to	O
run	O
they	O
instead	O
fill	O
it	O
with	O
a	O
NOP	O
,	O
which	O
simply	O
takes	O
up	O
space	O
.	O
</s>
<s>
Although	O
variable-length	O
instruction	B-Language
packets	I-Language
added	O
some	O
complexity	O
to	O
the	O
CPU	O
,	O
it	O
reduced	O
code	O
size	O
and	O
thus	O
the	O
number	O
of	O
expensive	O
cache	B-General_Concept
misses	O
by	O
increasing	O
the	O
amount	O
of	O
code	O
in	O
the	O
cache	B-General_Concept
at	O
any	O
one	O
time	O
.	O
</s>
<s>
The	O
primary	O
difference	O
was	O
the	O
way	O
that	O
the	O
MAJC	B-General_Concept
design	O
required	O
the	O
compiler	O
to	O
avoid	O
interlocks	O
,	O
pauses	O
in	O
execution	O
while	O
the	O
results	O
of	O
one	O
instruction	O
need	O
to	O
be	O
processed	O
for	O
the	O
next	O
to	O
be	O
able	O
to	O
run	O
.	O
</s>
<s>
For	O
instance	O
,	O
if	O
a	O
particular	O
implementation	O
took	O
three	O
cycles	O
to	O
complete	O
a	O
floating-point	B-Algorithm
multiplication	O
,	O
MAJC	B-General_Concept
compilers	O
would	O
attempt	O
to	O
schedule	O
in	O
other	O
instructions	O
that	O
took	O
three	O
cycles	O
to	O
complete	O
and	O
were	O
not	O
currently	O
stalled	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
compiler	O
was	O
not	O
tied	O
to	O
MAJC	B-General_Concept
as	O
a	O
whole	O
,	O
but	O
a	O
particular	O
implementation	O
of	O
MAJC	B-General_Concept
,	O
each	O
individual	O
CPU	O
based	O
on	O
the	O
MAJC	B-General_Concept
design	O
.	O
</s>
<s>
This	O
would	O
normally	O
be	O
a	O
serious	O
logistical	O
problem	O
;	O
consider	O
the	O
number	O
of	O
different	O
variations	O
of	O
the	O
Intel	B-Device
IA-32	I-Device
design	O
for	O
instance	O
,	O
each	O
one	O
would	O
need	O
its	O
own	O
dedicated	O
compiler	O
and	O
the	O
developer	O
would	O
have	O
to	O
produce	O
a	O
different	O
binary	O
for	O
every	O
one	O
.	O
</s>
<s>
However	O
it	O
is	O
precisely	O
this	O
concept	O
that	O
drives	O
the	O
Java	B-Language
marketthere	O
is	O
indeed	O
a	O
different	O
compiler	O
for	O
each	O
ISA	B-General_Concept
,	O
and	O
it	O
is	O
installed	O
on	O
the	O
client	O
's	O
machine	O
instead	O
of	O
the	O
developer	O
's	O
.	O
</s>
<s>
In	O
real-world	O
use	O
,	O
processors	O
that	O
attempt	O
to	O
do	O
this	O
scheduling	O
at	O
runtime	O
encounter	O
numerous	O
events	O
when	O
the	O
data	O
needed	O
is	O
outside	O
the	O
cache	B-General_Concept
,	O
and	O
there	O
is	O
no	O
other	O
instruction	O
in	O
the	O
program	O
that	O
is	O
n't	O
also	O
dependent	O
on	O
such	O
data	O
.	O
</s>
<s>
The	O
VLIW	B-General_Concept
approach	O
does	O
not	O
help	O
much	O
in	O
this	O
regard	O
;	O
although	O
the	O
compiler	O
might	O
be	O
able	O
to	O
spend	O
more	O
time	O
looking	O
for	O
instructions	O
to	O
run	O
,	O
that	O
does	O
n't	O
mean	O
that	O
it	O
can	O
actually	O
find	O
one	O
.	O
</s>
<s>
MAJC	B-General_Concept
attempted	O
to	O
address	O
this	O
problem	O
through	O
the	O
ability	O
to	O
execute	O
code	O
from	O
other	O
threads	O
if	O
the	O
current	O
thread	O
stalled	O
on	O
memory	O
.	O
</s>
<s>
Switching	O
threads	O
is	O
normally	O
a	O
very	O
expensive	O
process	O
known	O
as	O
a	O
context	B-Operating_System
switch	I-Operating_System
,	O
and	O
on	O
a	O
normal	O
processor	O
the	O
switch	O
would	O
overwhelm	O
any	O
savings	O
and	O
generally	O
slow	O
the	O
machine	O
down	O
.	O
</s>
<s>
On	O
MAJC	B-General_Concept
,	O
the	O
system	O
could	O
hold	O
the	O
state	O
for	O
up	O
to	O
four	O
threads	O
in	O
memory	O
at	O
the	O
same	O
time	O
,	O
reducing	O
the	O
context	B-Operating_System
switch	I-Operating_System
to	O
a	O
few	O
instructions	O
in	O
length	O
.	O
</s>
<s>
This	O
feature	O
has	O
since	O
appeared	O
on	O
other	O
processors	O
;	O
Intel	O
refers	O
to	O
it	O
as	O
HyperThreading	B-Operating_System
.	O
</s>
<s>
MAJC	B-General_Concept
took	O
this	O
idea	O
one	O
step	O
further	O
,	O
and	O
tried	O
to	O
prefetch	O
data	O
and	O
instructions	O
needed	O
for	O
threads	O
while	O
they	O
were	O
stalled	O
.	O
</s>
<s>
Most	O
processors	O
include	O
similar	O
functionality	O
for	O
parts	O
of	O
an	O
instruction	O
stream	O
,	O
known	O
as	O
speculative	B-General_Concept
execution	I-General_Concept
,	O
where	O
the	O
processor	O
runs	O
both	O
of	O
the	O
possible	O
outcomes	O
of	O
a	O
branch	O
while	O
waiting	O
for	O
the	O
deciding	O
variable	O
to	O
calculate	O
.	O
</s>
<s>
MAJC	B-General_Concept
instead	O
continued	O
to	O
run	O
the	O
thread	O
as	O
if	O
it	O
were	O
not	O
stalled	O
,	O
using	O
this	O
execution	O
to	O
find	O
and	O
then	O
load	O
any	O
data	O
or	O
instructions	O
that	O
would	O
soon	O
be	O
needed	O
when	O
the	O
thread	O
stopped	O
stalling	O
.	O
</s>
<s>
Sun	O
referred	O
to	O
this	O
as	O
Space-Time	O
Computing	O
(	O
STC	O
)	O
,	O
and	O
it	O
is	O
a	O
speculative	B-Operating_System
multithreading	I-Operating_System
design	O
.	O
</s>
<s>
In	O
seems	O
that	O
in	O
a	O
general	O
sense	O
the	O
MAJC	B-General_Concept
design	O
attempted	O
to	O
avoid	O
stalls	O
by	O
running	O
across	O
threads	O
(	O
and	O
programs	O
)	O
as	O
opposed	O
to	O
looking	O
for	O
parallelism	O
in	O
a	O
single	O
thread	O
.	O
</s>
<s>
VLIW	B-General_Concept
is	O
generally	O
expected	O
to	O
be	O
somewhat	O
worse	O
in	O
terms	O
of	O
stalls	O
because	O
it	O
is	O
difficult	O
to	O
understand	O
runtime	O
behavior	O
at	O
compile-time	O
,	O
making	O
the	O
MAJC	B-General_Concept
approach	O
in	O
dealing	O
with	O
this	O
problem	O
particularly	O
interesting	O
.	O
</s>
<s>
Sun	O
built	O
a	O
single	O
model	O
of	O
the	O
MAJC	B-General_Concept
,	O
the	O
two-core	O
MAJC	B-General_Concept
5200	O
,	O
which	O
was	O
the	O
heart	O
of	O
Sun	O
's	O
XVR-1000	O
and	O
XVR-4000	O
workstation	B-Device
graphics	O
boards	O
.	O
</s>
<s>
However	O
many	O
of	O
the	O
multicore	O
and	O
multithreading	O
design	O
ideas	O
,	O
notably	O
in	O
terms	O
of	O
using	O
multiple	O
threads	O
to	O
reduce	O
stalling	O
delays	O
,	O
worked	O
their	O
way	O
into	O
the	O
Sun	B-Architecture
SPARC	I-Architecture
processor	O
line	O
,	O
as	O
well	O
as	O
designs	O
from	O
other	O
companies	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
MAJC	B-General_Concept
idea	O
of	O
designing	O
the	O
processor	O
to	O
run	O
as	O
many	O
threads	O
as	O
possible	O
,	O
as	O
opposed	O
to	O
instructions	O
,	O
appears	O
to	O
be	O
the	O
basis	O
of	O
the	O
later	O
UltraSPARC	B-General_Concept
T1	I-General_Concept
(	O
code-named	O
Niagara	B-General_Concept
)	O
design	O
.	O
</s>
