<s>
Lockstep	B-General_Concept
systems	O
are	O
fault-tolerant	B-General_Concept
computer	I-General_Concept
systems	I-General_Concept
that	O
run	O
the	O
same	O
set	O
of	O
operations	O
at	O
the	O
same	O
time	O
in	O
parallel	B-Operating_System
.	O
</s>
<s>
The	O
redundancy	O
(	O
duplication	O
)	O
allows	O
error	O
detection	O
and	O
error	O
correction	O
:	O
the	O
output	O
from	O
lockstep	B-General_Concept
operations	O
can	O
be	O
compared	O
to	O
determine	O
if	O
there	O
has	O
been	O
a	O
fault	O
if	O
there	O
are	O
at	O
least	O
two	O
systems	O
(	O
dual	B-Error_Name
modular	I-Error_Name
redundancy	I-Error_Name
)	O
,	O
and	O
the	O
error	O
can	O
be	O
automatically	O
corrected	O
if	O
there	O
are	O
at	O
least	O
three	O
systems	O
(	O
triple	B-Error_Name
modular	I-Error_Name
redundancy	I-Error_Name
)	O
,	O
via	O
majority	O
vote	O
.	O
</s>
<s>
The	O
term	O
"	O
lockstep	B-General_Concept
"	O
originates	O
from	O
army	O
usage	O
,	O
where	O
it	O
refers	O
to	O
synchronized	O
walking	O
,	O
in	O
which	O
marchers	O
walk	O
as	O
closely	O
together	O
as	O
physically	O
practical	O
.	O
</s>
<s>
To	O
run	O
in	O
lockstep	B-General_Concept
,	O
each	O
system	O
is	O
set	O
up	O
to	O
progress	O
from	O
one	O
well-defined	O
state	O
to	O
the	O
next	O
well-defined	O
state	O
.	O
</s>
<s>
Some	O
vendors	O
,	O
including	O
Intel	O
,	O
use	O
the	O
term	O
lockstep	B-General_Concept
memory	O
to	O
describe	O
a	O
multi-channel	B-Architecture
memory	O
layout	O
in	O
which	O
cache	B-General_Concept
lines	I-General_Concept
are	O
distributed	O
between	O
two	O
memory	O
channels	O
,	O
so	O
one	O
half	O
of	O
the	O
cache	B-General_Concept
line	I-General_Concept
is	O
stored	O
in	O
a	O
DIMM	B-General_Concept
on	O
the	O
first	O
channel	O
,	O
while	O
the	O
second	O
half	O
goes	O
to	O
a	O
DIMM	B-General_Concept
on	O
the	O
second	O
channel	O
.	O
</s>
<s>
By	O
combining	O
the	O
single	O
error	O
correction	O
and	O
double	O
error	O
detection	O
(	O
SECDED	O
)	O
capabilities	O
of	O
two	O
ECC-enabled	O
DIMMs	B-General_Concept
in	O
a	O
lockstep	B-General_Concept
layout	O
,	O
their	O
single-device	O
data	O
correction	O
(	O
SDDC	O
)	O
nature	O
can	O
be	O
extended	O
into	O
double-device	O
data	O
correction	O
(	O
DDDC	O
)	O
,	O
providing	O
protection	O
against	O
the	O
failure	O
of	O
any	O
single	O
memory	O
chip	O
.	O
</s>
<s>
Downsides	O
of	O
the	O
Intel	O
's	O
lockstep	B-General_Concept
memory	O
layout	O
are	O
the	O
reduction	O
of	O
effectively	O
usable	O
amount	O
of	O
RAM	O
(	O
in	O
case	O
of	O
a	O
triple-channel	B-Architecture
memory	O
layout	O
,	O
maximum	O
amount	O
of	O
memory	O
reduces	O
to	O
one	O
third	O
of	O
the	O
physically	O
available	O
maximum	O
)	O
,	O
and	O
reduced	O
performance	O
of	O
the	O
memory	O
subsystem	O
.	O
</s>
<s>
For	O
this	O
reason	O
,	O
it	O
is	O
common	O
practice	O
to	O
run	O
DMR	O
systems	O
as	O
"	O
master/slave	O
"	O
configurations	O
with	O
the	O
slave	O
as	O
a	O
"	O
hot-standby	O
"	O
to	O
the	O
master	O
,	O
rather	O
than	O
in	O
lockstep	B-General_Concept
.	O
</s>
<s>
While	O
either	O
the	O
lockstep	B-General_Concept
or	O
the	O
DMR	O
approach	O
(	O
when	O
combined	O
with	O
some	O
means	O
of	O
detecting	O
errors	O
in	O
the	O
master	O
)	O
can	O
provide	O
redundancy	O
against	O
hardware	O
failure	O
in	O
the	O
master	O
,	O
they	O
do	O
not	O
protect	O
against	O
software	O
error	O
.	O
</s>
