<s>
In	O
computer	B-General_Concept
architecture	I-General_Concept
,	O
a	O
local	B-Architecture
bus	I-Architecture
is	O
a	O
computer	B-General_Concept
bus	I-General_Concept
that	O
connects	O
directly	O
,	O
or	O
almost	O
directly	O
,	O
from	O
the	O
central	B-General_Concept
processing	I-General_Concept
unit	I-General_Concept
(	O
CPU	O
)	O
to	O
one	O
or	O
more	O
slots	O
on	O
the	O
expansion	B-Device
bus	I-Device
.	O
</s>
<s>
The	O
significance	O
of	O
direct	O
connection	O
to	O
the	O
CPU	O
is	O
avoiding	O
the	O
bottleneck	O
created	O
by	O
the	O
expansion	B-Device
bus	I-Device
,	O
thus	O
providing	O
fast	O
throughput	O
.	O
</s>
<s>
VESA	O
Local	B-Architecture
Bus	I-Architecture
and	O
Processor	B-Device
Direct	I-Device
Slot	I-Device
were	O
examples	O
of	O
a	O
local	B-Architecture
bus	I-Architecture
design	O
.	O
</s>
<s>
Although	O
VL-Bus	O
was	O
later	O
succeeded	O
by	O
AGP	B-Architecture
,	O
it	O
is	O
not	O
correct	O
to	O
categorize	O
AGP	B-Architecture
as	O
a	O
local	B-Architecture
bus	I-Architecture
.	O
</s>
<s>
Whereas	O
VL-Bus	O
operated	O
on	O
the	O
CPU	O
's	O
memory	O
bus	O
at	O
the	O
CPU	O
's	O
clock	O
speed	O
,	O
an	O
AGP	B-Architecture
peripheral	O
runs	O
at	O
specified	O
clock	O
speeds	O
that	O
run	O
independently	O
of	O
the	O
CPU	O
clock	O
(	O
usually	O
using	O
a	O
divider	O
of	O
the	O
CPU	O
clock	O
)	O
.	O
</s>
