<s>
Instructions	O
that	O
have	O
at	O
some	O
point	O
been	O
present	O
as	O
documented	O
instructions	O
in	O
one	O
or	O
more	O
x86	B-Operating_System
processors	O
,	O
but	O
where	O
the	O
processor	O
series	O
containing	O
the	O
instructions	O
are	O
discontinued	O
or	O
superseded	O
,	O
with	O
no	O
known	O
plans	O
to	O
reintroduce	O
the	O
instructions	O
.	O
</s>
<s>
The	O
following	O
instructions	O
were	O
introduced	O
in	O
the	O
Intel	B-General_Concept
80386	I-General_Concept
,	O
but	O
later	O
discontinued	O
:	O
</s>
<s>
Description	O
Instruction	O
Opcode	O
Eventual	O
fate	O
Extract	O
Bit	O
String	O
Discontinued	O
from	O
revision	O
B1	O
of	O
the	O
80386	B-General_Concept
onwards	O
.	O
</s>
<s>
Insert	O
Bit	O
String	O
IBTS	O
r/m	O
,	O
r	O
0F	O
A7	O
/r	O
Move	O
from	O
test	B-General_Concept
register	I-General_Concept
0F	O
24	O
/r	O
Present	O
in	O
Intel	B-General_Concept
386	I-General_Concept
and	O
486	O
-	O
not	O
present	O
in	O
Intel	O
Pentium	O
or	O
any	O
later	O
Intel	O
CPUs	O
(	O
except	O
they	O
're	O
present	O
in	O
the	O
i486-derived	O
Quark	B-Device
X1000	I-Device
)	O
.	O
<	O
p>Present	O
in	O
all	O
Cyrix	O
CPUs	O
.	O
</s>
<s>
These	O
instructions	O
are	O
only	O
present	O
in	O
the	O
x86	B-Operating_System
operation	O
mode	O
of	O
early	O
Intel	B-General_Concept
Itanium	I-General_Concept
processors	O
with	O
hardware	O
support	O
for	O
x86	B-Operating_System
.	O
</s>
<s>
This	O
support	O
was	O
added	O
in	O
"	O
Merced	O
"	O
and	O
removed	O
in	O
"	O
Montecito	O
"	O
,	O
replaced	O
with	O
software	B-Device
emulation	I-Device
.	O
</s>
<s>
Instruction	O
Opcode	O
Meaning	O
JMPE	O
r/m16/32	O
0F	O
00	O
/6	O
Jump	O
To	O
Intel	B-General_Concept
Itanium	I-General_Concept
Instruction	O
Set.Intel	O
Itanium	O
Architecture	O
Software	O
Developer	O
's	O
Manual	O
,	O
volume	O
4	O
,	O
(	O
document	O
number	O
:	O
323208	O
,	O
revision	O
2.3	O
,	O
May	O
2010	O
)	O
.	O
</s>
<s>
These	O
instructions	O
were	O
introduced	O
in	O
6th	O
generation	O
Intel	O
Core	O
"	B-Architecture
Skylake	I-Architecture
"	I-Architecture
CPUs	O
.	O
</s>
<s>
The	O
last	O
CPU	O
generation	O
to	O
support	O
them	O
was	O
the	O
9th	O
generation	O
Core	O
"	O
Coffee	B-Device
Lake	I-Device
"	O
CPUs	O
.	O
</s>
<s>
The	O
Hardware	O
Lock	O
Elision	O
feature	O
of	O
Intel	B-Operating_System
TSX	I-Operating_System
is	O
marked	O
in	O
the	O
Intel	O
SDM	O
as	O
removed	O
from	O
2019	O
onwards	O
.	O
</s>
<s>
The	O
first	O
generation	O
Xeon	B-General_Concept
Phi	I-General_Concept
processors	O
,	O
codenamed	O
"	O
Knights	O
Corner	O
"	O
(	O
KNC	O
)	O
,	O
supported	O
a	O
large	O
number	O
of	O
instructions	O
that	O
are	O
not	O
seen	O
in	O
any	O
later	O
x86	B-Operating_System
processor	O
.	O
</s>
<s>
An	O
instruction	O
reference	O
is	O
available	O
-	O
the	O
instructions/opcodes	O
unique	O
to	O
KNC	O
are	O
the	O
ones	O
with	O
VEX	O
and	O
MVEX	O
prefixes	O
(	O
except	O
for	O
the	O
KMOV	O
,	O
KNOT	O
and	O
KORTEST	O
instructions	O
-	O
these	O
are	O
kept	O
with	O
the	O
same	O
opcodes	O
and	O
function	O
in	O
AVX-512	B-General_Concept
,	O
but	O
with	O
an	O
added	O
"	O
W	O
"	O
appended	O
to	O
their	O
instruction	O
names	O
)	O
.Most	O
of	O
these	O
KNC-unique	O
instructions	O
are	O
similar	O
but	O
not	O
identical	O
to	O
instructions	O
in	O
AVX-512	B-General_Concept
-	O
later	O
Xeon	B-General_Concept
Phi	I-General_Concept
processors	O
replaced	O
these	O
instructions	O
with	O
AVX-512	B-General_Concept
.	O
</s>
<s>
Some	O
of	O
the	O
AVX-512	B-General_Concept
instructions	O
in	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
"	O
Knights	O
Landing	O
"	O
and	O
later	O
models	O
belong	O
to	O
the	O
AVX-512	B-General_Concept
subsets	O
"	O
AVX512ER	O
"	O
,	O
"	O
AVX512_4FMAPS	O
"	O
,	O
"	O
AVX512PF	O
"	O
and	O
"	O
AVX512_4VNNIW	O
"	O
,	O
all	O
of	O
which	O
are	O
unique	O
to	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
series	O
of	O
processors	O
.	O
</s>
<s>
For	O
a	O
given	O
operation	O
,	O
all	O
the	O
scalar/packed	O
variants	O
belong	O
to	O
the	O
same	O
AVX-512	B-General_Concept
subset	O
.	O
</s>
<s>
A	O
handful	O
of	O
instructions	O
to	O
support	O
System	B-Architecture
Management	I-Architecture
Mode	I-Architecture
were	O
introduced	O
in	O
the	O
Am386SXLV	O
and	O
Am386DXLV	O
processors	O
.	O
</s>
<s>
The	O
SMM	O
functionality	O
of	O
these	O
processors	O
was	O
implemented	O
using	O
Intel	O
ICE	O
microcode	B-Device
without	O
a	O
valid	O
license	O
,	O
resulting	O
in	O
a	O
lawsuit	O
that	O
AMD	O
lost	O
in	O
1994	O
.	O
</s>
<s>
As	O
a	O
result	O
of	O
this	O
loss	O
,	O
the	O
ICE	O
microcode	B-Device
was	O
removed	O
from	O
all	O
later	O
AMD	O
CPUs	O
,	O
and	O
the	O
SMM	O
instructions	O
removed	O
with	O
it	O
.	O
</s>
<s>
These	O
SMM	O
instructions	O
were	O
also	O
present	O
on	O
the	O
IBM	B-Device
386SLC	I-Device
and	O
its	O
derivatives	O
(	O
albeit	O
with	O
the	O
LOADALL-like	O
SMM	O
return	O
opcode	O
0F	O
07	O
named	O
"	O
ICERET	O
"	O
)	O
.	O
</s>
<s>
AMD	O
K6-2	O
,	O
K6-III	O
,	O
and	O
all	O
processors	O
based	O
on	O
the	O
K7	B-Architecture
,	O
K8	B-Device
and	O
K10	O
microarchitectures	O
.	O
</s>
<s>
VIA	O
Cyrix	B-Device
III	I-Device
,	O
and	O
the	O
"	O
Samuel	O
"	O
and	O
"	O
Ezra	O
"	O
revisions	O
of	O
VIA	B-Device
C3	I-Device
.	O
</s>
<s>
National	O
Semiconductor	O
Geode	B-Device
GX2	O
;	O
AMD	B-Device
Geode	I-Device
GX	O
and	O
LX	O
.	O
</s>
<s>
SSE5	B-General_Concept
was	O
a	O
proposed	O
SSE	O
extension	O
by	O
AMD	O
.	O
</s>
<s>
AMD	O
chose	O
not	O
to	O
implement	O
SSE5	B-General_Concept
as	O
originally	O
proposed	O
,	O
however	O
,	O
derived	O
SSE	O
extensions	O
were	O
introduced	O
.	O
</s>
<s>
FMA4	B-General_Concept
was	O
realized	O
in	O
hardware	O
before	O
FMA3	B-General_Concept
.	O
</s>
<s>
These	O
instructions	O
are	O
specific	O
to	O
the	O
NEC	B-Device
V20/V30	I-Device
CPUs	O
and	O
their	O
successors	O
,	O
and	O
do	O
not	O
appear	O
in	O
any	O
non-NEC	O
CPUs	O
.	O
</s>
<s>
0F	O
FF	O
ib	O
BRKEM	O
imm8	O
Break	O
to	O
8080	B-General_Concept
emulation	O
mode	O
.	O
</s>
<s>
Jump	O
to	O
an	O
address	O
picked	O
from	O
the	O
Interrupt	O
Vector	O
Table	O
using	O
the	O
imm8	O
argument	O
,	O
similar	O
to	O
the	O
INT	O
instruction	O
,	O
but	O
start	O
executing	O
as	O
Intel	B-General_Concept
8080	I-General_Concept
code	O
rather	O
than	O
x86	B-Operating_System
code	O
.	O
</s>
<s>
These	O
registers	O
,	O
specific	O
to	O
V55	O
,	O
act	O
similar	O
to	O
regular	O
x86	B-Operating_System
real-mode	O
segment	O
registers	O
except	O
that	O
they	O
are	O
left-shifted	O
by	O
8	O
rather	O
than	O
4	O
,	O
enabling	O
access	O
to	O
16MB	O
of	O
memory	O
.	O
</s>
<s>
0F	O
9A	O
ALBIT	O
Dedicated	O
fax	O
instructions	O
V55PI	O
0F	O
9B	O
COLTRP	O
0F	O
93	O
MHENC	O
0F	O
97	O
MRENC	O
0F	O
78	O
SCHEOL	O
0F	O
79	O
GETBIT	O
0F	O
7C	O
MHDEC	O
0F	O
7D	O
MRDEC	O
0F	O
7A	O
CNVTRP	O
63	O
(	O
no	O
mnemonic	O
)	O
Designated	O
opcode	O
for	O
termination	O
of	O
the	O
x86	B-Operating_System
emulation	O
mode	O
on	O
the	O
NEC	O
V60.NEC	O
uPD70616	O
Programmer	O
's	O
Reference	O
Manual	O
(	O
november	O
1986	O
)	O
,	O
p.287	O
.	O
</s>
<s>
These	O
instructions	O
are	O
present	O
in	O
Cyrix	O
CPUs	O
as	O
well	O
as	O
NatSemi/AMD	O
Geode	O
CPUs	O
derived	O
from	O
Cyrix	O
microarchitectures	O
(	O
Geode	B-Device
GX	I-Device
and	O
LX	O
,	O
but	O
not	O
NX	O
)	O
.	O
</s>
<s>
The	O
first	O
8	O
bytes	O
are	O
the	O
descriptor	O
,	O
the	O
last	O
two	O
bytes	O
are	O
the	O
selector.Texas	O
Instruments	O
,	O
TI486	O
Microprocessor	O
Reference	O
Guide	O
,	O
1993	O
,	O
section	O
A.14	O
,	O
page	O
308	O
System	B-Architecture
Management	I-Architecture
Mode	I-Architecture
instructions	O
.	O
</s>
<s>
Present	O
on	O
all	O
Cyrix-derived	O
Geode	B-Device
CPUs	O
.	O
</s>
<s>
Uses	O
0F	O
7E	O
encoding	O
on	O
Cyrix	O
486	O
,	O
5x86	O
,	O
6x86	B-General_Concept
and	O
ZFx86	O
.	O
</s>
<s>
Uses	O
0F	O
38	O
encoding	O
on	O
Cyrix	O
6x86MX	B-General_Concept
,	O
MII	O
,	O
MediaGX	B-Device
and	O
Geode	B-Device
.	O
</s>
<s>
These	O
instructions	O
were	O
introduced	O
in	O
the	O
Cyrix	O
6x86MX	B-General_Concept
and	O
MII	O
processors	O
,	O
and	O
were	O
also	O
present	O
in	O
the	O
MediaGXm	B-Device
and	O
Geode	B-Device
GX1	O
processors	O
.	O
</s>
<s>
C&T	O
also	O
developed	O
a	O
386-compatible	O
processor	O
known	O
as	O
the	O
Super386	O
.	O
</s>
<s>
This	O
processor	O
supports	O
,	O
in	O
addition	O
to	O
the	O
basic	O
Intel	B-General_Concept
386	I-General_Concept
instruction	O
set	O
,	O
a	O
number	O
of	O
instructions	O
to	O
support	O
the	O
Super386-specific	O
"	O
SuperStateV	O
"	O
system-management	O
feature	O
.	O
</s>
<s>
The	O
M6117	O
series	O
of	O
embedded	O
microcontrollers	O
feature	O
a	O
386SX-class	O
CPU	O
core	O
with	O
a	O
few	O
M6117-specific	O
additions	O
to	O
the	O
Intel	B-General_Concept
386	I-General_Concept
instruction	O
set	O
.	O
</s>
<s>
The	O
ones	O
documented	O
for	O
DM&P	B-Device
M1167D	O
are	O
:	O
</s>
