<s>
In	O
computer	O
engineering	O
,	O
logic	O
synthesis	O
is	O
a	O
process	O
by	O
which	O
an	O
abstract	O
specification	O
of	O
desired	O
circuit	O
behavior	O
,	O
typically	O
at	O
register	O
transfer	O
level	O
(	O
RTL	O
)	O
,	O
is	O
turned	O
into	O
a	O
design	O
implementation	O
in	O
terms	O
of	O
logic	O
gates	O
,	O
typically	O
by	O
a	O
computer	B-Application
program	I-Application
called	O
a	O
synthesis	O
tool	O
.	O
</s>
<s>
Common	O
examples	O
of	O
this	O
process	O
include	O
synthesis	O
of	O
designs	O
specified	O
in	O
hardware	O
description	O
languages	O
,	O
including	O
VHDL	B-Language
and	O
Verilog	B-Language
.	O
</s>
<s>
Some	O
synthesis	O
tools	O
generate	O
bitstreams	O
for	O
programmable	O
logic	O
devices	O
such	O
as	O
PALs	O
or	O
FPGAs	B-Architecture
,	O
while	O
others	O
target	O
the	O
creation	O
of	O
ASICs	O
.	O
</s>
<s>
Nowadays	O
,	O
the	O
much	O
more	O
efficient	O
Espresso	B-Algorithm
heuristic	I-Algorithm
logic	I-Algorithm
minimizer	I-Algorithm
has	O
become	O
the	O
standard	O
tool	O
for	O
this	O
operation	O
.	O
</s>
<s>
Another	O
area	O
of	O
early	O
research	O
was	O
in	O
state	O
minimization	O
and	O
encoding	O
of	O
finite-state	B-Architecture
machines	I-Architecture
(	O
FSMs	O
)	O
,	O
a	O
task	O
that	O
was	O
the	O
bane	O
of	O
designers	O
.	O
</s>
<s>
Work	O
on	O
LSS	O
and	O
the	O
Yorktown	O
Silicon	B-General_Concept
Compiler	I-General_Concept
spurred	O
rapid	O
research	O
progress	O
in	O
logic	O
synthesis	O
in	O
the	O
1980s	O
.	O
</s>
<s>
Logic	O
design	O
is	O
a	O
step	O
in	O
the	O
standard	O
design	O
cycle	O
in	O
which	O
the	O
functional	B-Algorithm
design	I-Algorithm
of	O
an	O
electronic	O
circuit	O
is	O
converted	O
into	O
the	O
representation	O
which	O
captures	O
logic	O
operations	O
,	O
arithmetic	O
operations	O
,	O
control	O
flow	O
,	O
etc	O
.	O
</s>
<s>
In	O
modern	O
electronic	O
design	O
automation	O
parts	O
of	O
the	O
logical	O
design	O
may	O
be	O
automated	O
using	O
high-level	B-General_Concept
synthesis	I-General_Concept
tools	O
based	O
on	O
the	O
behavioral	O
description	O
of	O
the	O
circuit	O
.	O
</s>
<s>
With	O
a	O
goal	O
of	O
increasing	O
designer	O
productivity	O
,	O
research	O
efforts	O
on	O
the	O
synthesis	O
of	O
circuits	O
specified	O
at	O
the	O
behavioral	O
level	O
have	O
led	O
to	O
the	O
emergence	O
of	O
commercial	O
solutions	O
in	O
2004	O
,	O
which	O
are	O
used	O
for	O
complex	O
ASIC	O
and	O
FPGA	B-Architecture
design	O
.	O
</s>
<s>
Using	O
high-level	B-General_Concept
synthesis	I-General_Concept
,	O
also	O
known	O
as	O
ESL	B-General_Concept
synthesis	I-General_Concept
,	O
the	O
allocation	O
of	O
work	O
to	O
clock	O
cycles	O
and	O
across	O
structural	O
components	O
,	O
such	O
as	O
floating-point	O
ALUs	O
,	O
is	O
done	O
by	O
the	O
compiler	O
using	O
an	O
optimisation	O
procedure	O
,	O
whereas	O
with	O
RTL	O
logic	O
synthesis	O
(	O
even	O
from	O
behavioural	O
Verilog	B-Language
or	O
VHDL	B-Language
,	O
where	O
a	O
thread	O
of	O
execution	O
can	O
make	O
multiple	O
reads	O
and	O
writes	O
to	O
a	O
variable	O
within	O
a	O
clock	O
cycle	O
)	O
those	O
allocation	O
decisions	O
have	O
already	O
been	O
made	O
.	O
</s>
