<s>
The	O
company	O
was	O
known	O
for	O
inventing	O
the	O
first	O
commercially	O
viable	O
field-programmable	B-Architecture
gate	I-Architecture
array	I-Architecture
(	O
FPGA	B-Architecture
)	O
and	O
creating	O
the	O
first	O
fabless	B-Algorithm
manufacturing	I-Algorithm
model	O
.	O
</s>
<s>
Xilinx	O
was	O
founded	O
in	O
Silicon	O
Valley	O
in	O
1984	O
and	O
headquartered	O
in	O
San	O
Jose	O
,	O
United	O
States	O
,	O
with	O
additional	O
offices	O
in	O
Longmont	O
,	O
United	O
States	O
;	O
Dublin	O
,	O
Ireland	O
;	O
Singapore	O
;	O
Hyderabad	O
,	O
India	O
;	O
Beijing	O
,	O
China	O
;	O
Shanghai	B-Device
,	O
China	O
;	O
Brisbane	O
,	O
Australia	O
and	O
Tokyo	O
,	O
Japan	O
.	O
</s>
<s>
Xilinx	O
sells	O
a	O
broad	O
range	O
of	O
FPGAs	B-Architecture
,	O
complex	B-General_Concept
programmable	I-General_Concept
logic	I-General_Concept
devices	I-General_Concept
(	O
CPLDs	B-General_Concept
)	O
,	O
design	O
tools	O
,	O
intellectual	O
property	O
and	O
reference	O
designs	O
.	O
</s>
<s>
"	O
The	O
concept	O
required	O
lots	O
of	O
transistors	B-Application
and	O
,	O
at	O
that	O
time	O
,	O
transistors	B-Application
were	O
considered	O
extremely	O
precious	O
—	O
people	O
thought	O
that	O
Ross	O
's	O
idea	O
was	O
pretty	O
far	O
out	O
"	O
,	O
said	O
Xilinx	O
Fellow	O
Bill	O
Carter	O
,	O
hired	O
in	O
1984	O
to	O
design	O
ICs	O
as	O
Xilinx	O
's	O
eighth	O
employee	O
.	O
</s>
<s>
FPGA	B-Architecture
promised	O
to	O
make	O
specialized	O
circuits	O
profitable	O
.	O
</s>
<s>
Freeman	O
could	O
not	O
convince	O
Zilog	O
to	O
invest	O
in	O
FPGAs	B-Architecture
to	O
chase	O
a	O
market	O
then	O
estimated	O
at	O
$100	O
million	O
,	O
so	O
he	O
and	O
Barnett	O
left	O
to	O
team	O
up	O
with	O
Vonderschmitt	O
,	O
a	O
former	O
colleague	O
.	O
</s>
<s>
Together	O
,	O
they	O
raised	O
$4.5	O
million	O
in	O
venture	O
funding	O
to	O
design	O
the	O
first	O
commercially	O
viable	O
FPGA	B-Architecture
.	O
</s>
<s>
Other	O
FPGA	B-Architecture
makers	O
emerged	O
in	O
the	O
mid-1990s	O
.	O
</s>
<s>
Moshe	O
Gavrielov	O
–	O
an	O
EDA	O
and	O
ASIC	O
industry	O
veteran	O
who	O
was	O
appointed	O
president	O
and	O
CEO	O
in	O
early	O
2008	O
–	O
introduced	O
targeted	O
design	O
platforms	O
that	O
combine	O
FPGAs	B-Architecture
with	O
software	O
,	O
IP	O
cores	O
,	O
boards	O
and	O
kits	O
to	O
address	O
focused	O
target	O
applications	O
.	O
</s>
<s>
In	O
2011	O
,	O
the	O
company	O
introduced	O
the	O
Virtex-7	B-General_Concept
2000T	O
,	O
the	O
first	O
product	O
based	O
on	O
2.5D	O
stacked	O
silicon	O
(	O
based	O
on	O
silicon	O
interposer	O
technology	O
)	O
to	O
deliver	O
larger	O
FPGAs	B-Architecture
than	O
could	O
be	O
built	O
using	O
standard	O
monolithic	O
silicon	O
.	O
</s>
<s>
Xilinx	O
then	O
adapted	O
the	O
technology	O
to	O
combine	O
formerly	O
separate	O
components	O
in	O
a	O
single	O
chip	O
,	O
first	O
combining	O
an	O
FPGA	B-Architecture
with	O
transceivers	O
based	O
on	O
heterogeneous	O
process	O
technology	O
to	O
boost	O
bandwidth	O
capacity	O
while	O
using	O
less	O
power	O
.	O
</s>
<s>
According	O
to	O
former	O
Xilinx	O
CEO	O
Moshe	O
Gavrielov	O
,	O
the	O
addition	O
of	O
a	O
heterogeneous	O
communications	O
device	O
,	O
combined	O
with	O
the	O
introduction	O
of	O
new	O
software	O
tools	O
and	O
the	O
Zynq-7000	O
line	O
of	O
28nm	O
SoC	B-Architecture
devices	O
that	O
combine	O
an	O
ARM	B-Architecture
core	O
with	O
an	O
FPGA	B-Architecture
,	O
are	O
part	O
of	O
shifting	O
its	O
position	O
from	O
a	O
programmable	O
logic	O
device	O
supplier	O
to	O
one	O
delivering	O
“	O
all	O
things	O
programmable	O
”	O
.	O
</s>
<s>
In	O
addition	O
to	O
Zynq-7000	O
,	O
Xilinx	O
product	O
lines	O
include	O
the	O
Virtex	B-General_Concept
,	O
Kintex	O
and	O
Artix	O
series	O
,	O
each	O
including	O
configurations	O
and	O
models	O
optimized	O
for	O
different	O
applications	O
.	O
</s>
<s>
In	O
April	O
2012	O
,	O
the	O
company	O
introduced	O
the	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
-	O
a	O
next-generation	O
SoC-strength	O
design	O
environment	O
for	O
advanced	O
electronic	O
system	O
designs	O
.	O
</s>
<s>
In	O
May	O
,	O
2014	O
,	O
the	O
company	O
shipped	O
the	O
first	O
of	O
the	O
next	O
generation	O
FPGAs	B-Architecture
:	O
the	O
20nm	O
UltraScale	O
.	O
</s>
<s>
In	O
September	O
2017	O
,	O
Amazon.com	B-Application
and	O
Xilinx	O
started	O
a	O
campaign	O
for	O
FPGA	B-Architecture
adoption	O
.	O
</s>
<s>
This	O
campaign	O
enables	O
AWS	B-Application
Marketplace	O
's	O
Amazon	B-Application
Machine	I-Application
Images	I-Application
(	O
AMIs	O
)	O
with	O
associated	O
Amazon	B-Application
FPGA	B-Architecture
Instances	O
created	O
by	O
partners	O
.	O
</s>
<s>
The	O
two	O
companies	O
released	O
software	O
development	O
tools	O
to	O
simplify	O
the	O
creation	O
of	O
FPGA	B-Architecture
technology	O
.	O
</s>
<s>
In	O
October	O
2018	O
,	O
the	O
Xilinx	B-General_Concept
Virtex	I-General_Concept
UltraScale+	O
FPGAs	B-Architecture
and	O
NGCodec	O
's	O
H.265	B-Algorithm
video	O
encoder	O
were	O
used	O
in	O
a	O
cloud-based	O
video	O
coding	O
service	O
using	O
the	O
High	B-Algorithm
Efficiency	I-Algorithm
Video	I-Algorithm
Coding	I-Algorithm
(	O
HEVC	B-Algorithm
)	O
.	O
</s>
<s>
With	O
this	O
certification	O
,	O
developers	O
are	O
able	O
to	O
use	O
the	O
MPSoC	B-General_Concept
platform	O
in	O
AI-based	B-Application
safety	O
-	O
applications	O
of	O
up	O
to	O
SIL	O
3	O
,	O
in	O
industrial	O
4.0	O
platforms	O
of	O
automotive	O
,	O
aerospace	O
,	O
and	O
AI	B-Application
systems	O
.	O
</s>
<s>
Xilinx	O
's	O
platform	O
overlooks	O
the	O
aggregation	O
,	O
pre-processing	O
,	O
and	O
distribution	O
of	O
real-time	O
data	O
,	O
and	O
accelerates	O
the	O
AI	B-Application
processing	O
of	O
the	O
unit	O
.	O
</s>
<s>
The	O
products	O
included	O
the	O
industry	O
's	O
first	O
Defense-grade	O
heterogeneous	O
multi-processor	O
SoC	B-Architecture
devices	O
and	O
encompassed	O
the	O
XQ	O
Zynq	O
UltraScale+	O
MPSoCs	B-General_Concept
and	O
RFSoCs	O
as	O
well	O
as	O
XQ	O
UltraScale+	O
Kintex	O
and	O
Virtex	B-General_Concept
FPGAs	B-Architecture
.	O
</s>
<s>
The	O
initial	O
Alveo	O
line	O
included	O
the	O
U200	O
and	O
U250	O
,	O
which	O
featured	O
16nm	O
UltraScale+	O
Virtex	B-General_Concept
FPGAs	B-Architecture
and	O
DDR4	O
SDRAM	O
.	O
</s>
<s>
The	O
U55C	O
accelerator	O
card	O
was	O
launched	O
in	O
November	O
2021	O
,	O
designed	O
for	O
HPCC	B-Operating_System
and	O
big	B-Application
data	I-Application
workloads	O
by	O
incorporating	O
the	O
RoCE	O
v2-based	O
clustering	O
solution	O
,	O
allowing	O
for	O
FPGA-based	O
HPCC	B-Operating_System
clustering	O
to	O
be	O
integrated	O
into	O
existing	O
data	O
center	O
infrastructures	O
.	O
</s>
<s>
In	O
January	O
2019	O
,	O
Baidu	O
announced	O
that	O
its	O
new	O
edge	B-Device
acceleration	O
computing	O
product	O
,	O
EdgeBoard	O
,	O
was	O
powered	O
by	O
Xilinx	O
.	O
</s>
<s>
Edgeboard	O
is	O
a	O
part	O
of	O
the	O
Baidu	O
Brain	O
AI	B-Application
Hardware	O
Platform	O
Initiative	O
,	O
which	O
encompasses	O
Baidu	O
's	O
open	O
computing	O
services	O
,	O
and	O
hardware	O
and	O
software	O
products	O
for	O
its	O
edge	B-Device
AI	B-Application
applications	O
.	O
</s>
<s>
Edgeboard	O
is	O
based	O
on	O
the	O
Xilinx	O
Zynq	O
UltraScale+	O
MPSoC	B-General_Concept
,	O
which	O
uses	O
real-time	O
processors	O
together	O
with	O
programmable	O
logic	O
.	O
</s>
<s>
In	O
February	O
2019	O
,	O
the	O
company	O
announced	O
two	O
new	O
generations	O
of	O
its	O
Zynq	O
UltraScale+	O
RF	O
system	B-Architecture
on	I-Architecture
chip	I-Architecture
(	O
RFSoC	O
)	O
portfolio	O
.	O
</s>
<s>
The	O
companies	O
have	O
been	O
collaborating	O
since	O
then	O
on	O
advanced	O
networking	O
technology	O
,	O
and	O
in	O
March	O
2019	O
demonstrated	O
their	O
first	O
joint	O
solution	O
:	O
a	O
single-chip	O
FPGA-based	O
100G	O
NIC	B-Protocol
.	O
</s>
<s>
The	O
acquisition	O
enables	O
Xilinx	O
to	O
combine	O
its	O
FPGA	B-Architecture
,	O
MPSoC	B-General_Concept
and	O
ACAP	O
solutions	O
with	O
Solarflare	O
's	O
NIC	B-Protocol
technology	O
.	O
</s>
<s>
In	O
August	O
2019	O
,	O
Xilinx	O
announced	O
that	O
the	O
company	O
would	O
be	O
adding	O
the	O
world	O
's	O
largest	O
FPGA	B-Architecture
-	O
the	O
Virtex	B-General_Concept
Ultrascale+	O
VU19P	O
,	O
to	O
the	O
16nm	O
Virtex	B-General_Concept
Ultrascale+	O
family	O
.	O
</s>
<s>
The	O
VU19P	O
contains	O
35	O
billion	O
transistors	B-Application
.	O
</s>
<s>
Using	O
ACAP	O
,	O
the	O
chips’	O
hardware	O
and	O
software	O
can	O
be	O
programmed	O
to	O
run	O
almost	O
any	O
kind	O
of	O
AI	B-Application
software	I-Application
.	O
</s>
<s>
That	O
same	O
month	O
,	O
the	O
company	O
unveiled	O
the	O
Kria	O
portfolio	O
,	O
a	O
line	O
of	O
small	O
form	O
factor	O
system-on-modules	B-Architecture
(	O
SOMs	O
)	O
that	O
come	O
with	O
a	O
pre-built	O
software	O
stack	O
to	O
simplify	O
development	O
.	O
</s>
<s>
Xilinx	O
sells	O
both	O
FPGAs	B-Architecture
and	O
CPLDs	B-General_Concept
for	O
electronic	O
equipment	O
manufacturers	O
in	O
end	O
markets	O
such	O
as	O
communications	O
,	O
industrial	O
,	O
consumer	O
,	O
automotive	O
and	O
data	B-General_Concept
processing	I-General_Concept
.	O
</s>
<s>
Xilinx	O
's	O
FPGAs	B-Architecture
have	O
been	O
used	O
for	O
the	O
ALICE	O
(	O
A	O
Large	O
Ion	O
Collider	O
Experiment	O
)	O
at	O
the	O
CERN	O
European	O
laboratory	O
on	O
the	O
French-Swiss	O
border	O
to	O
map	O
and	O
disentangle	O
the	O
trajectories	O
of	O
thousands	O
of	O
subatomic	O
particles	O
.	O
</s>
<s>
Xilinx	O
has	O
also	O
engaged	O
in	O
a	O
partnership	O
with	O
the	O
United	O
States	O
Air	O
Force	O
Research	O
Laboratory	O
's	O
Space	O
Vehicles	O
Directorate	O
to	O
develop	O
FPGAs	B-Architecture
to	O
withstand	O
the	O
damaging	O
effects	O
of	O
radiation	O
in	O
space	O
,	O
which	O
are	O
1,000	O
times	O
less	O
sensitive	O
to	O
space	O
radiation	O
than	O
the	O
commercial	O
equivalent	O
,	O
for	O
deployment	O
in	O
new	O
satellites	O
.	O
</s>
<s>
Xilinx	O
FPGAs	B-Architecture
can	O
run	O
a	O
regular	O
embedded	O
OS	O
(	O
such	O
as	O
Linux	B-Application
or	O
vxWorks	B-Operating_System
)	O
and	O
can	O
implement	O
processor	O
peripherals	O
in	O
programmable	O
logic	O
.	O
</s>
<s>
The	O
Virtex-II	O
Pro	O
,	O
Virtex-4	O
,	O
Virtex-5	O
,	O
and	O
Virtex-6	O
FPGA	B-Architecture
families	O
,	O
which	O
include	O
up	O
to	O
two	O
embedded	O
IBM	B-Architecture
PowerPC	I-Architecture
cores	O
,	O
are	O
targeted	O
to	O
the	O
needs	O
of	O
system-on-chip	B-Architecture
(	O
SoC	B-Architecture
)	O
designers	O
.	O
</s>
<s>
)	O
,	O
for	O
domain	O
specific	O
cores	O
(	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
,	O
FFT	O
and	O
FIR	O
cores	O
)	O
to	O
complex	O
systems	O
(	O
multi-gigabit	O
networking	O
cores	O
,	O
the	O
MicroBlaze	B-Device
soft	O
microprocessor	O
and	O
the	O
compact	O
Picoblaze	O
microcontroller	O
)	O
.	O
</s>
<s>
The	O
main	O
design	O
toolkit	O
Xilinx	O
provides	O
engineers	O
is	O
the	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
,	O
an	O
integrated	O
design	O
environment	O
(	O
IDE	O
)	O
with	O
a	O
system-to-IC	O
level	O
tools	O
built	O
on	O
a	O
shared	O
scalable	O
data	O
model	O
and	O
a	O
common	O
debug	O
environment	O
.	O
</s>
<s>
Vivado	B-Algorithm
includes	O
electronic	O
system	O
level	O
(	O
ESL	O
)	O
design	O
tools	O
for	O
synthesizing	O
and	O
verifying	O
C-based	O
algorithmic	O
IP	O
;	O
standards	O
based	O
packaging	O
of	O
both	O
algorithmic	O
and	O
RTL	O
IP	O
for	O
reuse	O
;	O
standards	O
based	O
IP	O
stitching	O
and	O
systems	O
integration	O
of	O
all	O
types	O
of	O
system	O
building	O
blocks	O
;	O
and	O
the	O
verification	O
of	O
blocks	O
and	O
systems	O
.	O
</s>
<s>
A	O
free	O
version	O
WebPACK	O
Edition	O
of	O
Vivado	B-Algorithm
provides	O
designers	O
with	O
a	O
limited	O
version	O
of	O
the	O
design	O
environment	O
.	O
</s>
<s>
Xilinx	O
's	O
Embedded	O
Developer	O
's	O
Kit	O
(	O
EDK	O
)	O
supports	O
the	O
embedded	O
PowerPC	B-Architecture
405	O
and	O
440	O
cores	O
(	O
in	O
Virtex-II	O
Pro	O
and	O
some	O
Virtex-4	O
and	O
-5	O
chips	O
)	O
and	O
the	O
Microblaze	B-Device
core	O
.	O
</s>
<s>
Xilinx	O
's	O
System	O
Generator	O
for	O
DSP	O
implements	O
DSP	O
designs	O
on	O
Xilinx	O
FPGAs	B-Architecture
.	O
</s>
<s>
Xilinx	O
is	O
the	O
only	O
(	O
as	O
of	O
2007	O
)	O
FPGA	B-Architecture
vendor	O
to	O
distribute	O
a	O
native	O
Linux	B-Application
freeware	O
synthesis	O
toolchain	O
.	O
</s>
<s>
Xilinx	O
announced	O
the	O
architecture	O
for	O
a	O
new	O
ARM	O
Cortex-A9-based	O
platform	O
for	O
embedded	B-Architecture
systems	I-Architecture
designers	O
,	O
that	O
combines	O
the	O
software	O
programmability	O
of	O
an	O
embedded	B-Architecture
processor	I-Architecture
with	O
the	O
hardware	O
flexibility	O
of	O
an	O
FPGA	B-Architecture
.	O
</s>
<s>
With	O
this	O
platform	O
,	O
software	O
developers	O
can	O
leverage	O
their	O
existing	O
system	O
code	O
based	O
on	O
ARM	B-Architecture
technology	O
and	O
utilize	O
vast	O
off-the-shelf	O
open-source	O
and	O
commercially	O
available	O
software	O
component	O
libraries	O
.	O
</s>
<s>
Because	O
the	O
system	O
boots	O
an	O
OS	O
at	O
reset	O
,	O
software	O
development	O
can	O
get	O
under	O
way	O
quickly	O
within	O
familiar	O
development	O
and	O
debug	O
environments	O
using	O
tools	O
such	O
as	O
ARM	B-Architecture
's	O
RealView	O
development	O
suite	O
and	O
related	O
third-party	O
tools	O
,	O
Eclipse-based	O
IDEs	O
,	O
GNU	O
,	O
the	O
Xilinx	O
Software	O
Development	O
Kit	O
and	O
others	O
.	O
</s>
<s>
In	O
early	O
2011	O
,	O
Xilinx	O
began	O
shipping	O
the	O
Zynq-7000	O
SoC	B-Architecture
platform	O
immerses	O
ARM	B-Architecture
multi-cores	O
,	O
programmable	O
logic	O
fabric	O
,	O
DSP	O
data	O
paths	O
,	O
memories	O
and	O
I/O	O
functions	O
in	O
a	O
dense	O
and	O
configurable	O
mesh	O
of	O
interconnect	O
.	O
</s>
<s>
Following	O
the	O
introduction	O
of	O
its	O
28nm	O
7-series	O
FPGAs	B-Architecture
,	O
Xilinx	O
revealed	O
that	O
several	O
of	O
the	O
highest-density	O
parts	O
in	O
those	O
FPGA	B-Architecture
product	O
lines	O
will	O
be	O
constructed	O
using	O
multiple	O
dies	O
in	O
one	O
package	O
,	O
employing	O
technology	O
developed	O
for	O
3D	O
construction	O
and	O
stacked-die	O
assemblies	O
.	O
</s>
<s>
The	O
company	O
's	O
stacked	O
silicon	O
interconnect	O
(	O
SSI	O
)	O
technology	O
stacks	O
several	O
(	O
three	O
or	O
four	O
)	O
active	O
FPGA	B-Architecture
dies	O
side	O
by	O
side	O
on	O
a	O
silicon	O
interposer	O
–	O
a	O
single	O
piece	O
of	O
silicon	O
that	O
carries	O
passive	O
interconnect	O
.	O
</s>
<s>
The	O
individual	O
FPGA	B-Architecture
dies	O
are	O
conventional	O
,	O
and	O
are	O
flip-chip	O
mounted	O
by	O
microbumps	O
on	O
to	O
the	O
interposer	O
.	O
</s>
<s>
The	O
interposer	O
provides	O
direct	O
interconnect	O
between	O
the	O
FPGA	B-Architecture
dies	O
,	O
with	O
no	O
need	O
for	O
transceiver	O
technologies	O
such	O
as	O
high-speed	O
SerDes	O
.	O
</s>
<s>
In	O
October	O
2011	O
,	O
Xilinx	O
shipped	O
the	O
first	O
FPGA	B-Architecture
to	O
use	O
the	O
new	O
technology	O
,	O
the	O
Virtex-7	B-General_Concept
2000T	O
FPGA	B-Architecture
,	O
which	O
includes	O
6.8	O
billion	O
transistors	B-Application
and	O
20	O
million	O
ASIC	O
gates	O
.	O
</s>
<s>
The	O
following	O
spring	O
,	O
Xilinx	O
used	O
3D	O
technology	O
to	O
ship	O
the	O
Virtex-7	B-General_Concept
HT	O
,	O
the	O
industry	O
's	O
first	O
heterogeneous	O
FPGAs	B-Architecture
,	O
which	O
combine	O
high	O
bandwidth	O
FPGAs	B-Architecture
with	O
a	O
maximum	O
of	O
sixteen	O
28	O
Gbit/s	O
and	O
seventy-two	O
13.1	O
Gbit/s	O
transceivers	O
to	O
reduce	O
power	O
and	O
size	O
requirements	O
for	O
key	O
Nx100G	O
and	O
400G	O
line	O
card	O
applications	O
and	O
functions	O
.	O
</s>
<s>
In	O
January	O
2011	O
,	O
Xilinx	O
acquired	O
design	O
tool	O
firm	O
AutoESL	O
Design	O
Technologies	O
and	O
added	O
System	O
C	B-Language
high-level	O
design	O
for	O
its	O
6	O
-	O
and	O
7-series	O
FPGA	B-Architecture
families	O
.	O
</s>
<s>
The	O
addition	O
of	O
AutoESL	O
tools	O
extended	O
the	O
design	O
community	O
for	O
FPGAs	B-Architecture
to	O
designers	O
more	O
accustomed	O
to	O
designing	O
at	O
a	O
higher	O
level	O
of	O
abstraction	O
using	O
C	B-Language
,	O
C++	O
and	O
System	O
C	B-Language
.	O
</s>
<s>
In	O
April	O
2012	O
,	O
Xilinx	O
introduced	O
a	O
revised	O
version	O
of	O
its	O
toolset	O
for	O
programmable	O
systems	O
,	O
called	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
.	O
</s>
<s>
Vivado	B-Algorithm
provides	O
faster	O
integration	O
and	O
implementation	O
for	O
programmable	O
systems	O
into	O
devices	O
with	O
3D	O
stacked	O
silicon	O
interconnect	O
technology	O
,	O
ARM	B-Architecture
processing	O
systems	O
,	O
analog	O
mixed	O
signal	O
(	O
AMS	O
)	O
,	O
and	O
many	O
semiconductor	O
intellectual	O
property	O
(	O
IP	O
)	O
cores	O
.	O
</s>
<s>
In	O
July	O
2019	O
,	O
Xilinx	O
acquired	O
NGCodec	O
,	O
developers	O
of	O
FPGA	B-Architecture
accelerated	B-General_Concept
video	O
encoders	O
for	O
video	O
streaming	O
,	O
cloud	B-Application
gaming	I-Application
and	O
cloud	O
mixed	B-General_Concept
reality	I-General_Concept
services	O
.	O
</s>
<s>
NGCodec	O
video	O
encoders	O
include	O
support	O
for	O
H.264/AVC	B-Application
,	O
H.265/HEVC	B-Algorithm
,	O
VP9	B-Algorithm
and	O
AV1	B-Application
,	O
with	O
planned	O
future	O
support	O
for	O
H.266/VVC	B-Algorithm
and	O
AV2	O
.	O
</s>
<s>
In	O
May	O
2020	O
,	O
Xilinx	O
installed	O
its	O
first	O
Adaptive	O
Compute	O
Cluster	O
(	O
XACC	O
)	O
at	O
ETH	O
Zurich	O
in	O
Switzerland	B-Protocol
.	O
</s>
<s>
Before	O
2010	O
,	O
Xilinx	O
offered	O
two	O
main	O
FPGA	B-Architecture
families	O
:	O
the	O
high-performance	O
Virtex	B-General_Concept
series	O
and	O
the	O
high-volume	O
Spartan	O
series	O
,	O
with	O
a	O
cheaper	O
EasyPath	O
option	O
for	O
ramping	O
to	O
volume	O
production	O
.	O
</s>
<s>
The	O
company	O
also	O
provides	O
two	O
CPLD	B-General_Concept
lines	O
:	O
the	O
CoolRunner	O
and	O
the	O
9500	O
series	O
.	O
</s>
<s>
With	O
the	O
introduction	O
of	O
its	O
28nm	O
FPGAs	B-Architecture
in	O
June	O
2010	O
,	O
Xilinx	O
replaced	O
the	O
high-volume	O
Spartan	O
family	O
with	O
the	O
Kintex	O
family	O
and	O
the	O
low-cost	O
Artix	O
family	O
.	O
</s>
<s>
Xilinx	O
's	O
newer	O
FPGA	B-Architecture
products	O
use	O
a	O
High-K	B-Algorithm
Metal	I-Algorithm
Gate	I-Algorithm
(	O
HKMG	B-Algorithm
)	O
process	O
,	O
which	O
reduces	O
static	O
power	O
consumption	O
while	O
increasing	O
logic	O
capacity	O
.	O
</s>
<s>
Virtex-6	O
and	O
Spartan-6	O
FPGA	B-Architecture
families	O
are	O
said	O
to	O
consume	O
50	O
percent	O
less	O
power	O
,	O
and	O
have	O
up	O
to	O
twice	O
the	O
logic	O
capacity	O
compared	O
to	O
the	O
previous	O
generation	O
of	O
Xilinx	O
FPGAs	B-Architecture
.	O
</s>
<s>
In	O
June	O
2010	O
,	O
Xilinx	O
introduced	O
the	O
Xilinx	O
7	O
series	O
:	O
the	O
Virtex-7	B-General_Concept
,	O
Kintex-7	O
,	O
and	O
Artix-7	O
families	O
,	O
promising	O
improvements	O
in	O
system	O
power	O
,	O
performance	O
,	O
capacity	O
,	O
and	O
price	O
.	O
</s>
<s>
These	O
new	O
FPGA	B-Architecture
families	O
are	O
manufactured	O
using	O
TSMC	O
's	O
28nm	O
HKMG	B-Algorithm
process	O
.	O
</s>
<s>
Less	O
than	O
one	O
year	O
after	O
announcing	O
the	O
7	O
series	O
28nm	O
FPGAs	B-Architecture
,	O
Xilinx	O
shipped	O
the	O
world	O
's	O
first	O
28nm	O
FPGA	B-Architecture
device	O
,	O
the	O
Kintex-7	O
.	O
</s>
<s>
In	O
March	O
2011	O
,	O
Xilinx	O
introduced	O
the	O
Zynq-7000	O
family	O
,	O
which	O
integrates	O
a	O
complete	O
ARM	B-Application
Cortex-A9	I-Application
MPCore	I-Application
processor-based	O
system	O
on	O
a	O
28nm	O
FPGA	B-Architecture
for	O
system	O
architects	O
and	O
embedded	O
software	O
developers	O
.	O
</s>
<s>
In	O
Dec	O
,	O
2013	O
,	O
Xilinx	O
introduced	O
the	O
UltraScale	O
series	O
:	O
Virtex	B-General_Concept
UltraScale	O
and	O
Kintex	O
UltraScale	O
families	O
.	O
</s>
<s>
These	O
new	O
FPGA	B-Architecture
families	O
are	O
manufactured	O
by	O
TSMC	O
in	O
its	O
20nm	O
planar	O
process	O
.	O
</s>
<s>
At	O
the	O
same	O
time	O
it	O
announced	O
an	O
UltraScale	O
SoC	B-Architecture
architecture	O
,	O
called	O
Zynq	O
UltraScale+	O
MPSoC	B-General_Concept
,	O
in	O
TSMC	O
16nm	O
FinFET	O
process	O
.	O
</s>
<s>
In	O
March	O
2021	O
,	O
Xilinx	O
announced	O
a	O
new	O
cost-optimized	O
portfolio	O
with	O
Artix	O
and	O
Zynq	O
UltraScale+	O
devices	O
,	O
fabricated	B-Architecture
on	O
TSMC	O
's	O
16nm	O
process	O
.	O
</s>
<s>
The	O
Virtex	B-General_Concept
series	O
of	O
FPGAs	B-Architecture
have	O
integrated	O
features	O
that	O
include	O
FIFO	O
and	O
ECC	O
logic	O
,	O
DSP	O
blocks	O
,	O
PCI-Express	O
controllers	O
,	O
Ethernet	O
MAC	O
blocks	O
,	O
and	O
high-speed	O
transceivers	O
.	O
</s>
<s>
In	O
addition	O
to	O
FPGA	B-Architecture
logic	O
,	O
the	O
Virtex	B-General_Concept
series	O
includes	O
embedded	O
fixed	O
function	O
hardware	O
for	O
commonly	O
used	O
functions	O
such	O
as	O
multipliers	O
,	O
memories	O
,	O
serial	O
transceivers	O
and	O
microprocessor	O
cores	O
.	O
</s>
<s>
The	O
Virtex	B-General_Concept
7	O
family	O
,	O
is	O
based	O
on	O
a	O
28nm	O
design	O
and	O
is	O
reported	O
to	O
deliver	O
a	O
two-fold	O
system	O
performance	O
improvement	O
at	O
50	O
percent	O
lower	O
power	O
compared	O
to	O
previous	O
generation	O
Virtex-6	O
devices	O
.	O
</s>
<s>
In	O
addition	O
,	O
Virtex-7	B-General_Concept
doubles	O
the	O
memory	O
bandwidth	O
compared	O
to	O
previous	O
generation	O
Virtex	B-General_Concept
FPGAs	B-Architecture
with	O
1866Mbit/s	O
memory	O
interfacing	O
performance	O
and	O
over	O
two	O
million	O
logic	O
cells	O
.	O
</s>
<s>
In	O
2011	O
,	O
Xilinx	O
began	O
shipping	O
sample	O
quantities	O
of	O
the	O
Virtex-7	B-General_Concept
2000T	O
"	O
3D	O
FPGA	B-Architecture
"	O
,	O
which	O
combines	O
four	O
smaller	O
FPGAs	B-Architecture
into	O
a	O
single	O
package	O
by	O
placing	O
them	O
on	O
a	O
special	O
silicon	O
interconnection	O
pad	O
(	O
called	O
an	O
interposer	O
)	O
to	O
deliver	O
6.8	O
billion	O
transistors	B-Application
in	O
a	O
single	O
large	O
chip	O
.	O
</s>
<s>
The	O
interposer	O
provides	O
10,000	O
data	O
pathways	O
between	O
the	O
individual	O
FPGAs	B-Architecture
–	O
roughly	O
10	O
to	O
100	O
times	O
more	O
than	O
would	O
usually	O
be	O
available	O
on	O
a	O
board	O
–	O
to	O
create	O
a	O
single	O
FPGA	B-Architecture
.	O
</s>
<s>
In	O
2012	O
,	O
using	O
the	O
same	O
3D	O
technology	O
,	O
Xilinx	O
introduced	O
initial	O
shipments	O
of	O
their	O
Virtex-7	B-General_Concept
H580T	O
FPGA	B-Architecture
,	O
a	O
heterogeneous	O
device	O
,	O
so	O
called	O
because	O
it	O
comprises	O
two	O
FPGA	B-Architecture
dies	O
and	O
one	O
8-channel	O
28Gbit/s	O
transceiver	O
die	O
in	O
the	O
same	O
package	O
.	O
</s>
<s>
The	O
Virtex-6	O
family	O
is	O
built	O
on	O
a	O
40nm	O
process	O
for	O
compute-intensive	O
electronic	O
systems	O
,	O
and	O
the	O
company	O
claims	O
it	O
consumes	O
15	O
percent	O
less	O
power	O
and	O
has	O
15	O
percent	O
improved	O
performance	O
over	O
competing	O
40nm	O
FPGAs	B-Architecture
.	O
</s>
<s>
The	O
Virtex-5	O
LX	O
and	O
the	O
LXT	O
are	O
intended	O
for	O
logic-intensive	O
applications	O
,	O
and	O
the	O
Virtex-5	O
SXT	O
is	O
for	O
DSP	O
applications	O
.	O
</s>
<s>
With	O
the	O
Virtex-5	O
,	O
Xilinx	O
changed	O
the	O
logic	O
fabric	O
from	O
four-input	O
LUTs	O
to	O
six-input	O
LUTs	O
.	O
</s>
<s>
With	O
the	O
increasing	O
complexity	O
of	O
combinational	O
logic	O
functions	O
required	O
by	O
SoC	B-Architecture
designs	O
,	O
the	O
percentage	O
of	O
combinational	O
paths	O
requiring	O
multiple	O
four-input	O
LUTs	O
had	O
become	O
a	O
performance	O
and	O
routing	O
bottleneck	O
.	O
</s>
<s>
The	O
Virtex-5	O
series	O
is	O
a	O
65nm	O
design	O
fabricated	B-Architecture
in	O
1.0V	O
,	O
triple-oxide	O
process	O
technology	O
.	O
</s>
<s>
Legacy	O
Virtex	B-General_Concept
devices	O
(	O
Virtex	B-General_Concept
,	O
Virtex-II	O
,	O
Virtex-II	O
Pro	O
,	O
Virtex	B-General_Concept
4	O
)	O
are	O
still	O
available	O
,	O
but	O
are	O
not	O
recommended	O
for	O
use	O
in	O
new	O
designs	O
.	O
</s>
<s>
The	O
Kintex-7	O
family	O
is	O
the	O
first	O
Xilinx	O
mid-range	O
FPGA	B-Architecture
family	O
that	O
the	O
company	O
claims	O
delivers	O
Virtex-6	O
family	O
performance	O
at	O
less	O
than	O
half	O
the	O
price	O
while	O
consuming	O
50	O
percent	O
less	O
power	O
.	O
</s>
<s>
In	O
August	O
2018	O
,	O
SK	O
Telecom	O
deployed	O
Xilinx	O
Kintex	O
UltraScale	O
FPGAs	B-Architecture
as	O
their	O
artificial	B-Application
intelligence	I-Application
accelerators	O
at	O
their	O
data	O
centers	O
in	O
South	O
Korea	O
.	O
</s>
<s>
The	O
FPGAs	B-Architecture
run	O
SKT	O
's	O
automatic	O
speech-recognition	O
application	O
to	O
accelerate	O
Nugu	O
,	O
SKT	O
's	O
voice-activated	O
assistant	O
.	O
</s>
<s>
The	O
Artix-7	O
family	O
delivers	O
50	O
percent	O
lower	O
power	O
and	O
35	O
percent	O
lower	O
cost	O
compared	O
to	O
the	O
Spartan-6	O
family	O
and	O
is	O
based	O
on	O
the	O
unified	O
Virtex-series	O
architecture	O
.	O
</s>
<s>
The	O
Zynq-7000	O
family	O
of	O
SoCs	B-Architecture
addresses	O
high-end	O
embedded-system	O
applications	O
,	O
such	O
as	O
video	O
surveillance	O
,	O
automotive-driver	O
assistance	O
,	O
next-generation	O
wireless	O
,	O
and	O
factory	O
automation	O
.	O
</s>
<s>
The	O
Zynq	O
architecture	O
differs	O
from	O
previous	O
marriages	O
of	O
programmable	O
logic	O
and	O
embedded	B-Architecture
processors	I-Architecture
by	O
moving	O
from	O
an	O
FPGA-centric	O
platform	O
to	O
a	O
processor-centric	O
model	O
.	O
</s>
<s>
For	O
software	O
developers	O
,	O
Zynq-7000	O
appear	O
the	O
same	O
as	O
a	O
standard	O
,	O
fully	O
featured	O
ARM	O
processor-based	O
system-on-chip	B-Architecture
(	O
SOC	B-Architecture
)	O
,	O
booting	O
immediately	O
at	O
power-up	O
and	O
capable	O
of	O
running	O
a	O
variety	O
of	O
operating	O
systems	O
independently	O
of	O
the	O
programmable	O
logic	O
.	O
</s>
<s>
In	O
2013	O
,	O
Xilinx	O
introduced	O
the	O
Zynq-7100	O
,	O
which	O
integrates	O
digital	B-General_Concept
signal	I-General_Concept
processing	I-General_Concept
(	O
DSP	O
)	O
to	O
meet	O
emerging	O
programmable	O
systems	O
integration	O
requirements	O
of	O
wireless	O
,	O
broadcast	O
,	O
medical	O
and	O
military	O
applications	O
.	O
</s>
<s>
The	O
new	O
Zynq-7000	O
product	O
family	O
posed	O
a	O
key	O
challenge	O
for	O
system	O
designers	O
,	O
because	O
Xilinx	O
ISE	O
design	O
software	O
had	O
not	O
been	O
developed	O
to	O
handle	O
the	O
capacity	O
and	O
complexity	O
of	O
designing	O
with	O
an	O
FPGA	B-Architecture
with	O
an	O
ARM	B-Architecture
core	O
.	O
</s>
<s>
Xilinx	O
's	O
new	O
Vivado	B-Algorithm
Design	I-Algorithm
Suite	I-Algorithm
addressed	O
this	O
issue	O
,	O
because	O
the	O
software	O
was	O
developed	O
for	O
higher	O
capacity	O
FPGAs	B-Architecture
,	O
and	O
it	O
included	O
high	B-General_Concept
level	I-General_Concept
synthesis	I-General_Concept
(	O
HLS	O
)	O
functionality	O
that	O
allows	O
engineers	O
to	O
compile	O
the	O
co-processors	B-General_Concept
from	O
a	O
C-based	O
description	O
.	O
</s>
<s>
The	O
AXIOM	B-Algorithm
,	O
the	O
world	O
's	O
first	O
digital	B-Device
cinema	I-Device
camera	I-Device
that	O
is	O
open	O
source	O
hardware	O
,	O
contains	O
a	O
Zynq-7000	O
.	O
</s>
<s>
displays	O
,	O
set-top	O
boxes	O
,	O
wireless	B-Device
routers	I-Device
and	O
other	O
applications	O
.	O
</s>
<s>
The	O
Spartan-7	O
family	O
,	O
built	O
on	O
the	O
same	O
28nm	O
process	O
used	O
in	O
the	O
other	O
7-Series	O
FPGAs	B-Architecture
,	O
was	O
announced	O
in	O
2015	O
,	O
and	O
became	O
available	O
in	O
2017	O
.	O
</s>
<s>
Unlike	O
the	O
Artix-7	O
family	O
and	O
the	O
"	O
LXT	O
"	O
members	O
of	O
the	O
Spartan-6	O
family	O
,	O
the	O
Spartan-7	O
FPGAs	B-Architecture
lack	O
high-bandwidth	O
transceivers	O
.	O
</s>
<s>
Because	O
EasyPath	O
devices	O
are	O
identical	O
to	O
the	O
FPGAs	B-Architecture
that	O
customers	O
are	O
already	O
using	O
the	O
parts	O
can	O
be	O
produced	O
faster	O
and	O
more	O
reliably	O
from	O
the	O
time	O
they	O
are	O
ordered	O
compared	O
to	O
similar	O
competing	O
programs	O
.	O
</s>
<s>
Versal	O
is	O
Xilinx	O
's	O
7nm	O
architecture	O
that	O
targets	O
heterogeneous	O
computing	O
needs	O
in	O
datacenter	O
acceleration	O
applications	O
,	O
in	O
artificial	B-Application
intelligence	I-Application
acceleration	O
at	O
the	O
edge	B-Device
,	O
Internet	B-Operating_System
of	I-Operating_System
Things	I-Operating_System
(	O
IoT	B-Operating_System
)	O
applications	O
and	O
embedded	B-Architecture
computing	I-Architecture
.	O
</s>
<s>
The	O
Everest	O
program	O
focuses	O
on	O
the	O
Versal	O
Adaptive	O
Compute	O
Acceleration	O
Platform	O
(	O
ACAP	O
)	O
,	O
a	O
product	O
category	O
combining	O
a	O
traditional	O
FPGA	B-Architecture
fabric	O
with	O
an	O
ARM	B-Architecture
system	B-Architecture
on	I-Architecture
chip	I-Architecture
and	O
a	O
set	O
of	O
coprocessors	B-General_Concept
,	O
connected	O
through	O
a	O
network	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
.	O
</s>
<s>
Xilinx	O
's	O
goal	O
was	O
to	O
reduce	O
the	O
barriers	O
to	O
adoption	O
of	O
FPGAs	B-Architecture
for	O
accelerated	B-General_Concept
compute-intensive	O
datacenter	O
workloads	O
.	O
</s>
<s>
They	O
are	O
designed	O
for	O
a	O
wide	O
range	O
of	O
applications	O
in	O
the	O
fields	O
of	O
big	B-Application
data	I-Application
and	O
machine	O
learning	O
,	O
including	O
video	O
transcoding	O
,	O
database	O
querying	O
,	O
data	O
compression	O
,	O
search	O
,	O
AI	B-Application
inferencing	O
,	O
machine	B-General_Concept
vision	I-General_Concept
,	O
computer	B-Application
vision	I-Application
,	O
autonomous	O
vehicles	O
,	O
genomics	O
,	O
computational	O
storage	O
and	O
network	O
acceleration	O
.	O
</s>
