<s>
This	O
list	B-Device
of	I-Device
Mac	I-Device
models	I-Device
grouped	I-Device
by	I-Device
CPU	I-Device
type	I-Device
contains	O
all	O
central	B-General_Concept
processing	I-General_Concept
units	I-General_Concept
(	O
CPUs	O
)	O
used	O
by	O
Apple	O
Inc	O
.	O
for	O
their	O
Mac	B-Device
computers	I-Device
.	O
</s>
<s>
It	O
is	O
grouped	O
by	O
processor	O
family	O
,	O
processor	O
model	O
,	O
and	O
then	O
chronologically	O
by	O
Mac	B-Device
models	O
.	O
</s>
<s>
The	O
Motorola	B-Device
68000	I-Device
was	O
the	O
first	O
Apple	B-Device
Macintosh	I-Device
processor	O
.	O
</s>
<s>
It	O
has	O
32-bit	O
CPU	B-General_Concept
registers	I-General_Concept
,	O
a	O
24-bit	O
address	B-Architecture
bus	I-Architecture
,	O
and	O
a	O
16-bit	O
data	B-Architecture
path	I-Architecture
;	O
Motorola	O
referred	O
to	O
it	O
as	O
a	O
"	O
16-/32	O
-bit	O
microprocessor.	O
"	O
</s>
<s>
The	O
Motorola	B-Device
68020	I-Device
was	O
the	O
first	O
32-bit	O
Mac	B-Device
processor	O
,	O
first	O
used	O
on	O
the	O
Macintosh	B-Device
II	I-Device
.	O
</s>
<s>
The	O
68020	B-Device
has	O
many	O
improvements	O
over	O
the	O
68000	B-Device
,	O
including	O
an	O
instruction	B-General_Concept
cache	I-General_Concept
,	O
and	O
was	O
the	O
first	O
Mac	B-Device
processor	O
to	O
support	O
a	O
paged	B-General_Concept
memory	I-General_Concept
management	I-General_Concept
unit	I-General_Concept
,	O
the	O
Motorola	B-General_Concept
68851	I-General_Concept
.	O
</s>
<s>
The	O
Macintosh	B-Device
LC	I-Device
configured	O
the	O
68020	B-Device
to	O
use	O
a	O
16-bit	O
system	O
bus	O
with	O
ASICs	O
that	O
limited	O
RAM	O
to	O
10MB	O
(	O
as	O
opposed	O
to	O
the	O
32-bit	O
limit	O
of	O
4GB	O
)	O
.	O
</s>
<s>
The	O
Motorola	B-Device
68030	I-Device
was	O
the	O
first	O
Mac	B-Device
processor	O
with	O
an	O
integrated	O
paged	B-General_Concept
memory	I-General_Concept
management	I-General_Concept
unit	I-General_Concept
,	O
allowing	O
for	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
Another	O
improvement	O
over	O
the	O
68020	B-Device
was	O
the	O
addition	O
of	O
a	O
data	B-General_Concept
cache	I-General_Concept
.	O
</s>
<s>
The	O
Motorola	B-Device
68040	I-Device
has	O
improved	O
per-clock	O
performance	O
compared	O
to	O
the	O
68030	B-Device
,	O
as	O
well	O
as	O
larger	O
instruction	O
and	O
data	B-General_Concept
caches	I-General_Concept
,	O
and	O
was	O
the	O
first	O
Mac	B-Device
processor	O
with	O
an	O
integrated	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
MC68LC040	O
version	O
was	O
less	O
expensive	O
because	O
it	O
omitted	O
the	O
floating-point	B-General_Concept
unit	I-General_Concept
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
601	O
was	O
the	O
first	O
Mac	B-Device
processor	O
to	O
support	O
the	O
32-bit	O
PowerPC	B-Architecture
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
.	O
</s>
<s>
Processor	O
Model	O
Clock	O
speed(MHz )	O
FSB	B-Architecture
speed( 	O
MT/s	O
)	O
L1	O
cache(KB )	O
(	O
data/instr	O
.	O
)	O
</s>
<s>
Processor	O
Model	O
Clock	O
speed(MHz )	O
FSB	B-Architecture
speed( 	O
MT/s	O
)	O
L1	O
cache(KB )	O
(	O
data/instr	O
.	O
)	O
</s>
<s>
The	O
PowerPC	B-Architecture
604e	O
was	O
the	O
first	O
Mac	B-Device
processor	O
available	O
in	O
a	O
symmetric	B-Operating_System
multiprocessing	I-Operating_System
(	O
SMP	O
)	O
configuration	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
7400	O
was	O
the	O
first	O
Mac	B-Device
processor	O
to	O
include	O
an	O
AltiVec	B-General_Concept
vector	B-Operating_System
processing	I-Operating_System
unit	I-Operating_System
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
7455	O
was	O
the	O
first	O
Mac	B-Device
processor	O
over	O
1GHz	O
.	O
</s>
<s>
The	O
PowerPC	B-General_Concept
970	I-General_Concept
(	O
"	O
G5	B-Device
"	O
)	O
was	O
the	O
first	O
64-bit	B-Device
Mac	B-Device
processor	O
.	O
</s>
<s>
The	O
PowerPC	B-Architecture
970MP	B-General_Concept
was	O
the	O
first	O
dual-core	B-Architecture
Mac	B-Device
processor	O
and	O
the	O
first	O
to	O
be	O
found	O
in	O
a	O
quad-core	B-Architecture
configuration	O
.	O
</s>
<s>
It	O
was	O
also	O
the	O
first	O
Mac	B-Device
processor	O
with	O
partitioning	O
and	O
virtualization	O
capabilities	O
.	O
</s>
<s>
Apple	O
only	O
used	O
three	O
variants	O
of	O
the	O
G5	B-Device
,	O
and	O
soon	O
moved	O
entirely	O
onto	O
Intel	O
architecture	O
.	O
</s>
<s>
Yonah	B-Device
was	O
the	O
first	O
Mac	B-Device
processor	O
to	O
support	O
the	O
IA-32	B-Device
instruction	B-General_Concept
set	I-General_Concept
architecture	I-General_Concept
,	O
in	O
addition	O
to	O
the	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
and	O
SSE3	B-General_Concept
extension	O
instruction	B-General_Concept
sets	I-General_Concept
.	O
</s>
<s>
Woodcrest	O
added	O
support	O
for	O
the	O
SSSE3	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
<s>
Merom	B-Device
was	O
the	O
first	O
Mac	B-Device
processor	O
to	O
support	O
the	O
x86-64	B-Device
instruction	B-General_Concept
set	I-General_Concept
,	O
as	O
well	O
as	O
the	O
first	O
64-bit	B-Device
processor	I-Device
to	O
appear	O
in	O
a	O
Mac	B-Device
notebook	O
.	O
</s>
<s>
Clovertown	O
was	O
the	O
first	O
quad-core	B-Architecture
Mac	B-Device
processor	O
and	O
the	O
first	O
to	O
be	O
found	O
in	O
an	O
8-core	O
configuration	O
.	O
</s>
<s>
Penryn	B-Device
added	O
support	O
for	O
a	O
subset	O
for	O
SSE4	B-General_Concept
(	O
SSE4.1	O
)	O
.	O
</s>
<s>
Bloomfield	B-Device
and	O
Gainestown	O
introduced	O
a	O
number	O
of	O
notable	O
features	O
for	O
the	O
first	O
time	O
in	O
any	O
Mac	B-Device
processors	O
:	O
</s>
<s>
Integrated	B-General_Concept
memory	I-General_Concept
controllers	I-General_Concept
(	O
with	O
on-die	O
DMI	B-Architecture
or	O
QPI	B-Architecture
)	O
.	O
</s>
<s>
Simultaneous	B-Operating_System
multithreading	I-Operating_System
(	O
branded	O
as	O
Hyper-threading	B-Operating_System
)	O
.	O
</s>
<s>
Full	O
support	O
for	O
the	O
SSE4	B-General_Concept
instruction	B-General_Concept
set	I-General_Concept
(	O
SSE4.2	O
)	O
.	O
</s>
<s>
Support	O
for	O
Intel	B-Device
Turbo	I-Device
Boost	I-Device
.	O
</s>
<s>
Four	O
cores	O
on	O
a	O
single	O
die	O
rather	O
than	O
a	O
multi-chip	B-Algorithm
module	I-Algorithm
of	O
two	O
dual-core	B-Architecture
dies	O
.	O
</s>
<s>
Arrandale	O
introduced	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
an	O
on-die	O
integrated	O
GPU	B-Architecture
.	O
</s>
<s>
Sandy	O
Bridge	O
added	O
support	O
for	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
,	O
a	O
dedicated	O
on-die	O
video	O
encoding	O
and	O
decoding	O
core	O
.	O
</s>
<s>
It	O
was	O
also	O
the	O
first	O
quad-core	B-Architecture
processor	I-Architecture
to	O
appear	O
in	O
a	O
Mac	B-Device
notebook	O
.	O
</s>
<s>
Processor	O
Model	O
Clock	O
speed(GHz )	O
L2	O
cache(KB )	O
L3	O
cache(MB )	O
Cores	O
perCPU	O
HT	B-Operating_System
ITB	B-Device
Introduced	O
Discontinued	O
Core	O
i5	O
(	O
2-core	O
)	O
MacBook	B-Device
Pro	I-Device
(	O
Early	O
2011	O
)	O
MacBook	B-Device
Pro	I-Device
(	O
Late	O
2011	O
)	O
2.3	O
2×256	O
3	O
2	O
March	O
2011	O
June	O
2012	O
Mac	B-Device
mini	I-Device
(	O
Mid	O
2011	O
)	O
2.3	O
–	O
2.5	O
2×256	O
3	O
2	O
July	O
2011	O
October	O
2012	O
Core	O
i7	O
(	O
2-core	O
)	O
MacBook	B-Device
Pro	I-Device
(	O
Early	O
2011	O
)	O
MacBook	B-Device
Pro	I-Device
(	O
Late	O
2011	O
)	O
2.7	O
–	O
2.8	O
2×256	O
4	O
2	O
March	O
2011	O
June	O
2012	O
Mac	B-Device
mini	I-Device
(	O
Mid	O
2011	O
)	O
2.7	O
2×256	O
4	O
2	O
July	O
2011	O
October	O
2012	O
Core	O
i7	O
(	O
4-core	O
)	O
MacBook	B-Device
Pro	I-Device
(	O
Early	O
2011	O
)	O
MacBook	B-Device
Pro	I-Device
(	O
Late	O
2011	O
)	O
2.0	O
–	O
2.5	O
4×256	O
6	O
–	O
8	O
4	O
March	O
2011	O
June	O
2012	O
iMac	B-Device
(	O
Mid	O
2011	O
)	O
2.8	O
–	O
3.4	O
4×256	O
8	O
4	O
May	O
2011	O
October	O
2012	O
Mac	B-Device
mini	I-Device
Server	O
(	O
Mid	O
2011	O
)	O
2.0	O
4×256	O
6	O
4	O
July	O
2011	O
October	O
2012	O
Core	O
i3	O
(	O
2-core	O
)	O
iMac	B-Device
(	O
Late	O
2011	O
education	O
only	O
)	O
3.1	O
2×256	O
3	O
2	O
February	O
2011	O
?	O
</s>
<s>
The	O
Crystal	O
Well	O
variant	O
used	O
in	O
some	O
MacBook	B-Device
Pros	I-Device
contains	O
an	O
on-package	O
L4	O
cache	O
shared	O
between	O
the	O
CPU	O
and	O
integrated	O
graphics	O
.	O
</s>
<s>
Coffee	O
Lake	O
was	O
the	O
first	O
6-core	O
processor	O
to	O
appear	O
in	O
a	O
Mac	B-Device
notebook	O
.	O
</s>
<s>
Ice	O
Lake	O
(	O
Sunny	B-Device
Cove	I-Device
)	O
is	O
a	O
10th	O
generation	O
chip	O
.	O
</s>
<s>
The	O
M1	B-Device
is	O
a	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
fabricated	O
by	O
TSMC	O
on	O
the	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
and	O
contains	O
16	O
billion	O
transistors	O
.	O
</s>
<s>
Its	O
CPU	B-Architecture
cores	I-Architecture
are	O
the	O
first	O
to	O
be	O
used	O
in	O
a	O
Mac	B-Device
processor	O
designed	O
by	O
Apple	O
and	O
the	O
first	O
to	O
use	O
the	O
ARM	B-Architecture
instruction	I-Architecture
set	I-Architecture
architecture	O
.	O
</s>
<s>
It	O
has	O
8	O
CPU	B-Architecture
cores	I-Architecture
(	O
4	O
performance	O
and	O
4	O
efficiency	O
)	O
,	O
up	O
to	O
8	O
GPU	B-Architecture
cores	O
,	O
and	O
a	O
16-core	O
Neural	O
Engine	O
,	O
as	O
well	O
as	O
LPDDR4X	O
memory	O
with	O
a	O
bandwidth	O
of	O
68	O
GB/s	O
.	O
</s>
<s>
The	O
M1	B-Device
Pro	I-Device
and	O
M1	B-Device
Max	I-Device
SoCs	O
are	O
fabricated	O
by	O
TSMC	O
on	O
the	O
5nm	B-Algorithm
process	B-Architecture
and	O
contain	O
33.7	O
and	O
57	O
billion	O
transistors	O
respectively	O
.	O
</s>
<s>
Both	O
have	O
10	B-Algorithm
CPU	B-Architecture
cores	I-Architecture
(	O
8	O
performance	O
and	O
2	O
efficiency	O
)	O
and	O
a	O
16-core	O
Neural	O
Engine	O
.	O
</s>
<s>
The	O
M1	B-Device
Pro	I-Device
and	O
M1	B-Device
Max	I-Device
have	O
a	O
16-core	O
and	O
32-core	O
GPU	B-Architecture
,	O
and	O
a	O
256-bit	O
and	O
512-bit	O
LPDDR5	O
memory	O
bus	O
supporting	O
200	O
and	O
400	O
GB/s	O
bandwidth	O
respectively	O
.	O
</s>
<s>
Both	O
chips	O
were	O
first	O
introduced	O
in	O
the	O
MacBook	B-Device
Pro	I-Device
in	O
October	O
2021	O
.	O
</s>
<s>
On	O
March	O
8	O
,	O
2022	O
,	O
the	O
M1	B-Device
Ultra	I-Device
,	O
a	O
processor	O
combining	O
two	O
M1	B-Device
Max	I-Device
chips	O
in	O
one	O
package	O
,	O
was	O
announced	O
.	O
</s>
<s>
It	O
is	O
initially	O
available	O
exclusively	O
in	O
the	O
highest-end	O
variants	O
of	O
the	O
Mac	B-Device
Studio	I-Device
and	O
was	O
released	O
simultaneously	O
with	O
on	O
March	O
18	O
,	O
2022	O
.	O
</s>
<s>
All	O
parameters	O
of	O
the	O
M1	B-Device
Max	I-Device
processors	O
are	O
doubled	O
in	O
M1	B-Device
Ultra	I-Device
processors	O
,	O
as	O
they	O
are	O
essentially	O
two	O
M1	B-Device
Max	I-Device
chips	O
operating	O
in	O
parallel	O
;	O
they	O
are	O
,	O
however	O
,	O
packed	O
as	O
one	O
processor	O
package	O
(	O
in	O
size	O
being	O
bigger	O
than	O
Socket	O
AM4	O
AMD	O
Ryzen	O
processor	O
)	O
and	O
seen	O
as	O
one	O
M1	B-Device
Ultra	I-Device
processor	O
in	O
macOS	B-Operating_System
.	O
</s>
<s>
The	O
M2	O
is	O
a	O
system	B-Architecture
on	I-Architecture
a	I-Architecture
chip	I-Architecture
fabricated	O
by	O
TSMC	O
on	O
an	O
enhanced	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
,	O
containing	O
20	O
billion	O
transistors	O
.	O
</s>
<s>
It	O
has	O
8	O
CPU	B-Architecture
cores	I-Architecture
(	O
4	O
performance	O
and	O
4	O
efficiency	O
)	O
,	O
up	O
to	O
10	B-Algorithm
GPU	B-Architecture
cores	O
,	O
and	O
a	O
16	O
core	O
Neural	O
Engine	O
,	O
as	O
well	O
as	O
LPDDR5	O
memory	O
with	O
a	O
bandwidth	O
of	O
100	O
GB/s	O
.	O
</s>
<s>
The	O
M2	O
Pro	O
and	O
M2	O
Max	O
SoCs	O
are	O
fabricated	O
by	O
TSMC	O
on	O
an	O
enhanced	O
5	B-Algorithm
nm	I-Algorithm
process	I-Algorithm
and	O
contain	O
40	O
and	O
67	O
billion	O
transistors	O
respectively	O
.	O
</s>
<s>
Both	O
have	O
12	O
CPU	B-Architecture
cores	I-Architecture
(	O
8	O
performance	O
and	O
4	O
efficiency	O
)	O
and	O
a	O
16-core	O
Neural	O
Engine	O
.	O
</s>
<s>
The	O
M2	O
Pro	O
and	O
M2	O
Max	O
have	O
a	O
19-core	O
and	O
38-core	O
GPU	B-Architecture
,	O
and	O
a	O
256-bit	O
and	O
512-bit	O
LPDDR5	O
memory	O
bus	O
supporting	O
200	O
and	O
400	O
GB/s	O
bandwidth	O
respectively	O
.	O
</s>
<s>
Both	O
chips	O
were	O
first	O
introduced	O
in	O
the	O
MacBook	B-Device
Pro	I-Device
in	O
January	O
2023	O
.	O
</s>
