<s>
This	O
is	O
a	O
list	O
of	O
processors	O
that	O
implement	O
the	O
MIPS	B-Device
instruction	I-Device
set	I-Device
architecture	O
,	O
sorted	O
by	O
year	O
,	O
process	B-Architecture
size	I-Architecture
,	O
frequency	O
,	O
die	O
area	O
,	O
and	O
so	O
on	O
.	O
</s>
<s>
These	O
processors	O
are	O
designed	O
by	O
Imagination	O
Technologies	O
,	O
MIPS	B-Device
Technologies	O
,	O
and	O
others	O
.	O
</s>
<s>
It	O
displays	O
an	O
overview	O
of	O
the	O
MIPS	B-Device
processors	O
with	O
performance	O
and	O
functionality	O
versus	O
capabilities	O
for	O
the	O
more	O
recent	O
MIPS	B-Device
Aptiv	O
families	O
.	O
</s>
<s>
MIPS	B-Device
Technologies	O
was	O
acquired	O
17	O
December	O
2012	O
,	O
by	O
Imagination	O
Technologies	O
.	O
</s>
<s>
Imagination	O
Technologies	O
sold	O
MIPS	B-Device
processor	B-General_Concept
rights	O
to	O
Tallwood	O
MIPS	B-Device
Inc	O
in	O
2017	O
.	O
</s>
<s>
MIPS	B-Device
Technologies	O
was	O
acquired	O
by	O
Wave	O
Computing	O
in	O
2018	O
,	O
where	O
"	O
MIPS	B-Device
operates	O
as	O
an	O
IP	O
licensing	O
business	O
unit	O
"	O
.	O
</s>
<s>
The	O
CPU	O
IP	O
cores	O
comprising	O
the	O
MIPS	B-Device
Series5	O
‘	O
Warrior’	O
family	O
are	O
based	O
on	O
MIPS32	O
release	O
5	O
and	O
MIPS64	O
release	O
6	O
,	O
and	O
will	O
come	O
in	O
three	O
classes	O
of	O
performance	O
and	O
features	O
:	O
</s>
<s>
'	O
Warrior	O
I-class	O
'	O
:	O
mid-range	O
,	O
feature-rich	O
MIPS	B-Device
CPUs	O
following	O
on	O
from	O
the	O
highly	O
efficient	O
interAptiv	O
family	O
.	O
</s>
<s>
MIPS	B-Device
version	O
level	O
Processor	B-General_Concept
Year	O
Process	O
(	O
nm	O
)	O
Frequency	O
(	O
GHz	O
)	O
Transistors	O
(	O
billions	O
)	O
Die	O
area	O
(	O
mm2	O
)	O
Pin	O
count	O
Power	O
(	O
W	O
)	O
Voltage	O
(	O
V	O
)	O
D	O
.	O
cache	O
(	O
KB	O
)	O
I	O
.	O
cache	O
(	O
KB	O
)	O
MMU	B-General_Concept
L2	O
cache	O
L3	O
cache	O
Features	O
MIPS32	O
Release	O
5	O
Warrior-P	O
P5600	O
2013	O
?	O
</s>
<s>
A	O
number	O
of	O
companies	O
licensed	O
the	O
MIPS	B-Device
architecture	I-Device
and	O
developed	O
their	O
own	O
processors	O
.	O
</s>
<s>
MIPS	B-Device
version	O
Licensee	O
Processor	B-General_Concept
Features	O
Year	O
Process	O
(	O
nm	O
)	O
Frequency	O
(	O
MHz	O
)	O
Transistors	O
(	O
millions	O
)	O
Die	O
size	O
(	O
mm2	O
)	O
Pin	O
count	O
Power	O
(	O
W	O
)	O
Voltage	O
(	O
V	O
)	O
D	O
.	O
cache	O
(	O
KB	O
)	O
I	O
.	O
cache	O
(	O
KB	O
)	O
MMU	B-General_Concept
L2	O
cache	O
L3	O
cache	O
MIPS	B-Device
I	O
Lexra	O
LX4080	O
,	O
LX4180	O
,	O
LX4280	O
,	O
LX5280	O
,	O
LX8000	O
MIPS	B-Device
II	O
НИИСИ	O
РАН	O
KOMDIV-32	B-General_Concept
MIPS	B-Device
III	O
Sony	O
Computer	O
Entertainment	O
+	O
Toshiba	O
Emotion	B-Architecture
Engine	I-Architecture
НИИСИ	O
РАН	O
KOMDIV-64	B-General_Concept
MIPS32	O
Alchemy	B-Device
Semiconductor	O
Au1	B-Device
Broadcom	O
BMIPS3000	O
BMIPS4000	O
BMIPS5000	O
1300	O
BCM53001	O
65	O
400	O
32	O
32	O
BCM1255	O
Ingenic	B-Device
Semiconductor	I-Device
XBurst	B-Device
1	I-Device
single	O
issue	O
,	O
8-stage	O
pipeline	O
2005	O
180	O
,	O
130	O
,	O
64	O
,	O
40	O
240	O
0.15	O
1.8	O
16	O
16	O
yes	O
none	O
none	O
MIPS64	O
SiByte	O
SB1	O
Broadcom	O
BCM1125H	O
400-800	O
4w	O
@	O
400	O
MHz	O
32	O
32	O
yes	O
256	O
KB	O
BCM1255	O
Dual-core	O
,	O
DDR2	O
,	O
4×	O
Gigabit	O
LAN	O
800-1200	O
13	O
W	O
@	O
1	O
GHz	O
32	O
32	O
yes	O
512	O
KB	O
Cavium	O
Octeon	O
:	O
CN30xx	O
,	O
CN31xx	O
,	O
CN36xx	O
,	O
CN38xx	O
2006	O
Octeon	O
Plus	O
:	O
CN5xxx	O
2007	O
Octeon	O
II	O
:	O
CN6xxx	O
2009	O
Octeon	O
III	O
:	O
CN7xxx	O
2012	O
Ingenic	B-Device
Semiconductor	I-Device
XBurst	B-Device
2	I-Device
dual-issue/dual	O
-threaded	O
2013	O
40	O
240	O
0.15	O
1.8	O
16	O
16	O
yes	O
none	O
none	O
NEC	O
VR4305	O
VR4310	O
NXP	O
Semiconductors	O
?	O
</s>
<s>
CAS	O
:	O
ICT	O
none	B-Language
yet	I-Language
?	O
</s>
