<s>
This	O
article	O
provides	O
a	O
list	O
of	O
motherboard	B-Device
chipsets	B-Device
made	O
by	O
Intel	O
,	O
divided	O
into	O
three	O
main	O
categories	O
:	O
those	O
that	O
use	O
the	O
PCI	B-Protocol
bus	I-Protocol
for	O
interconnection	O
(	O
the	O
4xx	O
series	O
)	O
,	O
those	O
that	O
connect	O
using	O
specialized	O
"	O
hub	O
links	O
"	O
(	O
the	O
8xx	O
series	O
)	O
,	O
and	O
those	O
that	O
connect	O
using	O
PCI	B-Protocol
Express	O
(	O
the	O
9xx	O
series	O
)	O
.	O
</s>
<s>
The	O
chipsets	B-Device
are	O
listed	O
in	O
chronological	O
order	O
.	O
</s>
<s>
An	O
earlier	O
chipset	B-Device
support	O
for	O
Intel	O
8085	O
microprocessor	O
can	O
be	O
found	O
at	O
MCS-85	O
family	O
section	O
.	O
</s>
<s>
Early	O
IBM	B-Device
XT-compatible	I-Device
mainboards	B-Device
did	O
not	O
have	O
a	O
chipset	B-Device
yet	O
,	O
but	O
relied	O
instead	O
on	O
a	O
collection	O
of	O
discrete	O
TTL	B-General_Concept
chips	O
by	O
Intel	O
:	O
</s>
<s>
To	O
integrate	O
the	O
functions	O
needed	O
on	O
a	O
mainboard	B-Device
into	O
a	O
smaller	O
amount	O
of	O
ICs	O
,	O
Intel	O
licensed	O
the	O
ZyMOS	O
POACH	O
chipset	B-Device
for	O
its	O
Intel	B-General_Concept
80286	I-General_Concept
and	O
Intel	O
80386SX	O
processors	O
(	O
the	O
82230/82231	O
High	O
Integration	O
AT-Compatible	O
Chip	B-Device
Set	I-Device
)	O
.	O
</s>
<s>
The	O
82230	O
covers	O
this	O
combination	O
of	O
chips	O
:	O
82C284	O
clock	O
,	O
82288	O
bus	O
controller	O
,	O
and	O
dual	O
8259A	B-Device
interrupt	B-Architecture
controllers	I-Architecture
among	O
with	O
other	O
components	O
.	O
</s>
<s>
The	O
82231	O
covers	O
this	O
combination	O
of	O
chips	O
:	O
8254	B-Device
interrupt	O
timer	O
,	O
74LS612	O
memory	O
mapper	O
and	O
dual	O
8237A	B-Device
DMA	B-General_Concept
controller	I-General_Concept
among	O
with	O
other	O
components	O
.	O
</s>
<s>
This	O
chipset	B-Device
can	O
be	O
used	O
with	O
an	O
82335	O
High-integration	O
Interface	O
Device	O
to	O
provide	O
support	O
for	O
the	O
Intel	O
386SX	O
.	O
</s>
<s>
List	O
of	O
early	O
Intel	B-Device
chipset	I-Device
includes	O
:	O
</s>
<s>
82091AA	O
EISA/ISA	O
-	O
Advanced	O
Integrated	O
Peripheral	O
(	O
AIP	O
)	O
,	O
includes	O
:	O
floppy	B-Device
disk	I-Device
controller	I-Device
,	O
2×	O
UARTs	O
,	O
parallel	B-Device
port	I-Device
,	O
IDE	O
controller	O
,	O
oscillator	O
,	O
etc	O
.	O
</s>
<s>
82310	O
MCA	B-Device
family	O
chipset	B-Device
-	O
announced	O
in	O
April	O
1988	O
.	O
</s>
<s>
This	O
chipset	B-Device
also	O
supports	O
the	O
80386SX	O
based	O
machines	O
as	O
well	O
.	O
</s>
<s>
82350	O
EISA	B-Device
-	O
announced	O
in	O
September	O
1988	O
.	O
</s>
<s>
82311	O
MCA	B-Device
-	O
announced	O
in	O
November	O
1988	O
.	O
</s>
<s>
Includes	O
:	O
82303	O
and	O
82304	O
Local	O
I/O	O
Channel	O
Support	O
Chips	O
,	O
82307	O
DMA	O
Controller/Central	O
Arbiter	O
,	O
82308	O
Micro	B-Device
Channel	I-Device
Bus	O
Controller	O
,	O
82309	O
Address	O
Bus	O
Controller	O
,	O
82706	O
VGA	O
Graphics	O
Controller	O
,	O
82077	O
Floppy	B-Device
Disk	I-Device
Controller	I-Device
.	O
</s>
<s>
82320	O
MCA	B-Device
-	O
announced	O
in	O
April	O
1989	O
.	O
</s>
<s>
82340SX	O
PC	O
AT	O
-	O
announced	O
in	O
January	O
1990	O
,	O
it	O
is	O
the	O
Topcat	O
chipset	B-Device
licensed	O
from	O
VLSI	O
.	O
</s>
<s>
82340DX	O
PC	O
AT	O
-	O
announced	O
in	O
January	O
1990	O
,	O
it	O
is	O
the	O
Topcat	O
chipset	B-Device
licensed	O
from	O
VLSI	O
.	O
</s>
<s>
It	O
was	O
a	O
chipset	B-Device
for	O
the	O
mobile	O
80386SL	O
and	O
80486SL	B-Device
processors	O
.	O
</s>
<s>
It	O
integrated	O
DMA	B-General_Concept
controller	I-General_Concept
,	O
an	O
interrupt	B-Architecture
controller	I-Architecture
PIC	B-Architecture
,	O
serial	O
and	O
parallel	B-Device
ports	I-Device
,	O
and	O
power-management	O
logic	O
for	O
the	O
processor	O
.	O
</s>
<s>
82350DT	O
EISA	B-Device
-	O
announced	O
in	O
April	O
1991	O
.	O
</s>
<s>
82380	O
-	O
High	O
Performance	O
32-Bit	O
DMA	B-General_Concept
Controller	I-General_Concept
with	O
Integrated	O
System	O
Support	O
Peripherals	O
.	O
</s>
<s>
This	O
chipset	B-Device
has	O
20-level	O
programmable	B-Architecture
interrupt	I-Architecture
controller	I-Architecture
a	O
superset	O
of	O
Intel	O
's	O
82C59	O
PIC	B-Architecture
.	O
</s>
<s>
It	O
also	O
has	O
four	O
(	O
x4	O
)	O
16-bit	O
programmable	O
internal	O
timers	O
which	O
its	O
superset	O
Intel	O
's	O
82C54	O
PIT	B-Device
.	O
</s>
<s>
It	O
also	O
has	O
built-in	O
DRAM	B-General_Concept
refresh	I-General_Concept
controller	O
as	O
well	O
.	O
</s>
<s>
This	O
chipset	B-Device
was	O
introduced	O
in	O
February	O
1987	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
North	O
Bridge	O
sSpec	O
Number	O
South	O
Bridge	O
Release	O
Date	O
Processors	O
FSB	B-Architecture
SMP	B-Operating_System
Memory	O
types	O
Max	O
.	O
</s>
<s>
While	O
not	O
an	O
actual	O
Intel	B-Device
chipset	I-Device
bug	O
,	O
the	O
Mercury	O
and	O
Neptune	O
chipsets	B-Device
could	O
be	O
found	O
paired	O
with	O
RZ1000	O
and	O
CMD640	B-Error_Name
IDE	O
controllers	O
with	O
data	O
corruption	O
bugs	O
.	O
</s>
<s>
L2	O
caches	O
are	O
direct-mapped	O
with	O
SRAM	B-Architecture
tag	O
RAM	O
,	O
write-back	O
for	O
430FX	O
,	O
HX	O
,	O
VX	O
,	O
and	O
TX	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
Part	O
Numbers	O
sSpec	O
Number	O
South	O
Bridge	O
Release	O
Date	O
Processors	O
FSB	B-Architecture
SMP	B-Operating_System
Memory	O
types	O
Max	O
.	O
</s>
<s>
cacheable	O
Parity/ECC	O
L2	O
Cache	O
Type	O
PCI	B-Protocol
support	O
AGP	B-Architecture
support430LX	O
MercuryIntel	O
430LX	O
(	O
"	O
Mercury	O
"	O
)	O
,	O
PC	O
Guide	O
,	O
accessed	O
August	O
20	O
,	O
2007	O
.	O
</s>
<s>
SZ942	O
(	O
LBX	O
)	O
SIO	O
(	O
ISA	B-Architecture
)	O
PCEB/ESC	O
(	O
EISA	B-Device
)	O
March	O
1993	O
P60/66	O
60/66	O
MHz	O
FPM	O
192	O
MB	O
192	O
MB	O
rowspan	O
=	O
"	O
2	O
"	O
Async	O
.	O
</s>
<s>
SZ899	O
(	O
LBX	O
)	O
SIO	O
(	O
ISA	B-Architecture
)	O
SIO.A	O
(	O
DP	O
ISA	B-Architecture
)	O
PCEB/ESC	O
(	O
EISA	B-Device
)	O
March	O
1994	O
P75+	O
50/60/66	O
MHz	O
512	O
MB	O
512	O
MB430FX	O
TritonIntel	O
430FX	O
(	O
"	O
Triton	O
"	O
)	O
,	O
PC	O
Guide	O
,	O
accessed	O
August	O
20	O
,	O
2007.Summary	O
of	O
P5	O
chipsets	B-Device
,	O
comp.sys.intel	O
,	O
September	O
1996	O
.	O
</s>
<s>
SZ999	O
PIIX	B-Device
January	O
1995	O
rowspan	O
=	O
"	O
2	O
"	O
FPM/EDO	O
128	O
MB	O
64	O
MB	O
rowspan	O
=	O
"	O
2	O
"	O
Async	O
.	O
</s>
<s>
SU069	O
(	O
B0	O
)	O
MPIIX	O
October	O
1995430HX	O
Triton	O
IIIntel	O
430HX	B-Device
(	O
"	O
Triton	B-Device
II	I-Device
"	O
)	O
,	O
PC	O
Guide	O
,	O
accessed	O
August	O
20	O
,	O
2007	O
.	O
</s>
<s>
2.1430VX	O
Triton	O
IIIntel	O
430VX	O
(	O
"	O
Triton	B-Device
II	I-Device
"	O
,	O
a.k.a.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
Bridge	O
Release	O
Date	O
Processors	O
FSB	B-Architecture
SMP	B-Operating_System
Memory	O
Parity/ECC	O
PCI	B-Protocol
support	O
AGP	B-Architecture
support	O
Type	O
Max	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
bridge	O
Release	O
date	O
Processors	O
FSB	B-Architecture
SMP	B-Operating_System
Memory	O
types	O
Max	O
.	O
</s>
<s>
memory	O
Memory	O
banks	O
Parity	B-Error_Name
or	O
ECC	B-Error_Name
PCI	B-Protocol
Ext	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
bridge	O
Release	O
date	O
Processors	O
FSB	B-Architecture
SMP	B-Operating_System
Memory	O
types	O
Max	O
.	O
</s>
<s>
memory	O
Memory	O
banks	O
Parity	B-Error_Name
or	O
ECC	B-Error_Name
PCI	B-Protocol
Ext	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
bridge	O
Release	O
date	O
Socket	B-General_Concept
Processor	O
brands	O
FSB[ 	O
MT/s	O
]	O
SMP	B-Operating_System
Memory	O
types	O
Memory	O
Channels	O
Max	O
.	O
</s>
<s>
Similar	O
to	O
E7205	O
,	O
but	O
adds	O
support	O
for	O
800MHz	O
bus	O
,	O
DDR	O
at	O
400MHz	O
,	O
Communication	B-Device
Streaming	I-Device
Architecture	I-Device
(	O
CSA	O
)	O
,	O
Serial	O
ATA	B-Protocol
(	O
with	O
RAID	B-Architecture
in	O
certain	O
configurations	O
)	O
and	O
Performance	B-Device
Acceleration	I-Device
Technology	I-Device
(	O
PAT	O
)	O
,	O
a	O
mode	O
purported	O
to	O
cut	O
down	O
memory	O
latency	O
.	O
</s>
<s>
SMP	B-Operating_System
capability	O
exists	O
only	O
on	O
Xeon-based	O
(	O
socket	B-Device
604	I-Device
)	O
motherboards	B-Device
using	O
the	O
875P	O
chipset	B-Device
.	O
</s>
<s>
FSB	B-Architecture
is	O
rated	O
at	O
on	O
these	O
motherboards	B-Device
.	O
</s>
<s>
Also	O
lacks	O
ECC	B-Error_Name
Memory	O
support	O
.	O
</s>
<s>
865GV	O
-	O
865G	O
without	O
external	O
AGP	B-Architecture
slot	I-Architecture
.	O
</s>
<s>
One	O
PCI-X	O
slot	O
can	O
be	O
bridged	O
to	O
the	O
PCI-e	O
×8	O
using	O
the	O
Intel®	O
6702PXH	O
64-bit	O
PCI	B-Protocol
Hub	O
.	O
</s>
<s>
One	O
PCI-X	O
slot	O
can	O
be	O
bridged	O
to	O
the	O
PCI-e	O
×8	O
using	O
Intel®	O
6700PXH	O
64-bit	O
PCI	B-Protocol
Hub/Intel	O
®	O
6702PXH	O
64-bit	O
PCI	B-Protocol
Hub	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
bridge	O
Release	O
date	O
Processors	O
FSB	B-Architecture
SMP	B-Operating_System
Memory	O
types	O
Max	O
.	O
</s>
<s>
All	O
Chipsets	B-Device
listed	O
in	O
the	O
table	O
below	O
:	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
Part	O
numberssSpec	O
Number	O
South	O
Bridge	O
Release	O
Date	O
Supported	O
Processors	O
FSB	B-Architecture
 [ MT/s ] 	O
Memory	O
Parity	B-Error_Name
/	O
ECC	B-Error_Name
Graphics	O
TDP	B-General_Concept
 [ W ] 	O
types	O
max	O
.	O
</s>
<s>
Replaces	O
AGP	B-Architecture
and	O
CSA	O
with	O
PCI	B-Protocol
Express	O
,	O
and	O
also	O
supports	O
"	O
Matrix	B-Application
RAID	I-Application
"	O
,	O
a	O
RAID	B-Architecture
mode	O
designed	O
to	O
allow	O
the	O
usage	O
of	O
RAID	B-Architecture
levels	O
0	O
and	O
1	O
simultaneously	O
with	O
two	O
hard	O
drives	O
.	O
</s>
<s>
Supports	O
another	O
PAT-like	O
mode	O
and	O
ECC	B-Error_Name
memory	O
,	O
and	O
exclusively	O
uses	O
DDR-II	O
RAM	O
.	O
</s>
<s>
Update	O
on	O
915P	O
,	O
with	O
support	O
for	O
Serial	O
ATA	B-Protocol
II	O
,	O
RAID	B-Architecture
mode	O
5	O
,	O
an	O
improved	O
memory	O
controller	O
with	O
support	O
for	O
DDR-II	O
at	O
667MHz	O
and	O
additional	O
PCI	B-Protocol
Express	O
lanes	O
.	O
</s>
<s>
Formal	O
dual-core	O
support	O
was	O
added	O
to	O
this	O
chipset	B-Device
.	O
</s>
<s>
Update	O
for	O
925X	O
,	O
with	O
additional	O
features	O
of	O
"	O
Lakeport	O
"	O
(	O
e.g.	O
,	O
PAT	O
features	O
and	O
ECC	B-Error_Name
memory	O
)	O
,	O
and	O
uses	O
DDR2	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
Bridge	O
Release	O
Date	O
Supported	O
Processors	O
FSB	B-Architecture
Memory	O
Types	O
Max	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
bridge	O
Release	O
date	O
Processors	O
supported	O
(	O
official	O
)	O
FSB	B-Architecture
 [ MT/s ] 	O
Memory	O
Graphics	O
TDP	B-General_Concept
 [ W ] 	O
types	O
max	O
.	O
</s>
<s>
166	O
MHz	O
7943GML	O
82943GML	O
(	O
GMCH	O
)	O
Celeron	O
M	O
,	O
Core	B-Device
Solo	I-Device
,	O
Pentium	B-Device
Dual-Core	I-Device
Max	O
.	O
</s>
<s>
200	O
MHz	O
945GSE	O
82945GSE	O
(	O
GMCH	O
)	O
SLB2R	O
Q1'06	O
Intel	B-Device
Atom	I-Device
533/667	O
Max	O
.	O
</s>
<s>
166	O
MHz	O
6	O
945GMS	O
82945GMS	O
(	O
GMCH	O
)	O
SL8TC	O
January	O
2006	O
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Core	B-Device
Duo	I-Device
,	O
Pentium	B-Device
Dual-Core	I-Device
,	O
Core	B-Device
Solo	I-Device
,	O
Celeron	O
M	O
7	O
945GM/E	O
82945GM/E	O
(	O
GMCH	O
)	O
SL8Z2ICH7-M/ICH7	O
-M	O
DH	O
DDR2	O
400/533/667	O
4	O
Max	O
.	O
</s>
<s>
All	O
Core	B-Device
2	I-Device
Duo	I-Device
chipsets	B-Device
support	O
the	O
Pentium	B-Device
Dual-Core	I-Device
and	O
Celeron	O
processors	O
based	O
on	O
the	O
Core	B-Device
architecture	I-Device
.	O
</s>
<s>
Support	O
for	O
all	O
NetBurst	B-Device
based	O
processors	O
was	O
officially	O
dropped	O
starting	O
with	O
the	O
Bearlake	O
chipset	B-Device
family	O
.	O
</s>
<s>
However	O
,	O
some	O
motherboards	B-Device
still	O
support	O
the	O
older	O
processors	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
Part	O
numberssSpec	O
Number	O
South	O
Bridge	O
Release	O
Date	O
Processors	O
Lithography	O
Intel	O
VT-d	O
support	O
FSB	B-Architecture
 [ MT/s ] 	O
Memory	O
Parity/ECC	O
PCIe	O
iGraphics	O
types	O
max	O
.	O
</s>
<s>
SLASK	O
(	O
B0	O
)	O
ICH7	O
August	O
2007	O
Pentium	B-Device
Dual-Core	I-Device
,	O
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Core	B-Device
2	I-Device
Quad	O
90	O
nm	O
800/1066/1333	O
(	O
P45	O
unofficial	O
1600	O
)	O
DDR2	O
667/800	O
4	O
GB	O
rowspan	O
=	O
"	O
15	O
"	O
1×16	O
rev	O
.	O
</s>
<s>
SLGQ3	O
ICH7	O
September	O
2008	O
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Core	B-Device
2	I-Device
Quad	O
65	O
nm	O
rowspan	O
=	O
"	O
7	O
"	O
DDR2	O
667/800DDR3	O
800/1066	O
4	O
GB8	O
GB	O
GMA	O
X4500B43	O
Eaglelake	O
(	O
B	O
)	O
82B43	O
(	O
GMCH	O
)	O
SLGL7	O
(	O
A3	O
)	O
ICH10D	O
December	O
2008	O
16	O
GB	O
1×16	O
rev	O
.	O
</s>
<s>
Intel	O
's	O
X38	O
Express	O
Chipset	B-Device
Is	O
Ready	O
,	O
Softpedia	O
News	O
,	O
August	O
16	O
,	O
2007	O
.	O
</s>
<s>
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Core	B-Device
2	I-Device
Quad	O
,	O
Core	B-Device
2	I-Device
Extreme	O
90	O
nm	O
DDR3	O
800/1066/1333DDR2	O
667/800/1066	O
rowspan	O
=	O
"	O
2	O
"	O
2×16	O
rev	O
.	O
</s>
<s>
Operational	O
configuration	O
is	O
4	O
ranks	O
-	O
2×2GB	O
dual	O
rank	O
modules	O
or	O
4×1GB	O
single	O
rank	O
modules	O
-	O
depends	O
on	O
number	O
of	O
motherboard	B-Device
DDR2	O
slots	O
.	O
</s>
<s>
Update	O
on	O
945P	O
,	O
no	O
native	O
PATA	B-Protocol
support	O
,	O
improved	O
memory	O
controller	O
with	O
support	O
for	O
DDR2	O
memory	O
up	O
to	O
800MHz	O
and	O
official	O
Core	B-Device
2	I-Device
Duo	I-Device
support	O
.	O
</s>
<s>
Update	O
of	O
955	O
,	O
with	O
support	O
for	O
ATI	O
Crossfire	O
Dual	O
Graphics	O
systems	O
and	O
65nm	O
processors	O
,	O
including	O
Core	B-Device
2	I-Device
Duo	I-Device
.	O
</s>
<s>
The	O
P35	O
chipset	B-Device
provides	O
updated	O
support	O
for	O
the	O
new	O
Core	B-Device
2	I-Device
Duo	I-Device
E6550	O
,	O
E6750	O
,	O
E6800	O
,	O
and	O
E6850	O
.	O
</s>
<s>
Processors	O
with	O
a	O
number	O
ending	O
in	O
"	O
50	O
"	O
have	O
a	O
1333	O
MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
Support	O
for	O
all	O
NetBurst	B-Device
based	O
processors	O
is	O
dropped	O
with	O
this	O
chipset	B-Device
.	O
</s>
<s>
Operational	O
configuration	O
is	O
4	O
ranks	O
-	O
2×	O
2	O
GB	O
dual	O
rank	O
modules	O
or	O
4	O
×	O
1	O
GB	O
single	O
rank	O
modules	O
-	O
depends	O
on	O
number	O
of	O
motherboard	B-Device
DDR2	O
slots	O
.	O
</s>
<s>
It	O
supports	O
a	O
1333MT/s	O
FSB	B-Architecture
with	O
Core2	O
Duo	O
processors	O
,	O
but	O
Core2	O
Quad	O
processors	O
are	O
only	O
supported	O
up	O
to	O
1066MT/s	O
.	O
</s>
<s>
 [ 1 ] 	O
The	O
975X	O
chipset	B-Device
supports	O
only	O
×16	O
PCI	B-Protocol
Express	O
(	O
electrically	O
)	O
in	O
the	O
top	O
slot	O
when	O
the	O
slot	O
below	O
it	O
is	O
unpopulated	O
.	O
</s>
<s>
Otherwise	O
it	O
and	O
the	O
lower	O
slot	O
(	O
both	O
attached	O
to	O
the	O
Memory	B-Device
Controller	I-Device
Hub	I-Device
)	O
operate	O
at	O
×8	O
electrically	O
.	O
</s>
<s>
 [ 2 ] 	O
Officially	O
975X	O
supports	O
a	O
maximum	O
of	O
1066MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
Unofficially	O
,	O
third-party	O
motherboards	B-Device
(	O
Asus	O
,	O
Gigabyte	O
)	O
support	O
certain	O
1333FSB	O
45nm	O
Core2	O
processors	O
,	O
usually	O
with	O
later	O
BIOS	O
updates	O
.	O
</s>
<s>
 [ 3 ] 	O
The	O
975X	O
chipset	B-Device
technical	O
specification	O
shows	O
only	O
DDR2-533/667	O
memory	O
support	O
.	O
</s>
<s>
 [ 4 ] 	O
VT-d	O
is	O
inherently	O
supported	O
on	O
these	O
chipsets	B-Device
,	O
but	O
may	O
not	O
be	O
enabled	O
by	O
individual	O
OEMs	O
.	O
</s>
<s>
Always	O
read	O
the	O
motherboard	B-Device
manual	O
and	O
check	O
for	O
BIOS	O
updates	O
.	O
</s>
<s>
Note	O
that	O
VT-d	O
is	O
a	O
chipset	B-Device
Memory	B-Device
Controller	I-Device
Hub	I-Device
technology	O
,	O
not	O
a	O
processor	O
feature	O
,	O
but	O
this	O
is	O
complicated	O
by	O
later	O
processor	O
generations	O
(	O
Core	O
i3/i5/i7	O
)	O
moving	O
the	O
MCH	O
from	O
the	O
motherboard	B-Device
to	O
the	O
processor	O
package	O
,	O
making	O
only	O
certain	O
I	O
series	O
CPUs	B-Device
support	O
VT-d	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
name	O
Part	O
numbers	O
sSpec	O
Number	O
South	O
bridge	O
Release	O
date	O
Lithography	O
Processors	O
supported	O
(	O
official	O
)	O
FSB	B-Architecture
 [ MT/s ] 	O
Memory	O
Graphics	O
TDP	B-General_Concept
 [ W ] 	O
types	O
.	O
</s>
<s>
nm	O
Celeron	O
M	O
,	O
Pentium	B-Device
Dual-Core	I-Device
533	O
DDR2	O
533/667	O
3/51	O
Integrated	O
GMA	O
X3100	O
Max	O
.	O
</s>
<s>
400	O
MHz	O
13.5	O
GM965	O
82965GM	O
(	O
GMCH	O
)	O
SLA9F	O
(	O
C0	O
)	O
Core	B-Device
2	I-Device
Duo	I-Device
533/667/800	O
4/82	O
Max	O
.	O
</s>
<s>
SLGGM	O
(	O
A1	O
)	O
ICH9-M	O
Sep	O
2008	O
65	O
nm	O
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Celeron	O
,	O
Celeron	O
M	O
,	O
Pentium	B-Device
Dual-Core	I-Device
667/800	O
DDR2	O
667/800	O
,	O
DDR3	O
800/1066	O
4/82	O
Integrated	O
GMA	O
X4500MHD	O
Max	O
.	O
</s>
<s>
400	O
MHz	O
12	O
GS40	O
82GS40	O
(	O
GMCH	O
)	O
SLGT8	O
(	O
B3	O
)	O
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Celeron	O
,	O
Celeron	O
M	O
?,	O
Pentium	B-Device
Dual-Core	I-Device
4	O
GS45	O
82GS45	O
(	O
GMCH	O
)	O
(	O
For	O
CULV	O
)	O
SLB92	O
(	O
B3	O
)	O
Core	B-Device
2	I-Device
Solo	O
,	O
Core	B-Device
2	I-Device
Duo	I-Device
,	O
Core	B-Device
2	I-Device
Extreme	O
,	O
Celeron	O
M	O
800/1066	O
8	O
Max	O
.	O
</s>
<s>
1	O
Unofficially	O
this	O
chipset	B-Device
support	O
5GB	O
.	O
</s>
<s>
Unofficially	O
many	O
laptops	O
with	O
this	O
chipset	B-Device
support	O
8GB	O
.	O
</s>
<s>
The	O
Nehalem	B-Device
microarchitecture	I-Device
moves	O
the	O
memory	O
controller	O
into	O
the	O
processor	O
.	O
</s>
<s>
For	O
high-end	O
Nehalem	B-Device
processors	O
,	O
the	O
X58	B-Device
IOH	I-Device
acts	O
as	O
a	O
bridge	O
from	O
the	O
QPI	B-Architecture
to	O
PCI	B-Protocol
Express	O
peripherals	O
and	O
DMI	B-Architecture
to	O
the	O
ICH10	O
southbridge	B-Device
.	O
</s>
<s>
For	O
mainstream	O
and	O
lower-end	O
Nehalem	B-Device
processors	O
,	O
the	O
integrated	O
memory	O
controller	O
(	O
IMC	O
)	O
is	O
an	O
entire	O
northbridge	B-Device
(	O
some	O
even	O
having	O
GPUs	O
)	O
,	O
and	O
the	O
PCH	O
(	O
Platform	B-Device
Controller	I-Device
Hub	I-Device
)	O
acts	O
as	O
a	O
southbridge	B-Device
.	O
</s>
<s>
Not	O
listed	O
below	O
is	O
the	O
3450	O
chipset	B-Device
(	O
see	O
Xeon	B-Architecture
chipsets	I-Architecture
)	O
which	O
is	O
compatible	O
with	O
Nehalem	B-Device
mainstream	O
and	O
high-end	O
processors	O
but	O
does	O
not	O
claim	O
core	O
iX-compatibility	O
.	O
</s>
<s>
With	O
either	O
a	O
Core	B-Device
i5	I-Device
or	O
i3	B-Device
processor	O
,	O
the	O
3400-series	O
chipsets	B-Device
enable	O
the	O
ECC	B-Error_Name
functionality	O
of	O
unbuffered	B-General_Concept
ECC	B-Error_Name
memory	O
.	O
</s>
<s>
Otherwise	O
these	O
chipsets	B-Device
do	O
not	O
enable	O
unbuffered	B-General_Concept
ECC	B-Error_Name
functionality	O
.	O
</s>
<s>
The	O
Cougar	O
Point	O
Intel	O
6	O
series	O
chipsets	B-Device
with	O
stepping	O
B2	O
were	O
recalled	O
due	O
to	O
a	O
hardware	O
bug	O
that	O
causes	O
their	O
3Gbit/s	O
Serial	O
ATA	B-Protocol
to	O
degrade	O
over	O
time	O
until	O
they	O
become	O
unusable	O
.	O
</s>
<s>
Stepping	O
B3	O
of	O
the	O
Intel	O
6	O
series	O
chipsets	B-Device
will	O
have	O
the	O
fix	O
for	O
this	O
.	O
</s>
<s>
The	O
Z68	O
chipset	B-Device
which	O
supports	O
CPU	B-Device
overclocking	O
and	O
use	O
of	O
the	O
integrated	O
graphics	O
does	O
not	O
have	O
this	O
hardware	O
bug	O
,	O
however	O
all	O
other	O
ones	O
with	O
B2	O
did	O
.	O
</s>
<s>
The	O
Z68	O
also	O
added	O
support	O
for	O
transparently	O
caching	O
hard	O
disk	O
data	O
on	O
to	O
solid-state	B-Device
drives	I-Device
(	O
up	O
to	O
64GB	O
)	O
,	O
a	O
technology	O
called	O
Smart	B-Device
Response	I-Device
Technology	I-Device
.	O
</s>
<s>
Chipsets	B-Device
supporting	O
LGA	B-Device
1156	I-Device
CPUs	B-Device
(	O
Lynnfield	O
and	O
Clarkdale	O
)	O
.	O
</s>
<s>
Chipsets	B-Device
supporting	O
LGA	B-Device
1155	I-Device
CPUs	B-Device
(	O
Sandy	O
Bridge	O
and	O
Ivy	O
Bridge	O
)	O
.	O
</s>
<s>
The	O
PCIe	O
2.0	O
lanes	O
from	O
the	O
PCH	O
ran	O
at	O
5	O
GT/s	O
in	O
this	O
series	O
,	O
unlike	O
in	O
the	O
previous	O
LGA	B-Device
1156	I-Device
chips	O
.	O
</s>
<s>
Sandy	O
Bridge	O
CPUs	B-Device
provide	O
16	O
PCIe	O
2.0	O
lanes	O
for	O
direct	O
GPU	O
connectivity	O
.	O
</s>
<s>
Ivy	O
Bridge	O
CPUs	B-Device
provide	O
16	O
PCIe	O
3.0	O
lanes	O
for	O
direct	O
GPU	O
connectivity	O
and	O
additional	O
4	O
PCIe	O
2.0	O
lanes	O
.	O
</s>
<s>
Chipsets	B-Device
that	O
support	O
LGA	B-Device
1150	I-Device
CPUs	B-Device
are	O
listed	O
below	O
.	O
</s>
<s>
Haswell	B-Device
and	O
Haswell	B-Device
Refresh	O
CPUs	B-Device
are	O
supported	O
by	O
all	O
listed	O
chipsets	B-Device
;	O
however	O
,	O
a	O
BIOS	O
update	O
is	O
usually	O
required	O
for	O
8-Series	O
Lynx	O
Point	O
motherboards	B-Device
to	O
support	O
Haswell	B-Device
Refresh	O
CPUs	B-Device
.	O
</s>
<s>
Broadwell	B-General_Concept
CPUs	B-Device
are	O
supported	O
only	O
by	O
9-Series	O
chipsets	B-Device
,	O
which	O
are	O
usually	O
referred	O
to	O
as	O
Wildcat	O
Point	O
.	O
</s>
<s>
The	O
C1	O
stepping	O
of	O
the	O
Lynx	O
Point	O
chipset	B-Device
contains	O
a	O
bug	O
a	O
system	O
could	O
lose	O
connectivity	O
with	O
USB	B-Protocol
devices	I-Protocol
plugged	O
into	O
USB3.0	O
ports	O
provided	O
by	O
the	O
chipset	B-Device
if	O
the	O
system	O
enters	O
the	O
S3	O
sleep	O
mode	O
.	O
</s>
<s>
Single	O
socket	B-General_Concept
chipsets	B-Device
supporting	O
LGA	B-Device
1366	I-Device
,	O
LGA	B-Device
2011	I-Device
,	O
and	O
LGA	O
2011-v3	O
CPUs	B-Device
.	O
</s>
<s>
Please	O
consult	O
List	B-Architecture
of	I-Architecture
Intel	I-Architecture
Xeon	I-Architecture
chipsets	I-Architecture
for	O
further	O
,	O
multi-socket	O
,	O
chipsets	B-Device
for	O
these	O
sockets	O
.	O
</s>
<s>
1	O
X58	B-Device
South	O
Bridge	O
is	O
ICH10/ICH10R	O
.	O
</s>
<s>
2	O
X58	B-Device
TDP	B-General_Concept
includes	O
the	O
X58	B-Device
IOH	I-Device
TDP	B-General_Concept
in	O
addition	O
to	O
the	O
ICH10/ICH10R	O
TDP	B-General_Concept
.	O
</s>
<s>
Sandy	O
Bridge	O
CPUs	B-Device
will	O
provide	O
up	O
to	O
40	O
PCIe	O
3.0	O
lanes	O
for	O
direct	O
GPU	O
connectivity	O
and	O
additional	O
4	O
PCIe	O
2.0	O
lanes	O
.	O
</s>
<s>
NOTE	O
:	O
This	O
reference	O
number	O
4	O
is	O
on	O
X79	O
,	O
which	O
is	O
a	O
Sandy	O
bridge	O
-E	O
,	O
not	O
Sandy	O
Bridge	O
,	O
and	O
PCIe3.0	O
only	O
is	O
enabled	O
when	O
an	O
Ivy	O
Bridge-E	O
CPU	B-Device
or	O
Xeon	B-Device
E-5	O
series	O
is	O
used	O
.	O
</s>
<s>
4	O
For	O
Haswell	B-Device
enthusiast	O
desktop	O
platform	O
.	O
</s>
<s>
Haswell	B-Device
CPUs	B-Device
will	O
provide	O
up	O
to	O
40	O
PCIe	O
3.0	O
lanes	O
for	O
direct	O
GPU	O
connectivity	O
and	O
additional	O
4	O
PCIe	O
2.0	O
lanes	O
.	O
</s>
<s>
Chipsets	B-Device
supporting	O
LGA	B-Device
2066	I-Device
socket	B-General_Concept
for	O
Skylake-X	B-Architecture
processors	O
and	O
Kaby	B-Device
Lake-X	I-Device
processors	O
.	O
</s>
<s>
The	O
C621	O
Chipset	B-Device
also	O
supports	O
FCLGA3647	O
socket	B-General_Concept
for	O
Skylake-SP	O
as	O
well	O
as	O
Cascade	O
Lake-W	O
and	O
Cascade	O
Lake-SP	O
processors	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
sSpec	O
Number	O
Part	O
numbers	O
Release	O
Date	O
Bus	O
Interface	O
Link	O
Speed	O
PCI	B-Protocol
Express	O
lanes	O
SATA	O
SATAe	B-Architecture
PCIe	O
M.2	B-Protocol
QAT	B-Device
USB	B-Protocol
ports	I-Protocol
TDP	B-General_Concept
6	O
Gbit/s	O
v3.0	O
v2.0	O
X299	O
Basin	O
Falls	O
SR2Z2(A0 )	O
GL82X299	O
May	O
30	O
,	O
2017	O
DMI	B-Architecture
3.0	I-Architecture
32	O
GB/s	O
16	O
PCIe	O
3.0	O
(	O
for	O
i5	O
)	O
,	O
28-44	O
PCIe	O
3.0	O
(	O
i7	O
)	O
,	O
48	O
PCIe	O
3.0	O
(	O
i9	O
)	O
No	O
Up	O
to	O
10	O
Up	O
to	O
14	O
6	O
W	O
C422Kaby	O
LakeSR2WG(A0 )	O
GL82C422	O
July	O
11	O
,	O
201724	O
PCIe	O
3.0	O
?	O
</s>
<s>
All	O
Core-i	O
series	O
mobile	O
chipsets	B-Device
have	O
an	O
integrated	O
south	O
bridge	O
.	O
</s>
<s>
Every	O
4th	B-Device
Generation	I-Device
Intel	I-Device
Core	I-Device
and	O
5th	B-General_Concept
Generation	I-General_Concept
Intel	I-General_Concept
Core	I-General_Concept
processor	O
based	O
on	O
Mobile	O
U-Processor	O
and	O
Y-Processor	O
Lines	O
has	O
an	O
on-package	B-Algorithm
Platform	B-Device
Controller	I-Device
Hub	I-Device
.	O
</s>
<s>
All	O
support	O
Intel	O
VT-d	O
and	O
do	O
not	O
support	O
PCI	B-Protocol
.	O
</s>
<s>
The	O
100	O
Series	O
chipsets	B-Device
(	O
codenamed	O
Sunrise	O
Point	O
)	O
,	O
for	O
Skylake	B-Architecture
processors	O
using	O
the	O
LGA	B-Device
1151	I-Device
socket	B-General_Concept
,	O
were	O
released	O
in	O
the	O
third	O
quarter	O
of	O
2015	O
.	O
</s>
<s>
The	O
200	O
Series	O
chipsets	B-Device
(	O
codenamed	O
Union	O
Point	O
)	O
were	O
introduced	O
along	O
with	O
Kaby	B-Device
Lake	I-Device
processors	O
,	O
which	O
also	O
use	O
the	O
LGA	B-Device
1151	I-Device
socket	B-General_Concept
;	O
these	O
were	O
released	O
in	O
the	O
first	O
quarter	O
of	O
2017	O
.	O
</s>
<s>
While	O
Coffee	B-Device
Lake	I-Device
shares	O
the	O
same	O
socket	B-General_Concept
as	O
Skylake	B-Architecture
and	O
Kaby	B-Device
Lake	I-Device
,	O
this	O
revision	O
of	O
LGA	B-Device
1151	I-Device
is	O
electrically	O
incompatible	O
with	O
100	O
and	O
200	O
series	O
CPUs	B-Device
.	O
</s>
<s>
The	O
300	O
Series	O
chipsets	B-Device
were	O
introduced	O
along	O
with	O
Coffee	B-Device
Lake	I-Device
processors	O
,	O
which	O
use	O
the	O
LGA	B-Device
1151	I-Device
socket	B-General_Concept
;	O
the	O
enthusiast	O
model	O
was	O
released	O
in	O
the	O
last	O
quarter	O
of	O
2017	O
,	O
the	O
rest	O
of	O
the	O
line	O
was	O
released	O
in	O
2018	O
.	O
</s>
<s>
Chipset	B-Device
CodeName	O
sSpecNumber	O
Partnumbers	O
Release	O
Date	O
BusInterface	O
LinkSpeed	O
PCI	B-Protocol
Expresslanes	O
Intel	O
OptaneMemory	O
support	O
SATA	O
SATAe	B-Architecture
PCIe	O
M.2	B-Protocol
WirelessMAC	O
USB	B-Protocol
ports	I-Protocol
TDP	B-General_Concept
6	O
Gbit/s	O
v3.2	O
Gen	O
1x1	O
v3.2	O
Gen	O
2x1	O
Total	O
Z370	O
Cannon	O
Point	O
SR3MD(A0 )	O
GL82Z370	O
October	O
5	O
,	O
2017	O
DMI	B-Architecture
3.0	I-Architecture
3.93	O
GB/s	O
24	O
PCIe	O
3.0	O
6	O
up	O
to	O
3	O
up	O
to	O
3	O
Up	O
to	O
10	O
rowspan	O
=	O
2	O
Up	O
to	O
14	O
6	O
W	O
H310	O
SR409(B0 )	O
SRCXT(B0 )	O
SRCXY(B0 )	O
?	O
</s>
<s>
C232	O
and	O
C242	O
chipsets	B-Device
do	O
not	O
support	O
CPU	B-Device
integrated	O
GPUs	O
,	O
as	O
they	O
lack	O
FDI	B-Device
support	I-Device
.	O
</s>
<s>
Officially	O
they	O
support	O
only	O
Xeon	B-Device
processors	O
,	O
but	O
some	O
motherboards	B-Device
also	O
support	O
consumer	O
processors	O
(	O
6/7th	O
generation	O
Core	O
for	O
C230	O
series	O
,	O
8/9th	O
generation	O
Core	O
for	O
C240	O
series	O
and	O
its	O
Pentium/Celeron	O
derivatives	O
)	O
.	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
sSpec	O
Number	O
Part	O
numbers	O
Release	O
Date	O
Bus	O
Interface	O
Link	O
Speed	O
PCI	B-Protocol
Express	O
lanes	O
SATA	O
SATAe	B-Architecture
PCIe	O
M.2	B-Protocol
WirelessMAC	O
USB	B-Protocol
ports	I-Protocol
TDP	B-General_Concept
6	O
Gbit/s	O
v3.2	O
Gen	O
1x1	O
v3.2	O
Gen	O
2x1	O
Total	O
C232	O
Sunrise	O
Point	O
SR2CB(D1 )	O
GL82C232	O
(	O
PCH	O
)	O
September	O
1	O
,	O
2015	O
DMI	B-Architecture
3.0	O
3.93	O
GB/s	O
8	O
PCIe	O
3.0	O
Up	O
to	O
6	O
Up	O
to	O
3	O
Up	O
to	O
1	O
rowspan	O
=3	O
Up	O
to	O
6	O
rowspan	O
=	O
2	O
Up	O
to	O
12	O
6	O
W	O
C236	O
SR2CC(D1 )	O
GL82C236	O
(	O
PCH	O
)	O
20	O
PCIe	O
3.0	O
Up	O
to	O
8	O
Up	O
to	O
3	O
Up	O
to	O
10	O
Up	O
to	O
14	O
C242	O
Coffee	B-Device
Lake	I-Device
SR40C(B0 )	O
FH82C242	O
November	O
2018	O
10	O
PCIe	O
3.0	O
Up	O
to	O
6	O
?	O
</s>
<s>
Chipset	B-Device
Code	O
Name	O
sSpec	O
Number	O
Part	O
numbers	O
Release	O
Date	O
Bus	O
Interface	O
Link	O
Speed	O
PCI	B-Protocol
Express	O
lanes	O
SATA	O
SATAe	B-Architecture
PCIe	O
M.2	B-Protocol
WirelessMAC	O
USB	B-Protocol
ports	I-Protocol
TDP	B-General_Concept
6	O
Gbit/s	O
ports	O
v3.2	O
v2.0	O
Gen	O
1x1	O
Gen	O
2x1	O
HM170	O
SunrisePoint	O
SR2C4(D1 )	O
SR27Z	O
GL82HM170	O
(	O
PCH	O
)	O
September	O
1	O
,	O
2015	O
DMI	B-Architecture
3.0	O
3.93	O
GB/s	O
16	O
PCIe	O
3.0	O
Up	O
to	O
4	O
rowspan	O
=	O
"	O
10	O
"	O
Up	O
to	O
2	O
rowspan	O
=	O
"	O
7	O
"	O
Up	O
to	O
8	O
rowspan	O
=	O
"	O
7	O
"	O
Up	O
to	O
14	O
2.6	O
W	O
QM170	O
SR2C3(D1 )	O
SR27Y	O
GL82QM170	O
(	O
PCH	O
)	O
CM236	O
SR2CE(D1 )	O
GL82CM236	O
(	O
PCH	O
)	O
20	O
PCIe	O
3.0	O
Up	O
to	O
8	O
Up	O
to	O
3	O
Up	O
to	O
10	O
3.67	O
W	O
QMS180	O
SR2NH(D1 )	O
GLQMS180	O
(	O
PCH	O
)	O
?	O
</s>
<s>
CPU	B-Device
On-package	B-Algorithm
Chipset	B-Device
Code	O
Name	O
Release	O
Date	O
Bus	O
Interface	O
Link	O
Speed	O
PCI	B-Protocol
Express	O
lanes	O
SATA	O
SATAe	B-Architecture
PCIe	O
M.2	B-Protocol
WirelessMAC	O
USB	B-Protocol
ports	I-Protocol
TDP	B-General_Concept
6	O
Gbit/s	O
ports	O
v3.2	O
v2.0	O
Gen	O
1x1	O
Gen	O
2x1100	O
series	O
(	O
Base-U	O
)	O
SkylakeSeptember	O
2015OPI	O
x82GT/s	O
and	O
4GT/s10	O
PCIe	O
2.02	O
rowspan	O
="3	O
"	O
?	O
</s>
<s>
rowspan	O
="3	O
"	O
4	O
rowspan	O
="3	O
"	O
10	O
rowspan	O
="3	O
"	O
Kaby	B-Device
Lake	I-Device
(	O
Premium-U	O
)	O
12	O
PCIe	O
3.03	O
?	O
610Kaby	O
Lake	O
(	O
Premium-Y	O
)	O
10	O
PCIe	O
3.02	O
?	O
66300	O
series	O
(	O
Premium-U	O
)	O
Coffee	O
LakeApril	O
2018OPI	O
x8Up	O
to	O
4GT/s16	O
PCIe	O
3.03	O
?	O
</s>
<s>
LGA	O
1200	O
is	O
a	O
CPU	B-General_Concept
socket	I-General_Concept
designed	O
for	O
Comet	O
Lake	O
and	O
Rocket	O
Lake	O
desktop	O
CPUs	B-Device
.	O
</s>
<s>
Under	O
the	O
hood	O
,	O
LGA	O
1200	O
is	O
a	O
modified	O
version	O
of	O
LGA	B-Device
1151	I-Device
,	O
its	O
predecessor	O
.	O
</s>
<s>
†	O
Connection	O
to	O
the	O
CPU	B-Device
will	O
be	O
reduced	O
to	O
DMI	B-Architecture
3.0	I-Architecture
×4	O
if	O
a	O
Comet	O
Lake	O
CPU	B-Device
is	O
installed	O
.	O
</s>
<s>
DMI	B-Architecture
3.0	I-Architecture
×8	O
is	O
only	O
available	O
with	O
Rocket	O
Lake	O
CPUs	B-Device
.	O
</s>
<s>
‡	O
Mainboards	B-Device
advertised	O
as	O
H410	O
and	O
B460	O
with	O
Rocket	O
Lake	O
support	O
use	O
other	O
400-series	O
chipsets	B-Device
.	O
</s>
<s>
Every	O
12th	O
Gen	O
Intel	O
Core-i	O
mobile	O
CPU	B-Device
excluding	O
HX-series	B-Device
has	O
an	O
on-package	B-Algorithm
Platform	B-Device
Controller	I-Device
Hub	I-Device
.	O
</s>
<s>
Chipset	B-Device
CodeName	O
sSpecNumber	O
Partnumbers	O
Release	O
Date	O
BusInterface	O
LinkSpeed	O
PCI	B-Protocol
Expresslanes	O
Intel	O
OptaneMemory	O
support	O
SATA	O
SATAe	B-Architecture
PCIe	O
M.2	B-Protocol
WirelessMAC	O
USB	B-Protocol
ports	I-Protocol
TDP	B-General_Concept
4.0	O
3.0	O
6	O
Gbit/s	O
v2.0	O
v3.2	O
Gen	O
1x1	O
Gen	O
2x1	O
Gen	O
2x2	O
HM670Alder	O
Lake	O
SRL2Y(B1 )	O
FH82HM670Q2	O
2022DMI	O
4.0	O
✕8( 	O
15.76	O
GB/s	O
)	O
Up	O
to	O
16Up	O
to	O
12	O
rowspan	O
=	O
"	O
2	O
"	O
8	O
rowspan	O
=	O
"	O
2	O
"	O
rowspan	O
=	O
"	O
2	O
"	O
WiFi	O
6EUp	O
to	O
14Up	O
to	O
10Up	O
to	O
10Up	O
to	O
43.7	O
W	O
WM690	O
SRL2Z(B1 )	O
FH82WM690HM770Raptor	O
LakeSRM8M(B1 )	O
FH82HM770January	O
3	O
,	O
2023DMI	O
4.0	O
✕8( 	O
15.76	O
GB/s	O
)	O
28	O
including	O
PCIe	O
3.028	O
including	O
PCIe	O
3.0	O
rowspan	O
=	O
"	O
2	O
"	O
8	O
rowspan	O
=	O
"	O
2	O
"	O
rowspan	O
=	O
"	O
2	O
"	O
WiFi	O
6E14Up	O
to	O
10Up	O
to	O
10Up	O
to	O
43.7	O
WWM790	O
?	O
</s>
