<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
Turbo	B-Device
Boost	I-Device
(	O
except	O
D-1518	O
,	O
D-1529	O
)	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
8×	O
USB	B-Protocol
(	O
4×	O
2.0	O
,	O
4×	O
3.0	O
)	O
,	O
6×	O
SATA	O
,	O
2×	O
Integrated	O
10	O
GbE	O
LAN	B-General_Concept
,	O
UART	O
,	O
GPIO	B-Architecture
,	O
and	O
32	O
lanes	O
of	O
PCI	O
Express	O
(	O
8×	O
2.0	O
,	O
24×	O
3.0	O
)	O
,	O
in	O
×16	O
,	O
×8	O
and	O
×4	O
configurations	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
four	O
DIMMs	B-General_Concept
of	O
DDR4	O
or	O
DDR3L	O
memory	B-General_Concept
per	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
Modelnumber	O
sSpecnumber	O
Cores(threads )	O
Frequency	O
Turbo	B-Device
Boostall-core/2.0	O
(	O
/max	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
Turbo	B-Device
Boost	I-Device
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
four	O
DIMMs	B-General_Concept
of	O
DDR3L	O
memory	B-General_Concept
per	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
(	O
except	O
E5-2603v4	O
,	O
2609v4	O
and	O
4627v4	O
)	O
,	O
Turbo	B-Device
Boost	I-Device
2.0	O
(	O
except	O
E5-1603v4	O
,	O
1607v4	O
,	O
2603v4	O
,	O
2609v4	O
and	O
4610v4	O
)	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
twelve	O
DIMMs	B-General_Concept
of	O
DDR4	O
memory	B-General_Concept
per	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
Turbo	B-Device
Boost	I-Device
2.0	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
12	O
DIMMs	B-General_Concept
of	O
DDR4	O
memory	B-General_Concept
per	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
