<s>
The	O
Intel	B-General_Concept
Pentium	I-General_Concept
brand	O
is	O
a	O
line	O
of	O
mainstream	O
x86-architecture	O
microprocessors	B-Architecture
from	O
Intel	O
.	O
</s>
<s>
Processors	O
branded	O
Pentium	B-General_Concept
Processor	O
with	O
MMX	B-Architecture
Technology	O
(	O
and	O
referred	O
to	O
as	O
Pentium	B-General_Concept
MMX	B-Architecture
for	O
brevity	O
)	O
are	O
also	O
listed	O
here	O
.	O
</s>
<s>
Steppings	B-General_Concept
:	O
B1	O
,	O
C1	O
,	O
D1	O
(	O
Important	O
Notice	O
:	O
Only	O
D1	O
stepping	B-General_Concept
processors	O
do	O
not	O
have	O
FDIV	O
bug	O
!	O
)	O
</s>
<s>
Steppings	B-General_Concept
:	O
B1	O
,	O
B3	O
,	O
B5	O
,	O
C2	O
,	O
E0	O
(	O
Important	O
Notice	O
:	O
B5	O
,	O
C2	O
and	O
E0	O
stepping	B-General_Concept
processors	O
do	O
not	O
have	O
FDIV	O
bug	O
!	O
)	O
</s>
<s>
Desktop	O
processors	O
based	O
on	O
the	O
P6	B-Device
microarchitecture	I-Device
were	O
marketed	O
as	O
Pentium	B-Device
Pro	I-Device
,	O
Pentium	B-General_Concept
II	I-General_Concept
and	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
as	O
well	O
as	O
variations	O
of	O
these	O
names	O
.	O
</s>
<s>
Desktop	O
processors	O
based	O
on	O
the	O
NetBurst	B-Device
microarchitecture	I-Device
were	O
marketed	O
as	O
Pentium	B-General_Concept
4	I-General_Concept
and	O
Pentium	B-Device
D	I-Device
.	O
</s>
<s>
Earlier	O
E5xxx	O
desktop	O
processors	O
based	O
on	O
the	O
Core	B-Device
microarchitecture	I-Device
were	O
marketed	O
as	O
Pentium	B-Device
Dual-Core	I-Device
,	O
while	O
later	O
E5xxx	O
and	O
all	O
E6xxx	O
models	O
were	O
named	O
Pentium	B-General_Concept
.	O
</s>
<s>
Note	O
however	O
,	O
that	O
several	O
resellers	O
will	O
still	O
refer	O
to	O
the	O
newer	O
generation	O
processors	O
as	O
Pentium	B-Device
Dual-Core	I-Device
.	O
</s>
<s>
The	O
Intel	B-Device
Pentium	I-Device
Dual-Core	I-Device
processors	O
,	O
E2140	O
,	O
E2160	O
,	O
E2180	B-Device
,	O
E2200	O
,	O
and	O
E2220	O
use	O
the	O
Allendale	O
core	O
,	O
which	O
includes	O
2	O
MB	O
of	O
native	O
L2	O
cache	O
,	O
with	O
half	O
disabled	O
leaving	O
only	O
1	O
MB	O
.	O
</s>
<s>
Intel	O
has	O
shifted	O
its	O
product	O
lines	O
having	O
the	O
Core	O
2	O
line	O
as	O
Mainstream/Performance	O
,	O
Pentium	B-Device
Dual-Core	I-Device
as	O
Mainstream	O
,	O
and	O
the	O
new	O
Celeron	O
(	O
based	O
on	O
the	O
Conroe-L	O
core	O
)	O
as	O
Budget/Value	O
.	O
</s>
<s>
Based	O
on	O
the	O
64-bit	O
Core	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
1	O
MB	O
of	O
L2	O
cache	O
is	O
disabled	O
,	O
for	O
a	O
total	O
of	O
2	O
MB	O
L2	O
cache	O
,	O
or	O
twice	O
the	O
amount	O
in	O
the	O
original	O
Allendale	O
Pentiums	B-General_Concept
.	O
</s>
<s>
The	O
Wolfdale	O
core	O
is	O
capable	O
of	O
SSE4	O
,	O
but	O
it	O
is	O
disabled	O
in	O
these	O
Pentiums	B-General_Concept
.	O
</s>
<s>
Pentium	B-General_Concept
E2210	O
is	O
an	O
OEM	O
processor	O
based	O
on	O
Wolfdale-3M	O
with	O
only	O
1	O
MB	O
L2	O
cache	O
enabled	O
out	O
of	O
the	O
total	O
3	O
MB	O
.	O
</s>
<s>
E5000-series	O
processors	O
were	O
initially	O
known	O
as	O
Pentium	B-Device
Dual-Core	I-Device
,	O
while	O
all	O
later	O
processors	O
were	O
just	O
Pentium	B-General_Concept
.	O
</s>
<s>
Note	O
that	O
these	O
are	O
also	O
dual	O
core	O
,	O
but	O
under	O
the	O
Pentium	B-General_Concept
brand	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Contains	O
45nm	O
"	O
Ironlake	O
"	O
GPU	B-Architecture
.	O
</s>
<s>
G6951	O
can	O
be	O
unlocked	O
to	O
enable	O
Hyper-threading	B-Operating_System
and	O
an	O
extra	O
1MB	O
of	O
L3	O
cache	O
,	O
which	O
are	O
present	O
in	O
the	O
CPU	O
but	O
deliberately	O
disabled	O
,	O
with	O
the	O
purchase	O
of	O
a	O
$50	O
upgrade	O
card	O
by	O
way	O
of	O
the	O
Intel	B-Device
Upgrade	I-Device
Service	I-Device
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Pentium	B-General_Concept
G8xx	O
supports	O
DDR3-1333	O
in	O
addition	O
to	O
DDR3-1066	O
.	O
</s>
<s>
HD	B-Application
Graphics	I-Application
(	O
Sandy	B-Device
Bridge	I-Device
)	O
contain	O
6	O
EUs	B-General_Concept
as	O
well	O
as	O
HD	B-Application
Graphics	I-Application
2000	I-Application
,	O
but	O
does	O
not	O
support	O
the	O
following	O
technologies	O
:	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
,	O
InTru3D	B-Algorithm
,	O
Intel	B-Device
Clear	I-Device
Video	I-Device
HD	I-Device
,	O
Wireless	O
display	O
,	O
Intel	O
insider	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
G622	O
,	O
once	O
upgraded	O
via	O
Intel	B-Device
Upgrade	I-Device
Service	I-Device
,	O
operates	O
at	O
3.2	O
GHz	O
,	O
has	O
3	O
MB	O
L3	O
cache	O
and	O
is	O
recognized	O
as	O
Pentium	B-General_Concept
G693	O
.	O
</s>
<s>
The	O
Pentium	B-General_Concept
G632	O
,	O
once	O
upgraded	O
via	O
Intel	B-Device
Upgrade	I-Device
Service	I-Device
,	O
operates	O
at	O
3.3	O
GHz	O
,	O
has	O
3	O
MB	O
L3	O
cache	O
and	O
is	O
recognized	O
as	O
Pentium	B-General_Concept
G694	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
HD	B-Application
Graphics	I-Application
(	O
Ivy	B-Device
Bridge	I-Device
)	O
contain	O
6	O
EUs	B-General_Concept
as	O
well	O
as	O
HD	B-Application
Graphics	I-Application
2500	I-Application
,	O
but	O
does	O
not	O
support	O
the	O
following	O
technologies	O
:	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
,	O
InTru3D	B-Algorithm
,	O
Intel	B-Device
Clear	I-Device
Video	I-Device
HD	I-Device
,	O
Wireless	O
display	O
,	O
Intel	O
insider	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
G3258	O
(	O
Pentium	B-General_Concept
anniversary	O
edition	O
)	O
has	O
unlocked	O
CPU	O
multiplier	O
.	O
</s>
<s>
Haswell	B-Device
Pentiums	B-General_Concept
support	O
Quick	B-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
Intel	O
VT-x	O
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Ivy	B-Device
Bridge	I-Device
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
4	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
11	O
,	O
OpenGL	O
4.0	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
1.1	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
J2900	O
supports	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Broadwell	B-General_Concept
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
18	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
11.2	O
,	O
OpenGL	O
4.4	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
2.0	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Embedded	O
models	O
support	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Intel	O
SGX	O
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Kaby	B-Device
Lake	I-Device
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
18	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.5	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
2.0	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Intel	O
SGX	O
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Kaby	B-Device
Lake	I-Device
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
18	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.5	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
2.0	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
MPX	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Low	O
power	B-General_Concept
models	O
also	O
support	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Low	O
power	B-General_Concept
models	O
also	O
support	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Low	O
power	B-General_Concept
models	O
also	O
support	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
DL	B-General_Concept
Boost	I-General_Concept
,	O
GNA	O
3.0	O
,	O
and	O
Optane	B-Device
memory	I-Device
.	O
</s>
<s>
Mobile	O
processors	O
based	O
on	O
the	O
P6	B-Device
microarchitecture	I-Device
were	O
marketed	O
as	O
Pentium	B-General_Concept
II	I-General_Concept
,	O
Pentium	B-General_Concept
III	I-General_Concept
,	O
Pentium	B-Architecture
M	I-Architecture
and	O
Pentium	B-Device
Dual-Core	I-Device
,	O
as	O
well	O
as	O
variations	O
of	O
these	O
names	O
.	O
</s>
<s>
Mobile	O
processors	O
based	O
on	O
the	O
NetBurst	B-Device
microarchitecture	I-Device
were	O
marketed	O
as	O
Pentium	B-General_Concept
4	I-General_Concept
.	O
</s>
<s>
Prior	O
mobile	O
processors	O
based	O
on	O
the	O
Core	B-Device
microarchitecture	I-Device
were	O
marketed	O
as	O
Pentium	B-Device
Dual-Core	I-Device
,	O
while	O
the	O
current	O
models	O
are	O
named	O
Pentium	B-General_Concept
.	O
</s>
<s>
Note	O
however	O
,	O
that	O
several	O
resellers	O
will	O
still	O
refer	O
to	O
them	O
as	O
Pentium	B-Device
Dual-Core	I-Device
.	O
</s>
<s>
T2060	B-Device
debuted	O
on	O
January	O
30	O
,	O
2007	O
in	O
notebooks	O
only	O
sold	O
as	O
part	O
of	O
Windows	B-Application
Vista	I-Application
launch	O
bundles	O
;	O
it	O
appears	O
to	O
be	O
OEM-only	O
.	O
</s>
<s>
Note	O
:	O
The	O
Pentium	B-General_Concept
SU2X00	O
series	O
processors	O
have	O
a	O
single	O
core	O
,	O
not	O
two	O
,	O
according	O
to	O
Intel	O
's	O
website	O
.	O
</s>
<s>
FSB	B-Architecture
has	O
been	O
replaced	O
with	O
DMI	B-Architecture
.	O
</s>
<s>
Contains	O
45nm	O
"	O
Ironlake	O
"	O
GPU	B-Architecture
HD	B-Application
Graphics	I-Application
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
HD	B-Application
Graphics	I-Application
(	O
Sandy	B-Device
Bridge	I-Device
)	O
contain	O
6	O
EUs	B-General_Concept
as	O
well	O
as	O
HD	B-Application
Graphics	I-Application
2000	I-Application
,	O
but	O
does	O
not	O
support	O
the	O
following	O
technologies	O
:	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
,	O
InTru	B-Algorithm
3D	I-Algorithm
,	O
Clear	O
Video	O
HD	O
,	O
Wireless	O
Display	O
,	O
Intel	O
Insider	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
HD	B-Application
Graphics	I-Application
(	O
Ivy	B-Device
Bridge	I-Device
)	O
contain	O
6	O
EUs	B-General_Concept
as	O
well	O
as	O
HD	B-Application
Graphics	I-Application
2500	I-Application
,	O
but	O
does	O
not	O
support	O
the	O
following	O
technologies	O
:	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
,	O
InTru	B-Algorithm
3D	I-Algorithm
,	O
Clear	O
Video	O
HD	O
,	O
Wireless	O
Display	O
,	O
Intel	O
Insider	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
.	O
</s>
<s>
3825U	O
also	O
supports	O
Hyper-threading	B-Operating_System
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Ivy	B-Device
Bridge	I-Device
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
4	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
11	O
,	O
OpenGL	O
4.0	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
1.1	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
N3530	O
and	O
N3540	O
support	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Broadwell	B-General_Concept
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
16	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
11.2	O
,	O
OpenGL	O
4.3	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
1.2	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
GPU	B-Architecture
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.4	O
and	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
GPU	B-Architecture
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.4	O
and	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Skylake	B-Architecture
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
18	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.5	O
,	O
OpenGL	O
ES	O
3.0	O
,	O
OpenCL	O
1.2	O
(	O
on	O
Windows	O
)	O
and	O
Intel	B-Algorithm
Quick	I-Algorithm
Sync	I-Algorithm
Video	I-Algorithm
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Intel	O
SGX	O
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Kaby	B-Device
Lake	I-Device
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
18	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.5	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
1.2	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Intel	O
SGX	O
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Kaby	B-Device
Lake	I-Device
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
18	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
DirectX	O
12	O
,	O
OpenGL	O
4.5	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
1.2	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
MPX	B-Device
,	O
Hyper-threading	B-Operating_System
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
and	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
Note	O
:	O
Pentium	B-General_Concept
4415U	O
was	O
renamed	O
to	O
Pentium	B-General_Concept
Gold	O
4415U	O
(	O
end	O
2017	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
MPX	B-Device
,	O
Hyper-threading	B-Operating_System
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
and	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
MPX	B-Device
,	O
Hyper-threading	B-Operating_System
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
and	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
SGX	O
,	O
MPX	B-Device
,	O
Hyper-threading	B-Operating_System
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
and	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
down	O
.	O
</s>
<s>
Pentium	B-General_Concept
Gold	O
6500Y	O
also	O
support	O
:	O
AVX	B-General_Concept
,	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
Turbo	B-Device
Boost	I-Device
,	O
and	O
configurable	O
TDP	O
(	O
cTDP	O
)	O
up	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
Speed	B-Device
Shift	I-Device
Technology	I-Device
(	O
SST	O
)	O
,	O
Intel	O
64	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Turbo	B-Device
Boost	I-Device
,	O
Hyper-threading	B-Operating_System
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
DL	B-General_Concept
Boost	I-General_Concept
,	O
Optane	B-Device
memory	I-Device
,	O
GNA	O
2.0	O
,	O
IPU6	B-General_Concept
,	O
TB4	O
.	O
</s>
<s>
Two	O
USB	B-Protocol
3.2	O
2x1	O
ports	O
(	O
a.k.a.	O
</s>
<s>
Four	O
USB	B-Protocol
3.2	O
1x1	O
ports	O
(	O
a.k.a.	O
</s>
<s>
All	O
models	O
support	O
:	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
AVX2	O
,	O
FMA3	B-General_Concept
,	O
Speed	B-Device
Shift	I-Device
Technology	I-Device
(	O
SST	O
)	O
,	O
Intel	O
64	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
Hyper-threading	B-Operating_System
,	O
Turbo	B-Device
Boost	I-Device
,	O
AES-NI	B-Algorithm
,	O
IPU6	B-General_Concept
(	O
except	O
SRLFV	O
)	O
,	O
TB4	O
,	O
Smart	O
Cache	O
,	O
Thread	O
Director	O
,	O
DL	B-General_Concept
Boost	I-General_Concept
,	O
and	O
GNA	O
3.0	O
.	O
</s>
<s>
Standard	O
power	B-General_Concept
models	O
also	O
support	O
up	O
to	O
DDR5-4800	O
or	O
DDR4-3200	O
memory	O
.	O
</s>
<s>
Modelnumber	O
P-core	O
(	O
performance	O
)	O
E-core	O
(	O
efficiency	O
)	O
L3cache	O
GPUmodel	O
GPUfrequency	O
Power	B-General_Concept
Socket	B-General_Concept
I/O	O
bus	O
rowspan	O
=	O
2	O
style	O
=	O
"	O
text-align:right	O
;	O
"	O
Release	O
date	O
sSpecnumber	O
Partnumber(s )	O
Releaseprice	O
(	O
USD	O
)	O
Cores(threads )	O
Freq	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Smart	O
Cache	O
,	O
Hyper-threading	B-Operating_System
.	O
</s>
<s>
No	O
models	O
include	O
HD	B-Application
Graphics	I-Application
.	O
</s>
<s>
Based	O
on	O
Sandy	B-Device
Bridge-E	I-Device
CPU	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
Intel	O
VT-c	O
,	O
Intel	B-Error_Name
x8	I-Error_Name
SDDC	I-Error_Name
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
6	O
DIMMS	B-General_Concept
of	O
DDR3	O
memory	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
TXT	B-Device
,	O
Intel	O
VT-x	O
,	O
Intel	O
EPT	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
Smart	O
Cache	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
D1508	O
,	O
D1517	O
,	O
D1519	O
also	O
support	O
Hyper-threading	B-Operating_System
,	O
Turbo	B-Device
Boost	I-Device
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
8	O
×	O
USB	B-Protocol
(	O
4	O
×	O
2.0	O
,	O
4	O
×	O
3.0	O
)	O
,	O
6	O
×	O
SATA	O
,	O
2	O
×	O
Integrated	O
10	O
GbE	O
LAN	B-General_Concept
,	O
UART	O
,	O
GPIO	B-Architecture
,	O
and	O
32	O
lanes	O
of	O
PCI	O
Express	O
(	O
8	O
×	O
2.0	O
,	O
24	O
×	O
3.0	O
)	O
,	O
in	O
×16	O
,	O
×8	O
and	O
×4	O
configurations	O
.	O
</s>
<s>
Support	O
for	O
up	O
to	O
four	O
DIMMs	B-General_Concept
of	O
DDR4	O
or	O
DDR3L	O
memory	O
per	O
CPU	B-General_Concept
socket	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
EPT	O
,	O
Hyper-threading	B-Operating_System
,	O
Smart	O
Cache	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
GPU	B-Architecture
is	O
based	O
on	O
Gen11	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
up	O
to	O
32	O
execution	B-General_Concept
units	I-General_Concept
,	O
and	O
supports	O
up	O
to	O
3	O
displays	O
(	O
4K	O
@	O
60	O
Hz	O
)	O
through	O
HDMI	B-Protocol
,	O
DP	B-Protocol
,	O
eDP	O
,	O
or	O
DSI	O
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0/3.0/3.1	O
,	O
2	O
×	O
SATA	O
,	O
3	O
×	O
2.5GbE	O
LAN	B-General_Concept
,	O
UART	O
,	O
and	O
up	O
to	O
8	O
lanes	O
of	O
PCI	O
Express	O
3.0	O
in	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
