<s>
The	O
Itanium	B-General_Concept
from	O
Intel	O
is	O
a	O
high-end	O
server	B-Application
and	O
supercomputer	B-Architecture
microprocessor	O
.	O
</s>
<s>
CPUID	B-Architecture
:	O
0007000604h	O
(	O
stepping	O
C0	O
)	O
,	O
0007000704h	O
(	O
stepping	O
C1	O
)	O
or	O
0007000804h	O
(	O
stepping	O
C2	O
)	O
.	O
</s>
<s>
The	O
FSB	B-Architecture
data	O
bus	O
is	O
64	O
bits	O
wide	O
,	O
not	O
128	O
like	O
in	O
Itanium	B-General_Concept
2	O
.	O
</s>
<s>
Itanium	B-General_Concept
2	O
uses	O
socket	B-Device
PAC611	I-Device
with	O
a	O
128	O
bit	O
wide	O
FSB	B-Architecture
.	O
</s>
<s>
All	O
Itaniums	B-General_Concept
except	O
some	O
130nm	O
models	O
are	O
capable	O
of	O
>2-socket	O
SMP	B-Operating_System
.	O
</s>
<s>
CPUID	B-Architecture
:	O
001F010504h	O
.	O
</s>
<s>
CPUID	B-Architecture
:	O
001F020104h	O
(	O
stepping	O
A1	O
)	O
or	O
001F020204h	O
(	O
stepping	O
A2	O
)	O
.	O
</s>
<s>
9M	O
is	O
the	O
chip	O
of	O
all	O
the	O
third	O
generation	O
Itanium	B-General_Concept
2s	O
,	O
irrespective	O
of	O
the	O
amount	O
of	O
enabled	O
cache	O
.	O
</s>
<s>
This	O
multi-chip	B-Algorithm
module	I-Algorithm
codenamed	O
Hondo	O
is	O
not	O
an	O
Intel	O
product	O
,	O
but	O
a	O
separate	O
project	O
of	O
Hewlett-Packard	O
to	O
pack	O
two	O
CPUs	O
onto	O
one	O
PAC611	B-Device
socket	O
.	O
</s>
<s>
CPUID	B-Architecture
:	O
0020000504h	O
(	O
stepping	O
C1	O
)	O
or	O
0020000704h	O
(	O
stepping	O
C2	O
)	O
.	O
</s>
<s>
All	O
processors	O
can	O
support	O
the	O
legacy	O
400	O
MT/s	O
FSB	B-Architecture
.	O
</s>
<s>
From	O
Montecito	O
onwards	O
all	O
Itaniums	B-General_Concept
are	O
MP-capable	O
.	O
</s>
<s>
The	O
chip	O
is	O
similar	O
to	O
Montecito	O
,	O
but	O
the	O
stepping	O
is	O
A1	O
and	O
the	O
CPUID	B-Architecture
is	O
0020010104h	O
.	O
</s>
<s>
The	O
models	O
with	O
533	O
MT/s	O
FSB	B-Architecture
also	O
support	O
400	O
MT/s	O
FSB	B-Architecture
operation	O
.	O
</s>
<s>
Even	O
though	O
Intel	O
does	O
not	O
use	O
the	O
"	O
Itanium	B-General_Concept
2	O
"	O
branding	O
for	O
the	O
9100-series	O
,	O
it	O
's	O
still	O
grouped	O
with	O
Itanium	B-General_Concept
2	O
processors	O
because	O
it	O
uses	O
the	O
same	O
platform	O
and	O
is	O
a	O
minor	O
update	O
on	O
the	O
9000-series	O
.	O
</s>
<s>
These	O
later	O
generations	O
of	O
Itanium	B-General_Concept
use	O
socket	O
LGA	B-Device
1248	I-Device
,	O
the	O
QuickPath	B-Architecture
Interconnect	I-Architecture
and	O
Scalable	O
Memory	O
Interconnect	O
having	O
replaced	O
the	O
Front-Side	B-Architecture
Bus	I-Architecture
used	O
by	O
Itanium	B-General_Concept
2	O
.	O
</s>
<s>
CPUID	B-Architecture
:	O
0020020404.All	O
models	O
support	O
:	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Hyper-threading	B-Operating_System
,	O
Turbo	B-Device
Boost	I-Device
,	O
VT-i2	O
(	O
Itanium	B-General_Concept
Virtualization	O
technology	O
)	O
,	O
Intel	O
VT-d	O
,	O
RAS	O
with	O
Advanced	O
Machine	O
Check	O
Architecture	O
,	O
Cache	O
Safe	O
technology	O
,	O
Enhanced	O
Demand	O
Based	O
Switching	O
,	O
ECC	B-General_Concept
,	O
two	O
memory	O
controllers	O
each	O
with	O
two	O
SMI	O
links	O
to	O
memory	O
buffers	O
for	O
DDR3	O
,	O
for	O
a	O
combined	O
memory	O
bandwidth	O
of	O
34	O
GB/s	O
and	O
capacity	O
of	O
256	O
GB	O
.	O
</s>
<s>
The	O
QPI	B-Architecture
bandwidth	O
is	O
96	O
GB/s	O
for	O
cache	O
coherency	O
and	O
24	O
GB/s	O
for	O
I/O	O
.	O
</s>
<s>
CPUID	B-Architecture
:	O
0021000404.All	O
models	O
support	O
:	O
Itanium	B-General_Concept
New	O
Instructions	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
VT-i3	O
(	O
Itanium	B-General_Concept
Virtualization	O
technology	O
)	O
,	O
Hyper-threading	B-Operating_System
(	O
with	O
Dual-Domain	O
Multithreading	O
)	O
,	O
Turbo	B-Device
Boost	I-Device
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Cache-Safe	O
technology	O
,	O
RAS	O
with	O
Advanced	O
Machine	O
Check	O
Architecture	O
,	O
Instruction	O
Replay	O
technology	O
,	O
ECC	B-General_Concept
,	O
two	O
memory	O
controllers	O
each	O
with	O
two	O
SMI	O
links	O
to	O
memory	O
buffers	O
for	O
DDR3	O
,	O
for	O
a	O
combined	O
memory	O
bandwidth	O
of	O
45	O
GB/s	O
and	O
capacity	O
of	O
512	O
GB	O
.	O
</s>
<s>
The	O
QPI	B-Architecture
bandwidth	O
is	O
128	O
GB/s	O
for	O
cache	O
coherency	O
and	O
32	O
GB/s	O
for	O
I/O	O
.	O
</s>
<s>
The	O
9700	O
series	O
,	O
despite	O
nominally	O
having	O
a	O
different	O
stepping	O
(	O
E0	O
with	O
CPUID	B-Architecture
0021000504	O
)	O
,	O
is	O
functionally	O
identical	O
with	O
the	O
9500	O
series	O
,	O
even	O
having	O
exactly	O
the	O
same	O
bugs	O
,	O
the	O
only	O
difference	O
being	O
the	O
133MHz	O
higher	O
frequency	O
of	O
9760	O
and	O
9750	O
over	O
9560	O
and	O
9550	O
respectively	O
.	O
</s>
<s>
Kittson	O
was	O
supposed	O
to	O
be	O
on	O
a	O
22nm	O
process	O
and	O
use	O
the	O
same	O
LGA2011	B-Device
socket	O
and	O
platform	O
as	O
Xeons	B-Device
.	O
</s>
<s>
On	O
31	O
January	O
2013	O
Intel	O
issued	O
an	O
update	O
to	O
their	O
plans	O
for	O
Kittson	O
:	O
it	O
would	O
have	O
the	O
same	O
LGA1248	B-Device
socket	O
and	O
32nm	O
process	O
as	O
Poulson	O
,	O
effectively	O
halting	O
any	O
further	O
development	O
of	O
Itanium	B-General_Concept
processors	O
.	O
</s>
