<s>
The	O
Intel	B-Device
Atom	I-Device
is	O
Intel	O
's	O
line	O
of	O
low-power	O
,	O
low-cost	O
and	O
low-performance	O
x86	B-Operating_System
and	O
x86-64	B-Device
microprocessors	B-Architecture
.	O
</s>
<s>
Atom	B-Application
,	O
with	O
codenames	O
of	O
Silverthorne	O
and	O
Diamondville	O
,	O
was	O
first	O
announced	O
on	O
March	O
2	O
,	O
2008	O
.	O
</s>
<s>
For	O
Nettop	B-Protocol
and	O
Netbook	B-Device
Atom	B-Application
Microprocessors	B-Architecture
after	O
Diamondville	O
,	O
the	O
memory	O
and	O
graphics	O
controller	O
are	O
moved	O
from	O
the	O
northbridge	B-Device
to	O
the	O
CPU	O
.	O
</s>
<s>
This	O
explains	O
the	O
drastically	O
increased	O
transistor	O
count	O
for	O
post-Diamondville	O
Atom	B-Application
microprocessors	B-Architecture
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Hyper-Threading	B-Operating_System
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
Burst	O
Performance	O
Technology	O
(	O
BPT	O
)	O
,	O
Hyper-Threading	B-Operating_System
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
,	O
Intel	O
Burst	O
Performance	O
Technology	O
(	O
BPT	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
,	O
Intel	O
Burst	O
Performance	O
Technology	O
(	O
BPT	O
)	O
,	O
Intel	O
Wireless	O
Display	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Hyper-Threading	B-Operating_System
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Hyper-Threading	B-Operating_System
,	O
Intel	O
Burst	O
Performance	O
Technology	O
(	O
BPT	O
)	O
.	O
</s>
<s>
Type	O
4	O
SoC	B-Architecture
:	O
</s>
<s>
Type	O
3	O
SoC	B-Architecture
:	O
</s>
<s>
Type	O
4	O
SoC	B-Architecture
:	O
</s>
<s>
Type	O
3	O
SoC	B-Architecture
:	O
</s>
<s>
CPU	O
core	O
supports	O
IA-32	B-Device
architecture	O
,	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
hyper-threading	B-Operating_System
,	O
Intel	O
VT-x	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
GPU	O
is	O
based	O
on	O
Broadwell	B-General_Concept
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
12	O
execution	O
units	O
,	O
and	O
supports	O
DirectX	O
11.2	O
,	O
OpenGL	O
4.3	O
,	O
OpenGL	O
ES	O
3.0	O
and	O
OpenCL	O
1.2	O
(	O
on	O
Windows	O
)	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
.	O
</s>
<s>
GPU	O
is	O
based	O
on	O
Gen11	O
Intel	B-Application
HD	I-Application
Graphics	I-Application
,	O
with	O
up	O
to	O
32	O
execution	O
units	O
,	O
and	O
supports	O
up	O
to	O
3	O
displays	O
(	O
4K	O
@	O
60Hz	O
)	O
through	O
HDMI	B-Protocol
,	O
DP	B-Protocol
,	O
eDP	O
,	O
or	O
DSI	O
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0/3.0/3.1	O
,	O
2	O
×	O
SATA	O
,	O
3	O
×	O
2.5GbE	O
LAN	B-General_Concept
,	O
UART	O
,	O
and	O
up	O
to	O
8	O
lanes	O
of	O
PCI	O
Express	O
3.0	O
in	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
<s>
All	O
Atom	B-Application
server	B-Application
processors	O
include	O
ECC	O
support	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Hyper-threading	B-Operating_System
,	O
Intel	O
64	O
,	O
Intel	O
VT-x	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
Hyper-threading	B-Operating_System
,	O
Intel	O
64	O
,	O
Intel	O
VT-x	O
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	B-Device
Turbo	I-Device
Boost	I-Device
,	O
Intel	O
64	O
(	O
according	O
to	O
Datasheet	O
)	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
Dual-core	O
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
2	O
×	O
SATA	O
,	O
2	O
×	O
Integrated	O
GbE	O
LAN	B-General_Concept
,	O
2	O
×	O
UART	O
,	O
and	O
4	O
lanes	O
of	O
PCI	O
Express	O
2.0	O
,	O
in	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
<s>
Quad-core	O
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
2	O
(	O
C2530	O
)	O
or	O
6	O
(	O
C2550	O
)	O
×	O
SATA	O
,	O
2	O
×	O
Integrated	O
GbE	O
LAN	B-General_Concept
,	O
2	O
×	O
UART	O
,	O
and	O
8	O
lanes	O
of	O
PCI	O
Express	O
2.0	O
,	O
in	O
x8	O
,	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
<s>
C2730	O
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
2	O
×	O
SATA	O
,	O
2	O
×	O
Integrated	O
GbE	O
LAN	B-General_Concept
,	O
2	O
×	O
UART	O
,	O
and	O
8	O
lanes	O
of	O
PCI	O
Express	O
2.0	O
,	O
in	O
x8	O
,	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
<s>
C2750	O
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
6	O
×	O
SATA	O
,	O
4	O
×	O
Integrated	O
GbE	O
LAN	B-General_Concept
,	O
2	O
×	O
UART	O
,	O
and	O
16	O
lanes	O
of	O
PCI	O
Express	O
2.0	O
,	O
in	O
x16	O
,	O
x8	O
,	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	B-Device
Turbo	I-Device
Boost	I-Device
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
4-6	O
×	O
SATA	O
(	O
1	O
for	O
C2308	O
,	O
2	O
for	O
C2316	O
,	O
C2508	O
,	O
C2516	O
)	O
,	O
4	O
×	O
Integrated	O
GbE	O
LAN	B-General_Concept
(	O
2	O
for	O
C2316	O
)	O
,	O
2	O
×	O
UART	O
,	O
and	O
8-16	O
lanes	O
of	O
PCI	O
Express	O
2.0	O
(	O
4	O
lanes	O
for	O
C2308	O
)	O
,	O
in	O
x16	O
,	O
x8	O
,	O
x4	O
,	O
x2	O
,	O
and	O
x1	O
configurations	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Enhanced	O
Intel	B-Device
SpeedStep	I-Device
Technology	O
(	O
EIST	B-Device
)	O
,	O
Intel	B-Device
Turbo	I-Device
Boost	I-Device
(	O
dual-core	O
,	O
C3xx0	O
,	O
C3xx5	O
only	O
)	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
Intel	O
VT-d	O
,	O
AES-NI	B-Algorithm
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
8	O
–	O
16	O
×	O
USB	B-Protocol
3.0	O
,	O
6	O
–	O
16	O
×	O
SATA	O
,	O
4	O
×	O
Integrated	O
1GbE	O
,	O
2.5GbE	O
,	O
and	O
10GbE	O
(	O
C3538	O
and	O
up	O
)	O
LAN	B-General_Concept
,	O
and	O
up	O
to	O
20	O
lanes	O
of	O
PCI	O
Express	O
3.0	O
,	O
in	O
x8	O
,	O
x4	O
,	O
and	O
x2	O
configurations	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
3.0	O
,	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
16	O
×	O
SATA	O
,	O
Integrated	O
Intel	O
Ethernet	O
800	O
series	O
100Gbps	O
LAN	B-General_Concept
,	O
3	O
×	O
UART	O
,	O
and	O
up	O
to	O
32	O
lanes	O
of	O
PCI	O
Express	O
(	O
16	O
×	O
2.0	O
,	O
16	O
×	O
3.0	O
)	O
,	O
in	O
x16	O
,	O
x8	O
,	O
and	O
x4	O
configurations	O
.	O
</s>
<s>
P###	O
#B	O
models	O
are	O
designed	O
for	O
base	B-General_Concept
transceiver	I-General_Concept
stations	I-General_Concept
,	O
especially	O
that	O
for	O
5G	O
networks	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
Intel	O
64	O
,	O
XD	B-General_Concept
bit	I-General_Concept
(	O
an	O
NX	B-General_Concept
bit	I-General_Concept
implementation	O
)	O
,	O
Intel	O
VT-x	O
,	O
AES-NI	B-Algorithm
,	O
ECC	B-General_Concept
memory	I-General_Concept
.	O
</s>
<s>
SoC	B-Architecture
peripherals	O
include	O
4	O
×	O
USB	B-Protocol
3.0	O
,	O
4	O
×	O
USB	B-Protocol
2.0	O
,	O
16	O
×	O
SATA	O
,	O
Integrated	O
Intel	O
Ethernet	O
800	O
series	O
100Gbps	O
LAN	B-General_Concept
(	O
except	O
51xx	O
model	O
numbers	O
)	O
,	O
3	O
×	O
UART	O
,	O
and	O
up	O
to	O
32	O
lanes	O
of	O
PCI	O
Express	O
(	O
16	O
×	O
2.0	O
,	O
16	O
×	O
3.0	O
)	O
,	O
in	O
x16	O
,	O
x8	O
,	O
and	O
x4	O
configurations	O
.	O
</s>
