<s>
HDL	B-Algorithm
simulators	I-Algorithm
are	O
software	O
packages	O
that	O
simulate	O
expressions	O
written	O
in	O
one	O
of	O
the	O
hardware	O
description	O
languages	O
,	O
such	O
as	O
VHDL	B-Language
,	O
Verilog	B-Language
,	O
SystemVerilog	B-Language
.	O
</s>
<s>
This	O
page	O
is	O
intended	O
to	O
list	O
current	O
and	O
historical	O
HDL	B-Algorithm
simulators	I-Algorithm
,	O
accelerators	O
,	O
emulators	O
,	O
etc	O
.	O
</s>
<s>
+	O
List	B-Algorithm
of	I-Algorithm
HDL	I-Algorithm
simulators	I-Algorithm
in	O
alphabetical	O
order	O
by	O
name	O
Simulator	O
name	O
Author/company	O
Languages	O
Description	O
Active-HDL/Riviera	O
-PRO	O
Aldec	O
VHDL-1987	O
,	O
-1993	O
,	O
-2002	O
,	O
-2008	O
,	O
-2019	O
V1995	O
,	O
V2001	O
,	O
V2005	O
,	O
SV2009	O
,	O
SV2012	O
,	O
SV2017	O
Active-HDL	O
is	O
Aldec	O
's	O
Windows-based	O
simulator	O
with	O
complete	O
HDL	O
graphical	O
entry	O
and	O
verification	O
environment	O
aimed	O
at	O
FPGA	O
and	O
SoC	O
FPGA	O
applications	O
.	O
</s>
<s>
Aldec	O
simulators	O
have	O
the	O
complete	O
VHDL-2008	O
implementation	O
and	O
the	O
first	O
to	O
offer	O
VHDL-2019	O
features	O
.	O
</s>
<s>
Aeolus-DS	O
supports	O
pure	O
Verilog	B-Language
simulation.HiLoTeradyneUsed	O
in	O
1980s	O
.	O
</s>
<s>
Incisive	B-Algorithm
Enterprise	I-Algorithm
Simulator	I-Algorithm
( 	O
 '	O
big	O
3	O
 '	O
)	O
Cadence	O
Design	O
Systems	O
VHDL-1987	O
,	O
-1993	O
,	O
-2002	O
,	O
-2008	O
,	O
V2001	O
,	O
SV2005	O
,	O
SV2009	O
,	O
SV2012	O
,	O
SV2017	O
Cadence	O
initially	O
acquired	O
Gateway	O
Design	O
,	O
thereby	O
acquiring	O
Verilog-XL	O
.	O
</s>
<s>
In	O
response	O
to	O
competition	O
from	O
faster	O
simulators	O
,	O
Cadence	O
developed	O
its	O
own	O
compiled-language	O
simulator	O
,	O
NC-Verilog	B-Algorithm
.	O
</s>
<s>
The	O
modern	O
version	O
of	O
the	O
NCsim	B-Algorithm
family	O
,	O
called	O
Incisive	B-Algorithm
Enterprise	I-Algorithm
Simulator	I-Algorithm
,	O
includes	O
Verilog	B-Language
,	O
VHDL	B-Language
,	O
and	O
SystemVerilog	B-Language
support	O
.	O
</s>
<s>
It	O
also	O
provides	O
support	O
for	O
the	O
e	O
verification	O
language	O
,	O
and	O
a	O
fast	O
SystemC	B-Language
simulation	O
kernel	O
.	O
</s>
<s>
ISE	O
Simulator	O
Xilinx	O
VHDL-93	B-Language
,	O
V2001	O
Xilinx	O
's	O
simulator	O
comes	O
bundled	O
with	O
the	O
ISE	O
Design	O
Suite	O
.	O
</s>
<s>
Metrics	O
Cloud	O
Simulator	O
Metrics	O
Technologies	O
SV2012	O
SystemVerilog	B-Language
simulator	O
used	O
on	O
the	O
Metrics	O
cloud	O
platform	O
.	O
</s>
<s>
Includes	O
all	O
the	O
standard	O
features	O
of	O
a	O
modern	O
SystemVerilog	B-Language
simulator	O
including	O
debug	O
,	O
APIs	O
,	O
language	O
and	O
testbench	O
support	O
.	O
</s>
<s>
ModelSim	B-Algorithm
and	I-Algorithm
Questa	I-Algorithm
( 	O
 '	O
big	O
3	O
 '	O
)	O
Mentor	O
Graphics	O
VHDL-1987	O
,	O
-1993	O
,	O
-2002	O
,	O
-2008	O
,	O
V2001	O
,	O
SV2005	O
,	O
SV2009	O
,	O
SV2012	O
,	O
SV2017	O
The	O
original	O
Modeltech	O
(	O
VHDL	B-Language
)	O
simulator	O
was	O
the	O
first	O
mixed-language	O
simulator	O
capable	O
of	O
simulating	O
VHDL	B-Language
and	O
Verilog	B-Language
design	O
entities	O
together	O
.	O
</s>
<s>
In	O
2003	O
,	O
ModelSim	B-Algorithm
5.8	O
was	O
the	O
first	O
simulator	O
to	O
begin	O
supporting	O
features	O
of	O
the	O
Accellera	O
SystemVerilog	B-Language
3.0	O
standard.http://www.sutherland-hdl.com/papers/2004	O
-Mentor-U2U-presentation_SystemVerilog_and_ModelSim.pdf	O
In	O
2005	O
Mentor	O
introduced	O
Questa	O
to	O
provide	O
high	O
performance	O
Verilog	B-Language
and	O
SystemVerilog	B-Language
simulation	O
and	O
expand	O
Verification	O
capabilities	O
to	O
more	O
advanced	O
methodologies	O
such	O
as	O
Assertion	O
Based	O
Verification	O
and	O
Functional	O
Coverage	O
.	O
</s>
<s>
Today	O
Questa	O
is	O
the	O
leading	O
high	O
performance	O
SystemVerilog	B-Language
and	O
Mixed	O
simulator	O
supporting	O
a	O
full	O
suite	O
of	O
methodologies	O
including	O
industry	O
standard	O
OVM	O
and	O
UVM	O
.	O
</s>
<s>
ModelSim	B-Algorithm
is	O
still	O
the	O
leading	O
simulator	O
for	O
FPGA	O
design	O
.	O
</s>
<s>
MPSim	O
Axiom	O
Design	O
Automation	O
V2001	O
,	O
V2005	O
,	O
SV2005	O
,	O
SV2009	O
MPsim	O
is	O
a	O
fast	O
compiled	O
simulator	O
with	O
full	O
support	O
for	O
Verilog	B-Language
,	O
SystemVerilog	B-Language
and	O
SystemC	B-Language
.	O
</s>
<s>
It	O
includes	O
Designer	O
,	O
integrated	O
Verilog	B-Language
and	O
SystemVerilog	B-Language
debugging	O
environment	O
and	O
has	O
built-in	O
support	O
for	O
multi-cpu	O
simulation	O
.	O
</s>
<s>
PureSpeed	O
Frontline	O
V1995	O
The	O
first	O
Verilog	B-Language
simulator	O
available	O
on	O
the	O
Windows	O
OS	O
.	O
</s>
<s>
Quartus	B-Language
II	I-Language
Simulator	I-Language
(	O
Qsim	O
)	O
Altera	O
VHDL-1993	O
,	O
V2001	O
,	O
SV2005	O
Altera	O
's	O
simulator	O
bundled	O
with	O
the	O
Quartus	B-Language
II	I-Language
design	O
software	O
in	O
release	O
11.1	O
and	O
later	O
.	O
</s>
<s>
Supports	O
Verilog	B-Language
,	O
VHDL	B-Language
and	O
AHDL	B-Language
.	O
</s>
<s>
SILOS	O
Silvaco	O
V2001	O
As	O
one	O
of	O
the	O
low-cost	O
interpreted	O
Verilog	B-Language
simulators	O
,	O
Silos	O
III	O
,	O
from	O
SimuCad	O
,	O
enjoyed	O
great	O
popularity	O
in	O
the	O
1990s	O
.	O
</s>
<s>
SIMILI	O
VHDL	B-Language
Symphony	O
EDA	O
VHDL-1993	O
Another	O
low-cost	O
VHDL	B-Language
simulator	O
with	O
graphical	B-Application
user	I-Application
interface	I-Application
and	O
integrated	O
waveform	O
viewer	O
.	O
</s>
<s>
SMASH	O
Dolphin	O
Integration	O
V1995	O
,	O
V2001	O
,	O
VHDL-1993	O
SMASH	O
is	O
a	O
mixed-signal	O
,	O
multi-language	O
simulator	O
for	O
IC	O
or	O
PCB	O
designs	O
.	O
</s>
<s>
It	O
uses	O
SPICE	B-Protocol
syntax	O
for	O
analog	O
descriptions	O
,	O
Verilog-HDL	B-Language
and	O
VHDL	B-Language
for	O
digital	O
,	O
Verilog-A/AMS	O
,	O
VHDL-AMS	O
and	O
ABCD	O
(	O
a	O
combination	O
of	O
SPICE	B-Protocol
and	O
C	O
)	O
for	O
analog	O
behavioral	O
,	O
and	O
C	O
for	O
DSP	O
algorithms	O
.	O
</s>
<s>
VCS	O
( 	O
 '	O
big	O
3	O
 '	O
)	O
Synopsys	O
VHDL-1987	O
,	O
-1993	O
,	O
-2002	O
,	O
-2008	O
,	O
V2001	O
,	O
SV2005	O
,	O
SV2009	O
,	O
SV2012	O
,	O
SV2017	O
Originally	O
developed	O
by	O
John	O
Sanguinetti	O
,	O
Peter	O
Eichenberger	O
and	O
Michael	O
McNamara	O
under	O
the	O
startup	O
company	O
Chronologic	O
Simulation	O
,	O
which	O
was	O
acquired	O
by	O
ViewLogic	O
Systems	O
in	O
1994	O
.	O
</s>
<s>
VCS	O
has	O
been	O
in	O
continuous	O
active	O
development	O
,	O
and	O
pioneered	O
compiled-code	O
simulation	O
,	O
native	O
testbench	O
and	O
SystemVerilog	B-Language
support	O
,	O
and	O
unified	O
compiler	O
technologies	O
.	O
</s>
<s>
Today	O
,	O
VCS	O
provides	O
comprehensive	O
support	O
for	O
all	O
functional	O
verification	O
methodologies	O
and	O
languages	O
(	O
including	O
VHDL	B-Language
,	O
Verilog	B-Language
,	O
SystemVerilog	B-Language
,	O
Verilog	B-Language
AMS	O
,	O
SystemC	B-Language
,	O
and	O
C/C	O
++	O
)	O
,	O
and	O
advanced	O
simulation	O
technologies	O
including	O
native	O
low	O
power	O
,	O
x-propagation	O
,	O
unreachability	O
analysis	O
,	O
and	O
fine-grained	O
parallelism	O
.	O
</s>
<s>
Verilogger	O
Extreme	O
is	O
a	O
newer	O
,	O
compiled-code	O
simulator	O
that	O
is	O
Verilog-2001	O
compliant	O
and	O
much	O
faster	O
than	O
Pro	O
.	O
</s>
<s>
Verilog-XL	O
Cadence	O
Design	O
Systems	O
V1995	O
The	O
original	O
Verilog	B-Language
simulator	O
,	O
Gateway	O
Design	O
's	O
Verilog-XL	O
was	O
the	O
first	O
(	O
and	O
only	O
,	O
for	O
a	O
time	O
)	O
Verilog	B-Language
simulator	O
to	O
be	O
qualified	O
for	O
ASIC	O
(	O
validation	O
)	O
sign-off	O
.	O
</s>
<s>
After	O
its	O
acquisition	O
by	O
Cadence	O
Design	O
Systems	O
,	O
Verilog-XL	O
changed	O
very	O
little	O
over	O
the	O
years	O
,	O
retaining	O
an	O
interpreted	O
language	O
engine	O
,	O
and	O
freezing	O
language-support	O
at	O
Verilog-1995	O
.	O
</s>
<s>
Cadence	O
recommends	O
Incisive	B-Algorithm
Enterprise	I-Algorithm
Simulator	I-Algorithm
for	O
new	O
design	O
projects	O
,	O
as	O
XL	O
no	O
longer	O
receives	O
active	O
development	O
.	O
</s>
<s>
Nevertheless	O
,	O
XL	O
continues	O
to	O
find	O
use	O
in	O
companies	O
with	O
large	O
codebases	O
of	O
legacy	O
Verilog	B-Language
.	O
</s>
<s>
Many	O
early	O
Verilog	B-Language
codebases	O
will	O
only	O
simulate	O
properly	O
in	O
Verilog-XL	O
,	O
due	O
to	O
variation	O
in	O
language	O
implementation	O
of	O
other	O
simulators	O
.	O
</s>
<s>
Xilinx	O
Simulator(XSIM )	O
Xilinx	O
VHDL-1993	O
,	O
-2002	O
(	O
subset	O
)	O
,	O
-2008	O
(	O
subset	O
)	O
,	O
https://support.xilinx.com/s/article/76459	O
V2001	O
,	O
V2005	O
,	O
SV2009	O
,	O
SV2012	O
,	O
SV2017	O
Xilinx	O
Simulator	O
(	O
XSIM	O
)	O
comes	O
as	O
part	O
of	O
the	O
Vivado	B-Algorithm
design	I-Algorithm
suite	I-Algorithm
.	O
</s>
<s>
It	O
is	O
a	O
compiled-language	O
simulator	O
that	O
supports	O
mixed	O
language	O
simulation	O
with	O
Verilog	B-Language
,	O
SystemVerilog	B-Language
,	O
VHDL	B-Language
and	O
SystemC	B-Language
language	O
.	O
</s>
<s>
It	O
supports	O
both	O
GUI	B-Application
and	O
batch	O
mode	O
via	O
TCL	O
script	O
and	O
allows	O
simulation	O
of	O
encrypted	O
IPs	O
.	O
</s>
<s>
Xilinx	O
Simulator	O
supports	O
SystemVerilog	B-Language
Direct	O
Programming	O
Interface	O
(	O
DPI	O
)	O
and	O
Xilinx	O
simulator	O
interface	O
(	O
XSI	O
)	O
to	O
connect	O
C/C	O
++	O
model	O
with	O
Xilinx	O
simulator	O
.	O
</s>
<s>
Some	O
commercial	O
proprietary	O
simulators	O
(	O
such	O
as	O
ModelSim	B-Algorithm
)	O
are	O
available	O
in	O
student	O
,	O
or	O
evaluation/demo	O
editions	O
.	O
</s>
<s>
+	O
List	B-Algorithm
of	I-Algorithm
Verilog	I-Algorithm
simulators	I-Algorithm
in	O
alphabetical	O
order	O
Simulator	O
name	O
License	O
Author/company	O
Supported	O
languages	O
Description	O
Cascade	O
BSD	O
VMware	O
Research	O
V2005	O
(	O
large	O
subset	O
)	O
Just-in-Time	O
Verilog	B-Language
simulator	O
and	O
compiler	O
for	O
FPGAs	O
allowing	O
to	O
instantly	O
run	O
both	O
synthesizable	O
and	O
unsynthesizable	O
Verilog	B-Language
on	O
hardwareCVCPerl	O
style	O
artistic	O
license	O
Tachyon	O
Design	O
AutomationV2001	O
,	O
V2005CVC	O
is	O
a	O
Verilog	B-Language
HDL	I-Language
compiled	O
simulator	O
.	O
</s>
<s>
Icarus	B-Application
Verilog	I-Application
GPL2+	O
Stephen	O
Williams	O
V1995	O
,	O
V2001	O
,	O
V2005	O
,	O
limited	O
SV2005/SV2009/SV2012	O
Also	O
known	O
as	O
iverilog	O
.	O
</s>
<s>
Good	O
support	O
for	O
Verilog	B-Language
2005	O
,	O
including	O
generate	O
statements	O
and	O
constant	O
functions.Isotel	O
Mixed	O
Signal	O
&	O
Domain	O
SimulationGPLngspice	O
,	O
Yosys	O
communities	O
and	O
IsotelV2005Open-source	O
mixed	O
signal	O
ngspice	B-Algorithm
simulator	O
in	O
combination	O
with	O
verilog	B-Language
synthesis	O
software	O
called	O
Yosys	O
and	O
Isotel	O
extension	O
for	O
embedded	O
C/C	O
++	O
(	O
or	O
other	O
)	O
co-simulation	O
.	O
</s>
<s>
LIFTING	O
A	O
.	O
Bosio	O
,	O
G	O
.	O
Di	O
Natale	O
(	O
LIRMM	O
)	O
V1995	O
LIFTING	O
(	O
LIRMM	O
Fault	O
Simulator	O
)	O
is	O
an	O
open-source	O
simulator	O
able	O
to	O
perform	O
both	O
logic	O
and	O
fault	O
simulation	O
for	O
single/multiple	O
stuck-at	O
faults	O
and	O
single	O
event	O
upset	O
(	O
SEU	O
)	O
on	O
digital	O
circuits	O
described	O
in	O
Verilog	B-Language
.	O
</s>
<s>
OSS	O
CVC	O
Perl	O
style	O
artistic	O
license	O
Tachyon	O
Design	O
Automation	O
V2001	O
,	O
V2005	O
CVC	O
is	O
a	O
Verilog	B-Language
HDL	I-Language
compiled	O
simulator	O
.	O
</s>
<s>
TkGate	O
GPL2+	O
Jeffery	O
P	O
.	O
Hansen	O
V1995	O
Event	O
driven	O
digital	O
circuit	O
editor	O
and	O
simulator	O
with	O
tcl/tk	O
GUI	B-Application
based	O
on	O
Verilog	B-Language
.	O
</s>
<s>
Includes	O
Verilog	B-Language
simulator	O
Verga	O
.	O
</s>
<s>
Verilator	B-Application
GPL3	O
Veripool	O
V1995	O
,	O
V2001	O
,	O
V2005	O
,	O
SV2005	O
,	O
SV2009	O
,	O
SV2012	O
,	O
SV2017	O
Verilator	B-Application
is	O
a	O
very	O
high	O
speed	O
open-source	O
simulator	O
that	O
compiles	O
Verilog	B-Language
to	O
multithreaded	O
C++	O
/SystemC	O
.	O
</s>
<s>
Verilator	B-Application
previously	O
required	O
that	O
testbench	O
code	O
be	O
written	O
as	O
synthesiable	O
RTL	O
,	O
or	O
as	O
a	O
C++	O
or	O
SystemC	B-Language
testbench	O
,	O
because	O
Verilator	B-Application
did	O
not	O
support	O
behavioral	O
Verilog	B-Language
nor	O
tasks	O
with	O
#	O
and	O
@	O
operators	O
.	O
</s>
<s>
Verilog	B-Language
Behavioral	O
Simulator	O
(	O
VBS	O
)	O
GPL	O
Lay	O
H	O
.	O
Tho	O
and	O
Jimen	O
Ching	O
V1995	O
Supports	O
functions	O
,	O
tasks	O
and	O
module	O
instantiation	O
.	O
</s>
<s>
It	O
has	O
a	O
few	O
features	O
,	O
but	O
this	O
release	O
has	O
enough	O
for	O
a	O
VLSI	O
student	O
to	O
use	O
and	O
learn	O
Verilog	B-Language
.	O
</s>
<s>
Supports	O
only	O
behavioral	O
constructs	O
of	O
Verilog	B-Language
and	O
minimal	O
simulation	O
constructs	O
such	O
as	O
'	O
initial	O
 '	O
statements	O
.	O
</s>
<s>
+	O
List	O
of	O
VHDL	B-Language
simulators	O
in	O
alphabetical	O
order	O
Simulator	O
name	O
License	O
Author/company	O
Supported	O
languages	O
Description	O
FreeHDL	O
GPL2+	O
VHDL-1987	O
,	O
VHDL-1993	O
A	O
project	O
to	O
develop	O
a	O
free	O
,	O
open	O
source	O
,	O
VHDL	B-Language
simulator	O
GHDL	O
GPL2+	O
Tristan	O
Gingold	O
VHDL-1987	O
,	O
VHDL-1993	O
,	O
VHDL-2002	O
,	O
partial	O
VHDL-2008	O
GHDL	O
is	O
a	O
complete	O
VHDL	B-Language
simulator	O
,	O
using	O
the	O
GCC	O
technology.Icarus	O
VerilogGPL2+Maciej	O
Sumiński	O
and	O
Stephen	O
WilliamsVHDL	O
preprocessor	O
added	O
that	O
converts	O
VHDL	B-Language
to	O
Verilog	B-Language
NVC	O
GPL-3.0-or-later	O
Nick	O
Gasson	O
and	O
contributors	O
IEEE	O
1076-2002	O
,	O
VHDL-1993	O
,	O
subset	O
of	O
VHDL-2008	O
NVC	O
is	O
a	O
GPLv3	O
VHDL	B-Language
compiler	O
and	O
simulator	O
aiming	O
for	O
IEEE	O
1076-2002	O
compliance	O
.	O
</s>
