<s>
This	O
is	O
a	O
list	O
of	O
microprocessors	O
designed	O
by	O
AMD	O
containing	O
a	O
3D	O
integrated	O
graphics	O
processing	O
unit	O
(	O
iGPU	O
)	O
,	O
including	O
those	O
under	O
the	O
AMD	B-Architecture
APU	I-Architecture
(	O
Accelerated	B-Architecture
Processing	I-Architecture
Unit	I-Architecture
)	O
product	O
series	O
.	O
</s>
<s>
GPU	O
:	O
TeraScale	O
2	O
(	O
Evergreen	O
)	O
;	O
all	O
A	O
and	O
E	O
series	O
models	O
feature	O
Redwood-class	O
integrated	O
graphics	O
on	O
die	O
(	O
BeaverCreek	O
for	O
the	O
dual-core	B-Architecture
variants	O
and	O
WinterPark	O
for	O
the	O
quad-core	B-Architecture
variants	O
)	O
.	O
</s>
<s>
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4a	O
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AMD64	B-Device
,	O
AMD-V	O
,	O
AES	B-Algorithm
,	O
AVX	B-General_Concept
,	O
AVX1.1	O
,	O
XOP	B-General_Concept
,	O
FMA3	B-General_Concept
,	O
FMA4	B-General_Concept
,	O
F16C	B-Device
,	O
ABM	O
,	O
BMI1	O
,	O
TBM	O
,	O
Turbo	B-Device
Core	I-Device
3.0	O
,	O
NX	B-General_Concept
bit	I-General_Concept
,	O
PowerNow	B-Device
!	I-Device
</s>
<s>
Cores/threadsFreq	O
.	O
</s>
<s>
Fabrication	B-Architecture
28nm	O
by	O
GlobalFoundries	O
.	O
</s>
<s>
Two	O
or	O
four	O
CPU	B-Architecture
cores	I-Architecture
based	O
on	O
the	O
Steamroller	B-Application
microarchitecture	O
.	O
</s>
<s>
Die	O
Size	O
:	O
,	O
2.41Billion	O
transistors	B-Application
.	O
</s>
<s>
L1	O
Cache	B-General_Concept
:	O
16	O
KB	O
Data	O
per	O
core	O
and	O
96	O
KB	O
Instructions	O
per	O
module	O
.	O
</s>
<s>
Three	O
to	O
eight	O
Compute	O
Units	O
(	O
CUs	O
)	O
based	O
on	O
GCN	B-Architecture
2nd	O
gen	O
microarchitecture	O
;	O
1	O
Compute	O
Unit	O
(	O
CU	O
)	O
consists	O
of	O
64	O
Unified	O
Shader	O
Processors	O
:	O
4	O
Texture	B-General_Concept
Mapping	I-General_Concept
Units	I-General_Concept
(	O
TMUs	O
)	O
:	O
1	O
Render	B-General_Concept
Output	I-General_Concept
Unit	I-General_Concept
(	O
ROPs	O
)	O
.	O
</s>
<s>
SIP	B-Architecture
blocks	I-Architecture
:	O
Unified	O
Video	O
Decoder	O
,	O
Video	O
Coding	O
Engine	O
,	O
TrueAudio	O
.	O
</s>
<s>
Integrated	O
custom	O
ARM	B-Application
Cortex-A5	I-Application
co-processor	O
with	O
TrustZone	O
Security	O
Extensions	O
in	O
select	O
APU	O
models	O
,	O
except	O
the	O
Performance	O
APU	O
models	O
.	O
</s>
<s>
Cores/threadsFreq	O
.	O
</s>
<s>
PowerNow	B-Device
!	I-Device
</s>
<s>
Up	O
to	O
4	O
Steamroller	B-Application
x86	O
CPU	B-Architecture
cores	I-Architecture
with	O
4MB	O
of	O
L2	O
cache	B-General_Concept
.	O
</s>
<s>
L1	O
cache	B-General_Concept
:	O
64KB	O
(	O
32KB	O
data	O
+	O
32KB	O
instruction	O
)	O
per	O
core	O
.	O
</s>
<s>
L2	O
cache	B-General_Concept
:	O
512KB	O
per	O
core	O
.	O
</s>
<s>
L1	O
cache	B-General_Concept
:	O
64KB	O
(	O
32KB	O
data	O
+	O
32KB	O
instruction	O
)	O
per	O
core	O
.	O
</s>
<s>
L2	O
cache	B-General_Concept
:	O
512KB	O
per	O
core	O
.	O
</s>
<s>
L1	O
cache	B-General_Concept
:	O
64KB	O
(	O
32KB	O
data	O
+	O
32KB	O
instruction	O
)	O
per	O
core	O
.	O
</s>
<s>
L2	O
cache	B-General_Concept
:	O
512KB	O
per	O
core	O
.	O
</s>
<s>
PowerNow	B-Device
!	I-Device
</s>
<s>
PowerNow	B-Device
!	I-Device
</s>
<s>
PowerNow	B-Device
!	I-Device
</s>
<s>
CPU	O
GPU	O
DDR3	O
Memory	O
support	O
TDP	B-General_Concept
(	O
W	O
)	O
Part	O
number	O
Cores	B-Architecture
(	O
threads	B-Operating_System
)	O
 [ FPUs ] 	O
Clock	O
(	O
GHz	O
)	O
Turbo	O
(	O
GHz	O
)	O
Cache	B-General_Concept
Model	O
Config	O
Clock	O
(	O
MHz	O
)	O
Turbo	O
(	O
MHz	O
)	O
L1	O
L2	O
(	O
MB	O
)	O
L3	O
Q2	O
2014	O
28	O
nm	O
ML-A1	O
2	O
(	O
2	O
)	O
1.35	O
rowspan	O
=	O
5	O
32	O
KB	O
inst	O
.	O
</s>
<s>
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4a	O
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AVX	B-General_Concept
,	O
F16C	B-Device
,	O
CLMUL	B-Device
,	O
AES	B-Algorithm
,	O
MOVBE	O
(	O
Move	O
Big-Endian	O
instruction	O
)	O
,	O
XSAVE/XSAVEOPT	O
,	O
ABM	O
,	O
BMI1	O
,	O
AMD-V	O
support	O
.	O
</s>
<s>
GPU	O
microarchitecture	O
:	O
Graphics	B-Architecture
Core	I-Architecture
Next	I-Architecture
(	O
GCN	B-Architecture
)	O
with	O
Unified	O
Video	O
Decoder	O
3	O
(	O
H.264	O
,	O
VC-1	O
,	O
MPEG2	O
,	O
etc	O
.	O
)	O
</s>
<s>
Some	O
notable	O
examples	O
of	O
semi-custom	O
chips	O
that	O
have	O
come	O
from	O
this	O
sector	O
include	O
the	O
chips	O
from	O
the	O
PlayStation	O
4	O
and	O
Xbox	B-Device
One	I-Device
.	O
</s>
