<s>
Athlon	B-Architecture
is	O
the	O
name	O
of	O
a	O
family	O
of	O
CPUs	O
designed	O
by	O
AMD	O
,	O
targeted	O
mostly	O
at	O
the	O
desktop	O
market	O
.	O
</s>
<s>
It	O
has	O
been	O
largely	O
unused	O
as	O
just	O
"	O
Athlon	B-Architecture
"	O
since	O
2001	O
when	O
AMD	O
started	O
naming	O
its	O
processors	O
Athlon	B-Architecture
XP	O
,	O
but	O
in	O
2008	O
began	O
referring	O
to	O
single	O
core	O
64-bit	O
processors	O
from	O
the	O
AMD	B-Device
Athlon	I-Device
X2	I-Device
and	O
AMD	O
Phenom	O
product	O
lines	O
.	O
</s>
<s>
Later	O
the	O
name	O
began	O
being	O
used	O
for	O
some	O
APUs	B-Architecture
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
Enhanced	B-General_Concept
3DNow	I-General_Concept
!	I-General_Concept
</s>
<s>
L2	O
cache	B-General_Concept
runs	O
with	O
50%	O
(	O
up	O
to	O
700MHz	O
)	O
,	O
40%	O
(	O
up	O
to	O
850MHz	O
)	O
or	O
33%	O
(	O
up	O
to	O
1000MHz	O
)	O
of	O
CPU	O
speed	O
.	O
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
Enhanced	B-General_Concept
3DNow	I-General_Concept
!	I-General_Concept
</s>
<s>
All	O
models	O
support	O
:	O
MMX	B-Architecture
,	O
Enhanced	B-General_Concept
3DNow	I-General_Concept
!	I-General_Concept
</s>
<s>
MMX	B-Architecture
,	O
SSE	B-General_Concept
,	O
SSE2	B-General_Concept
,	O
SSE3	B-General_Concept
,	O
SSSE3	B-General_Concept
,	O
SSE4a	O
,	O
SSE4.1	O
,	O
SSE4.2	O
,	O
AMD64	B-Device
,	O
AMD-V	O
,	O
AES	B-Algorithm
,	O
AVX	B-General_Concept
,	O
AVX1.1	O
,	O
XOP	B-General_Concept
,	O
FMA3	O
,	O
FMA4	O
,	O
F16C	B-Device
,	O
ABM	O
,	O
BMI1	O
,	O
TBM	O
,	O
Turbo	B-Device
Core	I-Device
3.0	O
,	O
NX	B-General_Concept
bit	I-General_Concept
,	O
PowerNow	B-Device
!	I-Device
</s>
<s>
Cores/threadsFreq	O
.	O
</s>
<s>
(	O
MB	O
)	O
L3	O
Athlon	B-Architecture
X4	O
530	O
?	O
</s>
<s>
Fabrication	B-Architecture
28nm	O
by	O
GlobalFoundries	O
.	O
</s>
<s>
Two	O
or	O
four	O
CPU	B-Architecture
cores	I-Architecture
based	O
on	O
the	O
Steamroller	B-Application
microarchitecture	O
.	O
</s>
<s>
L1	O
Cache	B-General_Concept
:	O
16	O
KB	O
Data	O
per	O
core	O
and	O
96	O
KB	O
Instructions	O
per	O
module	O
.	O
</s>
<s>
Cores/threadsClock	O
(	O
GHz	O
)	O
Cache	B-General_Concept
Base	O
Turbo	O
L1	O
L2	O
Athlon	B-Architecture
X4	O
835	O
?	O
</s>
