<s>
In	O
computing	O
,	O
a	O
linear-feedback	B-Architecture
shift	I-Architecture
register	I-Architecture
(	O
LFSR	B-Architecture
)	O
is	O
a	O
shift	B-General_Concept
register	I-General_Concept
whose	O
input	O
bit	O
is	O
a	O
linear	O
function	O
of	O
its	O
previous	O
state	B-Application
.	O
</s>
<s>
Thus	O
,	O
an	O
LFSR	B-Architecture
is	O
most	O
often	O
a	O
shift	B-General_Concept
register	I-General_Concept
whose	O
input	O
bit	O
is	O
driven	O
by	O
the	O
XOR	O
of	O
some	O
bits	O
of	O
the	O
overall	O
shift	B-General_Concept
register	I-General_Concept
value	O
.	O
</s>
<s>
The	O
initial	O
value	O
of	O
the	O
LFSR	B-Architecture
is	O
called	O
the	O
seed	O
,	O
and	O
because	O
the	O
operation	O
of	O
the	O
register	O
is	O
deterministic	O
,	O
the	O
stream	O
of	O
values	O
produced	O
by	O
the	O
register	O
is	O
completely	O
determined	O
by	O
its	O
current	O
(	O
or	O
previous	O
)	O
state	B-Application
.	O
</s>
<s>
However	O
,	O
an	O
LFSR	B-Architecture
with	O
a	O
well-chosen	O
feedback	O
function	O
can	O
produce	O
a	O
sequence	O
of	O
bits	O
that	O
appears	O
random	O
and	O
has	O
a	O
very	O
long	O
cycle	O
.	O
</s>
<s>
Applications	O
of	O
LFSRs	B-Architecture
include	O
generating	O
pseudo-random	B-Error_Name
numbers	I-Error_Name
,	O
pseudo-noise	O
sequences	O
,	O
fast	O
digital	O
counters	O
,	O
and	O
whitening	O
sequences	O
.	O
</s>
<s>
Both	O
hardware	O
and	O
software	O
implementations	O
of	O
LFSRs	B-Architecture
are	O
common	O
.	O
</s>
<s>
The	O
mathematics	O
of	O
a	O
cyclic	O
redundancy	O
check	O
,	O
used	O
to	O
provide	O
a	O
quick	O
check	O
against	O
transmission	O
errors	O
,	O
are	O
closely	O
related	O
to	O
those	O
of	O
an	O
LFSR	B-Architecture
.	O
</s>
<s>
In	O
general	O
,	O
the	O
arithmetics	O
behind	O
LFSRs	B-Architecture
makes	O
them	O
very	O
elegant	O
as	O
an	O
object	O
to	O
study	O
and	O
implement	O
.	O
</s>
<s>
The	O
bit	O
positions	O
that	O
affect	O
the	O
next	O
state	B-Application
are	O
called	O
the	O
taps	O
.	O
</s>
<s>
The	O
rightmost	O
bit	O
of	O
the	O
LFSR	B-Architecture
is	O
called	O
the	O
output	O
bit	O
.	O
</s>
<s>
The	O
bits	O
in	O
the	O
LFSR	B-Architecture
state	B-Application
that	O
influence	O
the	O
input	O
are	O
called	O
taps	O
.	O
</s>
<s>
A	O
maximum-length	O
LFSR	B-Architecture
produces	O
an	O
m-sequence	O
(	O
i.e.	O
,	O
it	O
cycles	O
through	O
all	O
possible	O
2m−1	O
states	O
within	O
the	O
shift	B-General_Concept
register	I-General_Concept
except	O
the	O
state	B-Application
where	O
all	O
bits	O
are	O
zero	O
)	O
,	O
unless	O
it	O
contains	O
all	O
zeros	O
,	O
in	O
which	O
case	O
it	O
will	O
never	O
change	O
.	O
</s>
<s>
As	O
an	O
alternative	O
to	O
the	O
XOR-based	O
feedback	O
in	O
an	O
LFSR	B-Architecture
,	O
one	O
can	O
also	O
use	O
XNOR	O
.	O
</s>
<s>
This	O
function	O
is	O
an	O
affine	B-Algorithm
map	I-Algorithm
,	O
not	O
strictly	O
a	O
linear	B-Architecture
map	I-Architecture
,	O
but	O
it	O
results	O
in	O
an	O
equivalent	O
polynomial	B-Architecture
counter	I-Architecture
whose	O
state	B-Application
is	O
the	O
complement	O
of	O
the	O
state	B-Application
of	O
an	O
LFSR	B-Architecture
.	O
</s>
<s>
A	O
state	B-Application
with	O
all	O
ones	O
is	O
illegal	O
when	O
using	O
an	O
XNOR	O
feedback	O
,	O
in	O
the	O
same	O
way	O
as	O
a	O
state	B-Application
with	O
all	O
zeroes	O
is	O
illegal	O
when	O
using	O
XOR	O
.	O
</s>
<s>
This	O
state	B-Application
is	O
considered	O
illegal	O
because	O
the	O
counter	O
would	O
remain	O
"	O
locked-up	O
"	O
in	O
this	O
state	B-Application
.	O
</s>
<s>
This	O
method	O
can	O
be	O
advantageous	O
in	O
hardware	O
LFSRs	B-Architecture
using	O
flip-flops	O
that	O
start	O
in	O
a	O
zero	O
state	B-Application
,	O
as	O
it	O
does	O
not	O
start	O
in	O
a	O
lockup	O
state	B-Application
,	O
meaning	O
that	O
the	O
register	O
does	O
not	O
need	O
to	O
be	O
seeded	O
in	O
order	O
to	O
begin	O
operation	O
.	O
</s>
<s>
The	O
sequence	O
of	O
numbers	O
generated	O
by	O
an	O
LFSR	B-Architecture
or	O
its	O
XNOR	O
counterpart	O
can	O
be	O
considered	O
a	O
binary	O
numeral	O
system	O
just	O
as	O
valid	O
as	O
Gray	B-Device
code	I-Device
or	O
the	O
natural	O
binary	O
code	O
.	O
</s>
<s>
The	O
arrangement	O
of	O
taps	O
for	O
feedback	O
in	O
an	O
LFSR	B-Architecture
can	O
be	O
expressed	O
in	O
finite	O
field	O
arithmetic	O
as	O
a	O
polynomial	O
mod	O
2	O
.	O
</s>
<s>
The	O
LFSR	B-Architecture
is	O
maximal-length	O
if	O
and	O
only	O
if	O
the	O
corresponding	O
feedback	O
polynomial	O
is	O
primitive	O
over	O
the	O
Galois	O
field	O
GF(2 )	O
.	O
</s>
<s>
Tables	O
of	O
primitive	O
polynomials	O
from	O
which	O
maximum-length	O
LFSRs	B-Architecture
can	O
be	O
constructed	O
are	O
given	O
below	O
and	O
in	O
the	O
references	O
.	O
</s>
<s>
There	O
can	O
be	O
more	O
than	O
one	O
maximum-length	O
tap	O
sequence	O
for	O
a	O
given	O
LFSR	B-Architecture
length	O
.	O
</s>
<s>
If	O
the	O
tap	O
sequence	O
in	O
an	O
n-bit	O
LFSR	B-Architecture
is	O
,	O
where	O
the	O
0	O
corresponds	O
to	O
the	O
x0	O
=	O
1	O
term	O
,	O
then	O
the	O
corresponding	O
"	O
mirror	O
"	O
sequence	O
is	O
.	O
</s>
<s>
An	O
example	O
in	O
C	B-Language
is	O
below	O
:	O
</s>
<s>
This	O
LFSR	B-Architecture
configuration	O
is	O
also	O
known	O
as	O
standard	O
,	O
many-to-one	O
or	O
external	O
XOR	O
gates	O
.	O
</s>
<s>
Named	O
after	O
the	O
French	O
mathematician	O
Évariste	O
Galois	O
,	O
an	O
LFSR	B-Architecture
in	O
Galois	O
configuration	O
,	O
which	O
is	O
also	O
known	O
as	O
modular	O
,	O
internal	O
XORs	O
,	O
or	O
one-to-many	O
LFSR	B-Architecture
,	O
is	O
an	O
alternate	O
structure	O
that	O
can	O
generate	O
the	O
same	O
output	O
stream	O
as	O
a	O
conventional	O
LFSR	B-Architecture
(	O
but	O
offset	O
in	O
time	O
)	O
.	O
</s>
<s>
To	O
generate	O
the	O
same	O
output	O
stream	O
,	O
the	O
order	O
of	O
the	O
taps	O
is	O
the	O
counterpart	O
(	O
see	O
above	O
)	O
of	O
the	O
order	O
for	O
the	O
conventional	O
LFSR	B-Architecture
,	O
otherwise	O
the	O
stream	O
will	O
be	O
in	O
reverse	O
.	O
</s>
<s>
Note	O
that	O
the	O
internal	O
state	B-Application
of	O
the	O
LFSR	B-Architecture
is	O
not	O
necessarily	O
the	O
same	O
.	O
</s>
<s>
Galois	O
LFSRs	B-Architecture
do	O
not	O
concatenate	O
every	O
tap	O
to	O
produce	O
the	O
new	O
input	O
(	O
the	O
XORing	O
is	O
done	O
within	O
the	O
LFSR	B-Architecture
,	O
and	O
no	O
XOR	O
gates	O
are	O
run	O
in	O
serial	O
,	O
therefore	O
the	O
propagation	O
times	O
are	O
reduced	O
to	O
that	O
of	O
one	O
XOR	O
rather	O
than	O
a	O
whole	O
chain	O
)	O
,	O
thus	O
it	O
is	O
possible	O
for	O
each	O
tap	O
to	O
be	O
computed	O
in	O
parallel	O
,	O
increasing	O
the	O
speed	O
of	O
execution	O
.	O
</s>
<s>
In	O
a	O
software	O
implementation	O
of	O
an	O
LFSR	B-Architecture
,	O
the	O
Galois	O
form	O
is	O
more	O
efficient	O
,	O
as	O
the	O
XOR	O
operations	O
can	O
be	O
implemented	O
a	O
word	O
at	O
a	O
time	O
:	O
only	O
the	O
output	O
bit	O
must	O
be	O
examined	O
individually	O
.	O
</s>
<s>
Below	O
is	O
a	O
C	B-Language
code	O
example	O
for	O
the	O
16-bit	O
maximal-period	O
Galois	O
LFSR	B-Architecture
example	O
in	O
the	O
figure	O
:	O
</s>
<s>
In	O
addition	O
,	O
the	O
left-shifting	O
variant	O
may	O
produce	O
even	O
better	O
code	O
,	O
as	O
the	O
msb	O
is	O
the	O
carry	B-Algorithm
from	O
the	O
addition	O
of	O
lfsr	B-Architecture
to	O
itself	O
.	O
</s>
<s>
Binary	O
Galois	O
LFSRs	B-Architecture
like	O
the	O
ones	O
shown	O
above	O
can	O
be	O
generalized	O
to	O
any	O
q-ary	O
alphabet	O
{	O
0	O
,	O
1	O
,	O
...	O
,	O
q−1}	O
(	O
e.g.	O
,	O
for	O
binary	O
,	O
q	O
=	O
2	O
,	O
and	O
the	O
alphabet	O
is	O
simply	O
{	O
0	O
,	O
1}	O
)	O
.	O
</s>
<s>
Given	O
an	O
appropriate	O
tap	O
configuration	O
,	O
such	O
LFSRs	B-Architecture
can	O
be	O
used	O
to	O
generate	O
Galois	O
fields	O
for	O
arbitrary	O
prime	O
values	O
of	O
q	O
.	O
</s>
<s>
As	O
shown	O
by	O
George	O
Marsaglia	O
and	O
further	O
analysed	O
by	O
Richard	O
P	O
.	O
Brent	O
,	O
linear	B-Architecture
feedback	I-Architecture
shift	I-Architecture
registers	I-Architecture
can	O
be	O
implemented	O
using	O
XOR	O
and	O
Shift	O
operations	O
.	O
</s>
<s>
Below	O
is	O
a	O
C	B-Language
code	O
example	O
for	O
a	O
16-bit	O
maximal-period	O
Xorshift	O
LFSR	B-Architecture
using	O
the	O
7	O
,	O
9	O
,	O
13	O
triplet	O
from	O
John	O
Metcalf	O
:	O
</s>
<s>
Binary	O
LFSRs	B-Architecture
of	O
both	O
Fibonacci	O
and	O
Galois	O
configurations	O
can	O
be	O
expressed	O
as	O
linear	O
functions	O
using	O
matrices	O
in	O
(	O
see	O
GF(2 )	O
)	O
.	O
</s>
<s>
The	O
following	O
table	O
lists	O
examples	O
of	O
maximal-length	O
feedback	O
polynomials	O
(	O
primitive	O
polynomials	O
)	O
for	O
shift-register	B-General_Concept
lengths	O
up	O
to	O
24	O
.	O
</s>
<s>
The	O
formalism	O
for	O
maximum-length	O
LFSRs	B-Architecture
was	O
developed	O
by	O
Solomon	O
W	O
.	O
Golomb	O
in	O
his	O
1967	O
book	O
.	O
</s>
<s>
The	O
number	O
of	O
different	O
primitive	O
polynomials	O
grows	O
exponentially	O
with	O
shift-register	B-General_Concept
length	O
and	O
can	O
be	O
calculated	O
exactly	O
using	O
Euler	O
's	O
totient	O
function	O
.	O
</s>
<s>
In	O
one	O
period	O
of	O
a	O
maximal	O
LFSR	B-Architecture
,	O
2n−1	O
runs	O
occur	O
(	O
in	O
the	O
example	O
above	O
,	O
the	O
3-bit	O
LFSR	B-Architecture
has	O
4	O
runs	O
)	O
.	O
</s>
<s>
LFSR	B-Architecture
output	O
streams	O
are	O
deterministic	O
.	O
</s>
<s>
If	O
the	O
present	O
state	B-Application
and	O
the	O
positions	O
of	O
the	O
XOR	O
gates	O
in	O
the	O
LFSR	B-Architecture
are	O
known	O
,	O
the	O
next	O
state	B-Application
can	O
be	O
predicted	O
.	O
</s>
<s>
With	O
maximal-length	O
LFSRs	B-Architecture
,	O
it	O
is	O
much	O
easier	O
to	O
compute	O
the	O
next	O
state	B-Application
,	O
as	O
there	O
are	O
only	O
an	O
easily	O
limited	O
number	O
of	O
them	O
for	O
each	O
length	O
.	O
</s>
<s>
The	O
output	O
stream	O
is	O
reversible	O
;	O
an	O
LFSR	B-Architecture
with	O
mirrored	O
taps	O
will	O
cycle	O
through	O
the	O
output	O
sequence	O
in	O
reverse	O
order	O
.	O
</s>
<s>
Thus	O
an	O
LFSR	B-Architecture
of	O
length	O
n	O
cannot	O
be	O
used	O
to	O
generate	O
all	O
2n	O
values	O
.	O
</s>
<s>
LFSRs	B-Architecture
can	O
be	O
implemented	O
in	O
hardware	O
,	O
and	O
this	O
makes	O
them	O
useful	O
in	O
applications	O
that	O
require	O
very	O
fast	O
generation	O
of	O
a	O
pseudo-random	B-Error_Name
sequence	I-Error_Name
,	O
such	O
as	O
direct-sequence	B-Device
spread	I-Device
spectrum	I-Device
radio	O
.	O
</s>
<s>
LFSRs	B-Architecture
have	O
also	O
been	O
used	O
for	O
generating	O
an	O
approximation	O
of	O
white	O
noise	O
in	O
various	O
programmable	O
sound	O
generators	O
.	O
</s>
<s>
The	O
repeating	O
sequence	O
of	O
states	O
of	O
an	O
LFSR	B-Architecture
allows	O
it	O
to	O
be	O
used	O
as	O
a	O
clock	O
divider	O
or	O
as	O
a	O
counter	O
when	O
a	O
non-binary	O
sequence	O
is	O
acceptable	O
,	O
as	O
is	O
often	O
the	O
case	O
where	O
computer	O
index	O
or	O
framing	O
locations	O
need	O
to	O
be	O
machine-readable	O
.	O
</s>
<s>
LFSR	B-Architecture
counters	O
have	O
simpler	O
feedback	O
logic	O
than	O
natural	O
binary	O
counters	O
or	O
Gray-code	O
counters	O
,	O
and	O
therefore	O
can	O
operate	O
at	O
higher	O
clock	O
rates	O
.	O
</s>
<s>
However	O
,	O
it	O
is	O
necessary	O
to	O
ensure	O
that	O
the	O
LFSR	B-Architecture
never	O
enters	O
an	O
all-zeros	O
state	B-Application
,	O
for	O
example	O
by	O
presetting	O
it	O
at	O
start-up	O
to	O
any	O
other	O
state	B-Application
in	O
the	O
sequence	O
.	O
</s>
<s>
The	O
table	O
of	O
primitive	O
polynomials	O
shows	O
how	O
LFSRs	B-Architecture
can	O
be	O
arranged	O
in	O
Fibonacci	O
or	O
Galois	O
form	O
to	O
give	O
maximal	O
periods	O
.	O
</s>
<s>
One	O
can	O
obtain	O
any	O
other	O
period	O
by	O
adding	O
to	O
an	O
LFSR	B-Architecture
that	O
has	O
a	O
longer	O
period	O
some	O
logic	O
that	O
shortens	O
the	O
sequence	O
by	O
skipping	O
some	O
states	O
.	O
</s>
<s>
LFSRs	B-Architecture
have	O
long	O
been	O
used	O
as	O
pseudo-random	B-Algorithm
number	I-Algorithm
generators	I-Algorithm
for	O
use	O
in	O
stream	B-Algorithm
ciphers	I-Algorithm
,	O
due	O
to	O
the	O
ease	O
of	O
construction	O
from	O
simple	O
electromechanical	O
or	O
electronic	O
circuits	O
,	O
long	O
periods	O
,	O
and	O
very	O
uniformly	O
distributed	O
output	O
streams	O
.	O
</s>
<s>
However	O
,	O
an	O
LFSR	B-Architecture
is	O
a	O
linear	O
system	O
,	O
leading	O
to	O
fairly	O
easy	O
cryptanalysis	O
.	O
</s>
<s>
For	O
example	O
,	O
given	O
a	O
stretch	O
of	O
known	O
plaintext	O
and	O
corresponding	O
ciphertext	O
,	O
an	O
attacker	O
can	O
intercept	O
and	O
recover	O
a	O
stretch	O
of	O
LFSR	B-Architecture
output	O
stream	O
used	O
in	O
the	O
system	O
described	O
,	O
and	O
from	O
that	O
stretch	O
of	O
the	O
output	O
stream	O
can	O
construct	O
an	O
LFSR	B-Architecture
of	O
minimal	O
size	O
that	O
simulates	O
the	O
intended	O
receiver	O
by	O
using	O
the	O
Berlekamp-Massey	B-Algorithm
algorithm	I-Algorithm
.	O
</s>
<s>
This	O
LFSR	B-Architecture
can	O
then	O
be	O
fed	O
the	O
intercepted	O
stretch	O
of	O
output	O
stream	O
to	O
recover	O
the	O
remaining	O
plaintext	O
.	O
</s>
<s>
Three	O
general	O
methods	O
are	O
employed	O
to	O
reduce	O
this	O
problem	O
in	O
LFSR-based	O
stream	B-Algorithm
ciphers	I-Algorithm
:	O
</s>
<s>
Non-linear	O
combination	O
of	O
several	O
bits	O
from	O
the	O
LFSR	B-Architecture
state	B-Application
;	O
</s>
<s>
Non-linear	O
combination	O
of	O
the	O
output	O
bits	O
of	O
two	O
or	O
more	O
LFSRs	B-Architecture
(	O
see	O
also	O
:	O
shrinking	B-Algorithm
generator	I-Algorithm
)	O
;	O
or	O
using	O
Evolutionary	B-Algorithm
algorithm	I-Algorithm
to	O
introduce	O
non-linearity	O
.	O
</s>
<s>
Irregular	O
clocking	O
of	O
the	O
LFSR	B-Architecture
,	O
as	O
in	O
the	O
alternating	B-Algorithm
step	I-Algorithm
generator	I-Algorithm
.	O
</s>
<s>
Important	O
LFSR-based	O
stream	B-Algorithm
ciphers	I-Algorithm
include	O
A5/1	B-Algorithm
and	O
A5/2	B-Algorithm
,	O
used	O
in	O
GSM	O
cell	O
phones	O
,	O
E0	B-Algorithm
,	O
used	O
in	O
Bluetooth	B-Protocol
,	O
and	O
the	O
shrinking	B-Algorithm
generator	I-Algorithm
.	O
</s>
<s>
The	O
A5/2	B-Algorithm
cipher	B-Algorithm
has	O
been	O
broken	O
and	O
both	O
A5/1	B-Algorithm
and	O
E0	B-Algorithm
have	O
serious	O
weaknesses	O
.	O
</s>
<s>
The	O
linear	B-Architecture
feedback	I-Architecture
shift	I-Architecture
register	I-Architecture
has	O
a	O
strong	O
relationship	O
to	O
linear	B-Algorithm
congruential	I-Algorithm
generators	I-Algorithm
.	O
</s>
<s>
LFSRs	B-Architecture
are	O
used	O
in	O
circuit	O
testing	O
for	O
test-pattern	O
generation	O
(	O
for	O
exhaustive	O
testing	O
,	O
pseudo-random	B-Error_Name
testing	O
or	O
pseudo-exhaustive	O
testing	O
)	O
and	O
for	O
signature	O
analysis	O
.	O
</s>
<s>
Complete	O
LFSR	B-Architecture
are	O
commonly	O
used	O
as	O
pattern	O
generators	O
for	O
exhaustive	O
testing	O
,	O
since	O
they	O
cover	O
all	O
possible	O
inputs	O
for	O
an	O
n-input	O
circuit	O
.	O
</s>
<s>
Maximal-length	O
LFSRs	B-Architecture
and	O
weighted	O
LFSRs	B-Architecture
are	O
widely	O
used	O
as	O
pseudo-random	B-Error_Name
test-pattern	O
generators	O
for	O
pseudo-random	B-Error_Name
test	O
applications	O
.	O
</s>
<s>
BIST	O
is	O
accomplished	O
with	O
a	O
multiple-input	O
signature	O
register	O
(	O
MISR	O
or	O
MSR	O
)	O
,	O
which	O
is	O
a	O
type	O
of	O
LFSR	B-Architecture
.	O
</s>
<s>
A	O
standard	O
LFSR	B-Architecture
has	O
a	O
single	O
XOR	O
or	O
XNOR	O
gate	O
,	O
where	O
the	O
input	O
of	O
the	O
gate	O
is	O
connected	O
to	O
several	O
"	O
taps	O
"	O
and	O
the	O
output	O
is	O
connected	O
to	O
the	O
input	O
of	O
the	O
first	O
flip-flop	O
.	O
</s>
<s>
Consequently	O
,	O
the	O
next	O
state	B-Application
of	O
the	O
MISR	O
depends	O
on	O
the	O
last	O
several	O
states	O
opposed	O
to	O
just	O
the	O
current	O
state	B-Application
.	O
</s>
<s>
Recent	O
applications	O
are	O
proposing	O
set-reset	O
flip-flops	O
as	O
"	O
taps	O
"	O
of	O
the	O
LFSR	B-Architecture
.	O
</s>
<s>
This	O
allows	O
the	O
BIST	O
system	O
to	O
optimise	O
storage	O
,	O
since	O
set-reset	O
flip-flops	O
can	O
save	O
the	O
initial	O
seed	O
to	O
generate	O
the	O
whole	O
stream	O
of	O
bits	O
from	O
the	O
LFSR	B-Architecture
.	O
</s>
<s>
When	O
the	O
LFSR	B-Architecture
runs	O
at	O
the	O
same	O
bit	O
rate	O
as	O
the	O
transmitted	O
symbol	O
stream	O
,	O
this	O
technique	O
is	O
referred	O
to	O
as	O
scrambling	O
.	O
</s>
<s>
When	O
the	O
LFSR	B-Architecture
runs	O
considerably	O
faster	O
than	O
the	O
symbol	O
stream	O
,	O
the	O
LFSR-generated	O
bit	O
sequence	O
is	O
called	O
chipping	O
code	O
.	O
</s>
<s>
The	O
chipping	O
code	O
is	O
combined	O
with	O
the	O
data	O
using	O
exclusive	O
or	O
before	O
transmitting	O
using	O
binary	O
phase-shift	B-General_Concept
keying	I-General_Concept
or	O
a	O
similar	O
modulation	O
method	O
.	O
</s>
<s>
The	O
resulting	O
signal	O
has	O
a	O
higher	O
bandwidth	O
than	O
the	O
data	O
,	O
and	O
therefore	O
this	O
is	O
a	O
method	O
of	O
spread-spectrum	B-Architecture
communication	O
.	O
</s>
<s>
When	O
used	O
only	O
for	O
the	O
spread-spectrum	B-Architecture
property	O
,	O
this	O
technique	O
is	O
called	O
direct-sequence	B-Device
spread	I-Device
spectrum	I-Device
;	O
when	O
used	O
to	O
distinguish	O
several	O
signals	O
transmitted	O
in	O
the	O
same	O
channel	O
at	O
the	O
same	O
time	O
and	O
frequency	O
,	O
it	O
is	O
called	O
code-division	B-Protocol
multiple	I-Protocol
access	I-Protocol
.	O
</s>
<s>
Neither	O
scheme	O
should	O
be	O
confused	O
with	O
encryption	O
or	O
encipherment	B-Algorithm
;	O
scrambling	O
and	O
spreading	O
with	O
LFSRs	B-Architecture
do	O
not	O
protect	O
the	O
information	O
from	O
eavesdropping	O
.	O
</s>
<s>
Other	O
digital	O
communications	O
systems	O
using	O
LFSRs	B-Architecture
:	O
</s>
<s>
All	O
current	O
systems	O
use	O
LFSR	B-Architecture
outputs	O
to	O
generate	O
some	O
or	O
all	O
of	O
their	O
ranging	O
codes	O
(	O
as	O
the	O
chipping	O
code	O
for	O
CDMA	B-Protocol
or	O
DSSS	B-Device
)	O
or	O
to	O
modulate	O
the	O
carrier	O
without	O
data	O
(	O
like	O
GPSL2CL	O
ranging	O
code	O
)	O
.	O
</s>
<s>
GLONASS	O
also	O
uses	O
frequency-division	O
multiple	O
access	O
combined	O
with	O
DSSS	B-Device
.	O
</s>
<s>
LFSRs	B-Architecture
are	O
also	O
used	O
in	O
radio	O
jamming	O
systems	O
to	O
generate	O
pseudo-random	B-Error_Name
noise	O
to	O
raise	O
the	O
noise	O
floor	O
of	O
a	O
target	O
communication	O
system	O
.	O
</s>
<s>
The	O
German	O
time	O
signal	O
DCF77	O
,	O
in	O
addition	O
to	O
amplitude	O
keying	O
,	O
employs	O
phase-shift	B-General_Concept
keying	I-General_Concept
driven	O
by	O
a	O
9-stage	O
LFSR	B-Architecture
to	O
increase	O
the	O
accuracy	O
of	O
received	O
time	O
and	O
the	O
robustness	O
of	O
the	O
data	O
stream	O
in	O
the	O
presence	O
of	O
noise	O
.	O
</s>
