<s>
LatticeMico32	B-Device
is	O
a	O
32-bit	O
microprocessor	B-Architecture
reduced	B-Architecture
instruction	I-Architecture
set	I-Architecture
computer	I-Architecture
(	O
RISC	B-Architecture
)	O
soft	O
core	O
from	O
Lattice	O
Semiconductor	O
optimized	O
for	O
field-programmable	B-Architecture
gate	I-Architecture
arrays	I-Architecture
(	O
FPGAs	B-Architecture
)	O
.	O
</s>
<s>
It	O
uses	O
a	O
Harvard	B-Architecture
architecture	I-Architecture
,	O
which	O
means	O
the	O
instruction	O
and	O
data	O
buses	O
are	O
separate	O
.	O
</s>
<s>
LatticeMico32	B-Device
is	O
licensed	O
under	O
a	O
free	O
(	O
IP	O
)	O
core	O
license	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
Mico32	B-Device
is	O
not	O
restricted	O
to	O
Lattice	O
FPGAs	B-Architecture
,	O
and	O
can	O
be	O
legally	O
used	O
on	O
any	O
host	O
architecture	O
(	O
FPGA	B-Architecture
,	O
application-specific	O
integrated	O
circuit	O
(	O
ASIC	O
)	O
,	O
or	O
software	O
emulation	O
,	O
e.g.	O
,	O
QEMU	B-Application
)	O
.	O
</s>
<s>
It	O
is	O
possible	O
to	O
embed	O
a	O
LatticeMico32	B-Device
core	O
into	O
Xilinx	O
and	O
Altera	O
FPGAs	B-Architecture
,	O
in	O
addition	O
to	O
the	O
Lattice	O
Semiconductor	O
parts	O
the	O
LatticeMico32	B-Device
was	O
developed	O
for	O
.	O
</s>
<s>
AMD	O
PowerTune	O
uses	O
LatticeMico32	B-Device
.	O
</s>
<s>
The	O
CPU	O
core	O
and	O
the	O
development	O
toolchain	B-General_Concept
are	O
available	O
as	O
source-code	O
,	O
allowing	O
third	O
parties	O
to	O
implement	O
changes	O
to	O
the	O
processor	O
architecture	O
.	O
</s>
