<s>
Larrabee	B-Architecture
is	O
the	O
codename	O
for	O
a	O
cancelled	O
GPGPU	B-Architecture
chip	O
that	O
Intel	O
was	O
developing	O
separately	O
from	O
its	O
current	B-Application
line	I-Application
of	I-Application
integrated	I-Application
graphics	I-Application
accelerators	I-Application
.	O
</s>
<s>
It	O
is	O
named	O
after	O
either	O
Mount	O
Larrabee	B-Architecture
or	O
Larrabee	B-Architecture
State	O
Park	O
in	O
Whatcom	O
County	O
,	O
Washington	O
,	O
near	O
the	O
town	O
of	O
Bellingham	O
.	O
</s>
<s>
The	O
chip	O
was	O
to	O
be	O
released	O
in	O
2010	O
as	O
the	O
core	O
of	O
a	O
consumer	O
3D	B-Device
graphics	I-Device
card	I-Device
,	O
but	O
these	O
plans	O
were	O
cancelled	O
due	O
to	O
delays	O
and	O
disappointing	O
early	O
performance	O
figures	O
.	O
</s>
<s>
The	O
project	O
to	O
produce	O
a	O
GPU	B-Architecture
retail	O
product	O
directly	O
from	O
the	O
Larrabee	B-Architecture
research	O
project	O
was	O
terminated	O
in	O
May	O
2010	O
and	O
its	O
technology	O
was	O
passed	O
on	O
to	O
the	O
Xeon	B-General_Concept
Phi	I-General_Concept
.	O
</s>
<s>
The	O
Intel	B-General_Concept
MIC	I-General_Concept
multiprocessor	O
architecture	O
announced	O
in	O
2010	O
inherited	O
many	O
design	O
elements	O
from	O
the	O
Larrabee	B-Architecture
project	O
,	O
but	O
does	O
not	O
function	O
as	O
a	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
;	O
the	O
product	O
is	O
intended	O
as	O
a	O
co-processor	B-General_Concept
for	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
.	O
</s>
<s>
Almost	O
a	O
decade	O
later	O
,	O
on	O
June	O
12	O
,	O
2018	O
;	O
the	O
idea	O
of	O
an	O
Intel	O
dedicated	O
GPU	B-Architecture
was	O
revived	O
again	O
with	O
Intel	O
's	O
desire	O
to	O
create	O
a	O
discrete	B-Device
GPU	I-Device
by	O
2020	O
.	O
</s>
<s>
This	O
project	O
would	O
eventually	O
become	O
the	O
Intel	B-General_Concept
Xe	I-General_Concept
and	O
Intel	B-Device
Arc	I-Device
series	O
,	O
released	O
in	O
September	O
2020	O
and	O
March	O
2022	O
,	O
respectively	O
-	O
but	O
both	O
were	O
unconnected	O
to	O
the	O
work	O
on	O
the	O
Larrabee	B-Architecture
project	O
.	O
</s>
<s>
On	O
December	O
4	O
,	O
2009	O
,	O
Intel	O
officially	O
announced	O
that	O
the	O
first-generation	O
Larrabee	B-Architecture
would	O
not	O
be	O
released	O
as	O
a	O
consumer	O
GPU	B-Architecture
product	O
.	O
</s>
<s>
Instead	O
,	O
it	O
was	O
to	O
be	O
released	O
as	O
a	O
development	O
platform	O
for	O
graphics	O
and	O
high-performance	B-Architecture
computing	I-Architecture
.	O
</s>
<s>
On	O
May	O
25	O
,	O
2010	O
,	O
the	O
Technology	O
@Intel	O
blog	O
announced	O
that	O
Larrabee	B-Architecture
would	O
not	O
be	O
released	O
as	O
a	O
GPU	B-Architecture
,	O
but	O
instead	O
would	O
be	O
released	O
as	O
a	O
product	O
for	O
high-performance	B-Architecture
computing	I-Architecture
competing	O
with	O
the	O
Nvidia	B-Device
Tesla	I-Device
.	O
</s>
<s>
The	O
project	O
to	O
produce	O
a	O
GPU	B-Architecture
retail	O
product	O
directly	O
from	O
the	O
Larrabee	B-Architecture
research	O
project	O
was	O
terminated	O
in	O
May	O
2010	O
.	O
</s>
<s>
The	O
Intel	B-General_Concept
MIC	I-General_Concept
multiprocessor	O
architecture	O
announced	O
in	O
2010	O
inherited	O
many	O
design	O
elements	O
from	O
the	O
Larrabee	B-Architecture
project	O
,	O
but	O
does	O
not	O
function	O
as	O
a	O
graphics	B-Architecture
processing	I-Architecture
unit	I-Architecture
;	O
the	O
product	O
is	O
intended	O
as	O
a	O
co-processor	B-General_Concept
for	O
high	B-Architecture
performance	I-Architecture
computing	I-Architecture
.	O
</s>
<s>
Larrabee	B-Architecture
can	O
be	O
considered	O
a	O
hybrid	O
between	O
a	O
multi-core	B-Architecture
CPU	I-Architecture
and	O
a	O
GPU	B-Architecture
,	O
and	O
has	O
similarities	O
to	O
both	O
.	O
</s>
<s>
Its	O
coherent	B-General_Concept
cache	I-General_Concept
hierarchy	B-General_Concept
and	O
x86	B-Operating_System
architecture	I-Operating_System
compatibility	O
are	O
CPU-like	O
,	O
while	O
its	O
wide	O
SIMD	B-Device
vector	O
units	O
and	O
texture	O
sampling	O
hardware	O
are	O
GPU-like	O
.	O
</s>
<s>
As	O
a	O
GPU	B-Architecture
,	O
Larrabee	B-Architecture
would	O
have	O
supported	O
traditional	O
rasterized	O
3D	O
graphics	O
(	O
Direct3D	B-Application
&	O
OpenGL	B-Application
)	O
for	O
games	O
.	O
</s>
<s>
However	O
,	O
its	O
hybridization	O
of	O
CPU	B-Device
and	O
GPU	B-Architecture
features	O
should	O
also	O
have	O
been	O
suitable	O
for	O
general	B-Architecture
purpose	I-Architecture
GPU	I-Architecture
(	O
GPGPU	B-Architecture
)	O
or	O
stream	B-Application
processing	I-Application
tasks	O
.	O
</s>
<s>
For	O
example	O
,	O
it	O
might	O
have	O
performed	O
ray	B-Algorithm
tracing	I-Algorithm
or	O
physics	O
processing	O
,	O
in	O
real	B-General_Concept
time	I-General_Concept
for	O
games	O
or	O
offline	O
for	O
scientific	O
research	O
as	O
a	O
component	O
of	O
a	O
supercomputer	B-Architecture
.	O
</s>
<s>
Larrabee	B-Architecture
's	O
early	O
presentation	O
drew	O
some	O
criticism	O
from	O
GPU	B-Architecture
competitors	O
.	O
</s>
<s>
At	O
NVISION	O
08	O
,	O
an	O
Nvidia	O
employee	O
called	O
Intel	O
's	O
SIGGRAPH	O
paper	O
about	O
Larrabee	B-Architecture
"	O
marketing	O
puff	O
"	O
and	O
quoted	O
an	O
industry	O
analyst	O
(	O
Peter	O
Glaskowsky	O
)	O
who	O
speculated	O
that	O
the	O
Larrabee	B-Architecture
architecture	O
was	O
"	O
like	O
a	O
GPU	B-Architecture
from	O
2006	O
"	O
.	O
</s>
<s>
By	O
June	O
2009	O
,	O
Intel	O
claimed	O
that	O
prototypes	O
of	O
Larrabee	B-Architecture
were	O
on	O
par	O
with	O
the	O
Nvidia	O
GeForce	O
GTX	O
285	O
.	O
</s>
<s>
Justin	O
Rattner	O
,	O
Intel	O
CTO	O
,	O
delivered	O
a	O
keynote	O
at	O
the	O
Supercomputing	B-Architecture
2009	O
conference	O
on	O
November	O
17	O
,	O
2009	O
.	O
</s>
<s>
During	O
his	O
talk	O
he	O
demonstrated	O
an	O
overclocked	O
Larrabee	B-Architecture
processor	O
topping	O
one	O
teraFLOPS	O
in	O
performance	O
.	O
</s>
<s>
Because	O
this	O
was	O
only	O
one	O
fifth	O
that	O
of	O
available	O
competing	O
graphics	B-Device
boards	I-Device
,	O
Larrabee	B-Architecture
was	O
cancelled	O
"	O
as	O
a	O
standalone	O
discrete	B-Device
graphics	I-Device
product	O
"	O
on	O
December	O
4	O
,	O
2009	O
.	O
</s>
<s>
Larrabee	B-Architecture
was	O
intended	O
to	O
differ	O
from	O
older	O
discrete	B-Device
GPUs	I-Device
such	O
as	O
the	O
GeForce	O
200	O
Series	O
and	O
the	O
Radeon	B-Device
4000	I-Device
series	I-Device
in	O
three	O
major	O
ways	O
:	O
</s>
<s>
It	O
was	O
to	O
use	O
the	O
x86	B-Operating_System
instruction	O
set	O
with	O
Larrabee-specific	O
extensions	O
.	O
</s>
<s>
It	O
was	O
to	O
feature	O
cache	B-General_Concept
coherency	I-General_Concept
across	O
all	O
its	O
cores	O
.	O
</s>
<s>
This	O
had	O
been	O
expected	O
to	O
make	O
Larrabee	B-Architecture
more	O
flexible	O
than	O
current	O
GPUs	B-Architecture
,	O
allowing	O
more	O
differentiation	O
in	O
appearance	O
between	O
games	O
or	O
other	O
3D	O
applications	O
.	O
</s>
<s>
Intel	O
's	O
SIGGRAPH	O
2008	O
paper	O
mentioned	O
several	O
rendering	O
features	O
that	O
were	O
difficult	O
to	O
achieve	O
on	O
current	O
GPUs	B-Architecture
:	O
render	O
target	O
read	O
,	O
order-independent	O
transparency	O
,	O
irregular	O
shadow	O
mapping	O
,	O
and	O
real-time	O
raytracing	B-Algorithm
.	O
</s>
<s>
More	O
recent	O
GPUs	B-Architecture
such	O
as	O
ATI	O
's	O
Radeon	O
HD	O
5xxx	O
and	O
Nvidia	O
's	O
GeForce	O
400	O
Series	O
feature	O
increasingly	O
broad	O
general-purpose	O
computing	O
capabilities	O
via	O
DirectX11	O
DirectCompute	O
and	O
OpenCL	O
,	O
as	O
well	O
as	O
Nvidia	O
's	O
proprietary	O
CUDA	B-Architecture
technology	O
,	O
giving	O
them	O
many	O
of	O
the	O
capabilities	O
of	O
Larrabee	B-Architecture
.	O
</s>
<s>
The	O
x86	B-Operating_System
processor	O
cores	O
in	O
Larrabee	B-Architecture
differed	O
in	O
several	O
ways	O
from	O
the	O
cores	O
in	O
current	O
Intel	O
CPUs	B-Device
such	O
as	O
the	O
Core	O
2	O
Duo	O
or	O
Core	B-Device
i7	I-Device
:	O
</s>
<s>
Its	O
x86	B-Operating_System
cores	O
were	O
based	O
on	O
the	O
much	O
simpler	O
P54C	O
Pentium	B-General_Concept
design	O
which	O
is	O
still	O
being	O
maintained	O
for	O
use	O
in	O
embedded	B-Architecture
applications	O
.	O
</s>
<s>
The	O
P54C-derived	O
core	B-Device
is	I-Device
superscalar	B-General_Concept
but	O
does	O
not	O
include	O
out-of-order	B-General_Concept
execution	I-General_Concept
,	O
though	O
it	O
has	O
been	O
updated	O
with	O
modern	O
features	O
such	O
as	O
x86-64	B-Device
support	O
,	O
similar	O
to	O
the	O
Bonnell	B-Device
microarchitecture	I-Device
used	O
in	O
Atom	B-Device
.	O
</s>
<s>
Each	O
core	O
contained	O
a	O
512-bit	O
vector	B-Operating_System
processing	I-Operating_System
unit	I-Operating_System
,	O
able	O
to	O
process	O
16	O
single	O
precision	O
floating	O
point	O
numbers	O
at	O
a	O
time	O
.	O
</s>
<s>
This	O
is	O
similar	O
to	O
,	O
but	O
four	O
times	O
larger	O
than	O
,	O
the	O
SSE	B-General_Concept
units	O
on	O
most	O
x86	B-Operating_System
processors	O
,	O
with	O
additional	O
features	O
like	O
scatter/gather	B-General_Concept
instructions	O
and	O
a	O
mask	O
register	O
designed	O
to	O
make	O
using	O
the	O
vector	O
unit	O
easier	O
and	O
more	O
efficient	O
.	O
</s>
<s>
Larrabee	B-Architecture
was	O
to	O
derive	O
most	O
of	O
its	O
number-crunching	O
power	O
from	O
these	O
vector	O
units	O
.	O
</s>
<s>
This	O
bus	O
can	O
be	O
configured	O
in	O
two	O
modes	O
to	O
support	O
Larrabee	B-Architecture
products	O
with	O
16	O
cores	O
or	O
more	O
,	O
or	O
fewer	O
than	O
16	O
cores	O
.	O
</s>
<s>
It	O
included	O
explicit	O
cache	O
control	O
instructions	O
to	O
reduce	O
cache	B-General_Concept
thrashing	I-General_Concept
during	O
streaming	O
operations	O
which	O
only	O
read/write	O
data	O
once	O
.	O
</s>
<s>
Each	O
core	O
supported	O
four-way	O
interleaved	O
multithreading	O
,	O
with	O
four	O
copies	O
of	O
each	O
processor	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
Theoretically	O
Larrabee	B-Architecture
's	O
x86	B-Operating_System
processor	O
cores	O
would	O
have	O
been	O
able	O
to	O
run	O
existing	O
PC	O
software	O
,	O
or	O
even	O
operating	O
systems	O
.	O
</s>
<s>
A	O
different	O
version	O
of	O
the	O
processor	O
might	O
sit	O
in	O
motherboard	O
CPU	B-Device
sockets	O
using	O
QuickPath	B-Architecture
,	O
but	O
Intel	O
never	O
announced	O
any	O
plans	O
for	O
this	O
.	O
</s>
<s>
Though	O
Larrabee	B-Architecture
's	O
native	O
C/C	O
++	O
compiler	O
included	O
auto-vectorization	O
and	O
many	O
applications	O
were	O
able	O
to	O
execute	O
correctly	O
after	O
having	O
been	O
recompiled	O
,	O
maximum	O
efficiency	O
was	O
expected	O
to	O
have	O
required	O
code	O
optimization	O
using	O
C++	O
vector	O
intrinsics	O
or	O
inline	O
Larrabee	B-Architecture
assembly	O
code	O
.	O
</s>
<s>
However	O
,	O
as	O
in	O
all	O
GPGPUs	B-Architecture
,	O
not	O
all	O
software	O
would	O
have	O
benefited	O
from	O
utilization	O
of	O
a	O
vector	B-Operating_System
processing	I-Operating_System
unit	I-Operating_System
.	O
</s>
<s>
One	O
tech	O
journalism	O
site	O
claims	O
that	O
Larrabee	B-Architecture
's	O
graphics	O
capabilities	O
were	O
planned	O
to	O
be	O
integrated	O
in	O
CPUs	B-Device
based	O
on	O
the	O
Haswell	B-Device
microarchitecture	I-Device
.	O
</s>
<s>
Larrabee	B-Architecture
's	O
philosophy	O
of	O
using	O
many	O
small	O
,	O
simple	O
cores	O
was	O
similar	O
to	O
the	O
ideas	O
behind	O
the	O
Cell	B-General_Concept
processor	I-General_Concept
.	O
</s>
<s>
However	O
,	O
there	O
were	O
many	O
significant	O
differences	O
in	O
implementation	O
which	O
were	O
expected	O
to	O
make	O
programming	O
Larrabee	B-Architecture
simpler	O
.	O
</s>
<s>
The	O
Cell	B-General_Concept
processor	I-General_Concept
includes	O
one	O
main	O
processor	O
which	O
controls	O
many	O
smaller	O
processors	O
.	O
</s>
<s>
In	O
contrast	O
,	O
all	O
of	O
Larrabee	B-Architecture
's	O
cores	O
are	O
the	O
same	O
,	O
and	O
the	O
Larrabee	B-Architecture
was	O
not	O
expected	O
to	O
run	O
an	O
OS	O
.	O
</s>
<s>
Each	O
computer	O
core	O
in	O
the	O
Cell	O
(	O
SPE	O
)	O
has	O
a	O
local	O
store	O
,	O
for	O
which	O
explicit	O
(	O
DMA	B-General_Concept
)	O
operations	O
are	O
used	O
for	O
all	O
accesses	O
to	O
DRAM	O
.	O
</s>
<s>
In	O
Larrabee	B-Architecture
,	O
all	O
on-chip	O
and	O
off-chip	O
memories	O
are	O
under	O
automatically	O
managed	O
coherent	B-General_Concept
cache	I-General_Concept
hierarchy	B-General_Concept
,	O
so	O
that	O
its	O
cores	O
virtually	O
shared	O
a	O
uniform	O
memory	O
space	O
through	O
standard	O
copy	O
(	O
MOV	O
)	O
instructions	O
.	O
</s>
<s>
Larrabee	B-Architecture
cores	O
each	O
had	O
256KB	O
of	O
local	O
L2	O
cache	O
,	O
and	O
an	O
access	O
which	O
hits	O
another	O
L2	O
segment	O
takes	O
longer	O
to	O
access	O
.	O
</s>
<s>
Because	O
of	O
the	O
cache	B-General_Concept
coherency	I-General_Concept
noted	O
above	O
,	O
each	O
program	O
running	O
in	O
Larrabee	B-Architecture
had	O
virtually	O
a	O
large	O
linear	O
memory	O
just	O
as	O
in	O
traditional	O
general-purpose	O
CPU	B-Device
;	O
whereas	O
an	O
application	O
for	O
Cell	O
should	O
be	O
programmed	O
taking	O
into	O
consideration	O
limited	O
memory	O
footprint	O
of	O
the	O
local	O
store	O
associated	O
with	O
each	O
SPE	O
(	O
for	O
details	O
see	O
this	O
article	O
)	O
but	O
with	O
theoretically	O
higher	O
bandwidth	O
.	O
</s>
<s>
Cell	O
uses	O
DMA	B-General_Concept
for	O
data	O
transfer	O
to	O
and	O
from	O
on-chip	O
local	O
memories	O
,	O
which	O
enables	O
explicit	O
maintenance	O
of	O
overlays	O
stored	O
in	O
local	O
memory	O
to	O
bring	O
memory	O
closer	O
to	O
the	O
core	O
and	O
reduce	O
access	O
latencies	O
,	O
but	O
requiring	O
additional	O
effort	O
to	O
maintain	O
coherency	O
with	O
main	O
memory	O
;	O
whereas	O
Larrabee	B-Architecture
used	O
a	O
coherent	B-General_Concept
cache	I-General_Concept
with	O
special	O
instructions	O
for	O
cache	O
manipulation	O
(	O
notably	O
cache	O
eviction	O
hints	O
and	O
pre-fetch	O
instructions	O
)	O
,	O
which	O
mitigated	O
miss	O
and	O
eviction	O
penalties	O
and	O
reduce	O
cache	O
pollution	O
(	O
e.g.	O
</s>
<s>
for	O
rendering	O
pipelines	O
and	O
other	O
stream-like	O
computation	O
)	O
at	O
the	O
cost	O
of	O
additional	O
traffic	O
and	O
overhead	O
to	O
maintain	O
cache	B-General_Concept
coherency	I-General_Concept
.	O
</s>
<s>
A	O
core	O
in	O
Larrabee	B-Architecture
ran	O
up	O
to	O
four	O
threads	O
,	O
but	O
only	O
one	O
at	O
a	O
time	O
.	O
</s>
<s>
Larrabee	B-Architecture
's	O
hyperthreading	O
helped	O
hide	O
the	O
latencies	O
inherent	O
to	O
in-order	O
execution	O
.	O
</s>
<s>
Intel	O
began	O
integrating	O
a	O
line	O
of	O
GPUs	B-Architecture
onto	O
motherboards	O
under	O
the	O
Intel	B-Device
GMA	I-Device
brand	O
in	O
2004	O
.	O
</s>
<s>
Being	O
integrated	O
onto	O
motherboards	O
(	O
newer	O
versions	O
,	O
such	O
as	O
those	O
released	O
with	O
Sandy	O
Bridge	O
,	O
are	O
incorporated	O
onto	O
the	O
same	O
die	O
as	O
the	O
CPU	B-Device
)	O
these	O
chips	O
were	O
not	O
sold	O
separately	O
.	O
</s>
<s>
Though	O
the	O
low	O
cost	O
and	O
power	B-General_Concept
consumption	I-General_Concept
of	O
Intel	B-Device
GMA	I-Device
chips	O
made	O
them	O
suitable	O
for	O
small	O
laptops	O
and	O
less	O
demanding	O
tasks	O
,	O
they	O
lack	O
the	O
3D	O
graphics	O
processing	O
power	O
to	O
compete	O
with	O
contemporary	O
Nvidia	O
and	O
AMD/ATI	O
GPUs	B-Architecture
for	O
a	O
share	O
of	O
the	O
high-end	O
gaming	O
computer	O
market	O
,	O
the	O
HPC	B-Architecture
market	O
,	O
or	O
a	O
place	O
in	O
popular	O
video	B-Device
game	I-Device
consoles	I-Device
.	O
</s>
<s>
In	O
contrast	O
,	O
Larrabee	B-Architecture
was	O
to	O
be	O
sold	O
as	O
a	O
discrete	B-Device
GPU	I-Device
,	O
separate	O
from	O
motherboards	O
,	O
and	O
was	O
expected	O
to	O
perform	O
well	O
enough	O
for	O
consideration	O
in	O
the	O
next	O
generation	O
of	O
video	B-Device
game	I-Device
consoles	I-Device
.	O
</s>
<s>
The	O
team	O
working	O
on	O
Larrabee	B-Architecture
was	O
separate	O
from	O
the	O
Intel	B-Device
GMA	I-Device
team	O
.	O
</s>
<s>
The	O
hardware	O
was	O
designed	O
by	O
a	O
newly	O
formed	O
team	O
at	O
Intel	O
's	O
Hillsboro	O
,	O
Oregon	O
,	O
site	O
,	O
separate	O
from	O
those	O
that	O
designed	O
the	O
Nehalem	B-Device
.	O
</s>
<s>
The	O
3D	O
stack	O
specifically	O
was	O
written	O
by	O
developers	O
at	O
RAD	B-Algorithm
Game	I-Algorithm
Tools	I-Algorithm
(	O
including	O
Michael	O
Abrash	O
)	O
.	O
</s>
<s>
The	O
Intel	O
Visual	O
Computing	O
Institute	O
will	O
research	O
basic	O
and	O
applied	O
technologies	O
that	O
could	O
be	O
applied	O
to	O
Larrabee-based	O
products	O
.	O
</s>
<s>
Intel	O
's	O
SIGGRAPH	O
2008	O
paper	O
describes	O
cycle-accurate	B-Application
simulations	I-Application
(	O
limitations	O
of	O
memory	O
,	O
caches	O
and	O
texture	O
units	O
was	O
included	O
)	O
of	O
Larrabee	B-Architecture
's	O
projected	O
performance	O
.	O
</s>
<s>
Graphs	O
show	O
how	O
many	O
1GHz	O
Larrabee	B-Architecture
cores	O
are	O
required	O
to	O
maintain	O
60	O
frame/s	O
at	O
1600×1200	O
resolution	O
in	O
several	O
popular	O
games	O
.	O
</s>
<s>
Roughly	O
25	O
cores	O
are	O
required	O
for	O
Gears	B-Application
of	I-Application
War	I-Application
with	O
no	O
antialiasing	O
,	O
25	O
cores	O
for	O
F.E.A.R	O
with	O
4×	O
antialiasing	O
,	O
and	O
10	O
cores	O
for	O
Half-Life	B-Application
2	I-Application
:	I-Application
Episode	I-Application
Two	I-Application
with	O
4×	O
antialiasing	O
.	O
</s>
<s>
Intel	O
claimed	O
that	O
Larrabee	B-Architecture
would	O
likely	O
run	O
faster	O
than	O
1GHz	O
,	O
so	O
these	O
numbers	O
do	O
not	O
represent	O
actual	O
cores	O
,	O
rather	O
virtual	O
timeslices	O
of	O
such	O
.	O
</s>
<s>
A	O
June	O
2007	O
PC	O
Watch	O
article	O
suggested	O
that	O
the	O
first	O
Larrabee	B-Architecture
chips	O
would	O
feature	O
32	O
x86	B-Operating_System
processor	O
cores	O
and	O
come	O
out	O
in	O
late	O
2009	O
,	O
fabricated	O
on	O
a	O
45	B-Algorithm
nanometer	I-Algorithm
process	I-Algorithm
.	O
</s>
<s>
Chips	O
with	O
a	O
few	O
defective	O
cores	O
due	O
to	O
yield	B-Architecture
issues	O
would	O
be	O
sold	O
as	O
a	O
24-core	O
version	O
.	O
</s>
<s>
Later	O
in	O
2010	O
,	O
Larrabee	B-Architecture
would	O
be	O
shrunk	O
for	O
a	O
32	B-Algorithm
nanometer	I-Algorithm
fabrication	I-Algorithm
process	I-Algorithm
to	O
enable	O
a	O
48-core	O
version	O
.	O
</s>
<s>
The	O
last	O
statement	O
of	O
performance	O
can	O
be	O
calculated	O
(	O
theoretically	O
this	O
is	O
maximum	O
possible	O
performance	O
)	O
as	O
follows	O
:	O
32	O
cores	O
×	O
16	O
single-precision	O
float	O
SIMD/core	O
×	O
2	O
FLOP	O
(	O
fused	O
multiply-add	O
)	O
×	O
2GHz	O
=	O
2	O
TFLOPS	O
theoretically	O
.	O
</s>
<s>
A	O
public	O
demonstration	O
of	O
the	O
Larrabee	B-Architecture
ray-tracing	B-Algorithm
capabilities	I-Algorithm
took	O
place	O
at	O
the	O
Intel	O
Developer	O
Forum	O
in	O
San	O
Francisco	O
on	O
September	O
22	O
,	O
2009	O
.	O
</s>
<s>
An	O
experimental	O
version	O
of	O
Enemy	B-Application
Territory	I-Application
:	I-Application
Quake	I-Application
Wars	I-Application
titled	O
Quake	B-Application
Wars	I-Application
:	O
Ray	B-Algorithm
Traced	I-Algorithm
was	O
shown	O
in	O
real-time	O
.	O
</s>
<s>
The	O
scene	O
contained	O
a	O
ray	B-Algorithm
traced	I-Algorithm
water	O
surface	O
that	O
reflected	O
the	O
surrounding	O
objects	O
,	O
like	O
a	O
ship	O
and	O
several	O
flying	O
vehicles	O
,	O
accurately	O
.	O
</s>
<s>
A	O
Larrabee	B-Architecture
card	O
was	O
able	O
to	O
achieve	O
1006	O
GFLops	O
in	O
the	O
SGEMM	O
4Kx4K	O
calculation	O
.	O
</s>
<s>
An	O
engineering	O
sample	O
of	O
a	O
Larrabee	B-Architecture
card	O
was	O
procured	O
and	O
reviewed	O
by	O
Linus	O
Sebastian	O
in	O
a	O
video	O
published	O
May	O
14	O
,	O
2018	O
.	O
</s>
