<s>
К1839	O
is	O
a	O
microprocessor	B-Architecture
chipset	O
developed	O
between	O
1984	O
and	O
1989	O
at	O
the	O
Angstrem	O
Research	O
Institute	O
by	O
the	O
same	O
team	O
that	O
developed	O
the	O
1801BMx	B-General_Concept
series	O
of	O
CPUs	O
.	O
</s>
<s>
It	O
was	O
the	O
first	O
Soviet	O
,	O
and	O
later	O
the	O
first	O
Russian	O
32-bit	O
microprocessor	B-Architecture
system	O
.	O
</s>
<s>
From	O
a	O
programmer	O
's	O
point	O
of	O
view	O
,	O
it	O
was	O
a	O
complete	O
replica	O
of	O
the	O
VAX	O
11/750	O
Comet	O
and	O
included	O
floating-point	B-Algorithm
arithmetic	I-Algorithm
,	O
unlike	O
the	O
MicroVAX	B-Device
microprocessors	B-Architecture
produced	O
by	O
DEC	O
.	O
</s>
<s>
The	O
chipset	O
included	O
a	O
processor	O
,	O
a	O
coprocessor	O
for	O
integer	O
and	O
floating-point	B-Algorithm
arithmetic	I-Algorithm
,	O
a	O
memory	O
controller	O
and	O
a	O
bus	O
adapter	O
.	O
</s>
<s>
The	O
VAX-11	O
instruction	O
set	O
includes	O
304	O
instructions	O
,	O
21	O
addressing	O
modes	O
,	O
8/16/32/64	O
bits	O
of	O
data	O
,	O
32	O
bit	O
machine	O
word	O
,	O
16	O
GPRs	B-General_Concept
(	O
general	O
purpose	O
registers	B-General_Concept
)	O
and	O
hardware	O
support	O
for	O
multitasking	B-Operating_System
and	O
virtual	B-Architecture
memory	I-Architecture
.	O
</s>
<s>
L1839VM2	O
(	O
)	O
–	O
Arithmetic	O
and	O
Floating	B-Algorithm
point	I-Algorithm
coprocessor	O
.	O
</s>
<s>
252	O
instructions	O
,	O
8/16/32/64	O
bits	O
integers	O
,	O
floating	B-Algorithm
point	I-Algorithm
F	O
/	O
D	O
/	O
G	O
formats	O
,	O
and	O
24	O
bit	O
addressing	O
.	O
</s>
<s>
Integer	O
multiply	O
0.8μs	O
,	O
floating	B-Algorithm
point	I-Algorithm
multiply	O
1.5μs	O
.	O
</s>
<s>
L1839VT1	O
(	O
)	O
–	O
DRAM	O
and	O
cache	B-General_Concept
controller	O
.	O
</s>
<s>
DRAM	O
word	O
access	O
time	O
800ns	O
,	O
cache	B-General_Concept
access	O
time	O
of	O
200ns	O
.	O
</s>
