<s>
Jazelle	B-Language
DBX	O
(	O
direct	O
bytecode	O
execution	O
)	O
is	O
an	O
extension	O
that	O
allows	O
some	O
ARM	B-Architecture
processors	I-Architecture
to	O
execute	O
Java	B-Language
bytecode	I-Language
in	O
hardware	B-Architecture
as	O
a	O
third	O
execution	O
state	O
alongside	O
the	O
existing	O
ARM	B-Architecture
and	O
Thumb	O
modes	O
.	O
</s>
<s>
Jazelle	B-Language
functionality	O
was	O
specified	O
in	O
the	O
ARMv5TEJ	O
architecture	O
and	O
the	O
first	O
processor	O
with	O
Jazelle	B-Language
technology	O
was	O
the	O
ARM926EJ-S	O
.	O
Jazelle	B-Language
is	O
denoted	O
by	O
a	O
"	O
J	O
"	O
appended	O
to	O
the	O
CPU	O
name	O
,	O
except	O
for	O
post-v5	O
cores	O
where	O
it	O
is	O
required	O
(	O
albeit	O
only	O
in	O
trivial	O
form	O
)	O
for	O
architecture	O
conformance	O
.	O
</s>
<s>
Jazelle	B-Language
RCT	O
(	O
Runtime	O
Compilation	O
Target	O
)	O
is	O
a	O
different	O
technology	O
and	O
is	O
based	O
on	O
ThumbEE	O
mode	O
and	O
supports	O
ahead-of-time	B-Application
(	O
AOT	B-Application
)	O
and	O
just-in-time	O
(	O
JIT	O
)	O
compilation	O
with	O
Java	O
and	O
other	O
execution	O
environments	O
.	O
</s>
<s>
The	O
most	O
prominent	O
use	O
of	O
Jazelle	B-Language
DBX	O
is	O
by	O
manufacturers	O
of	O
mobile	O
phones	O
to	O
increase	O
the	O
execution	O
speed	O
of	O
Java	B-Language
ME	I-Language
games	O
and	O
applications	O
.	O
</s>
<s>
A	O
Jazelle-aware	O
Java	B-Language
virtual	I-Language
machine	I-Language
(	O
JVM	B-Language
)	O
will	O
attempt	O
to	O
run	O
Java	B-Language
bytecode	I-Language
in	O
hardware	B-Architecture
,	O
while	O
returning	O
to	O
the	O
software	O
for	O
more	O
complicated	O
,	O
or	O
lesser-used	O
bytecode	O
operations	O
.	O
</s>
<s>
ARM	B-Architecture
claims	O
that	O
approximately	O
95%	O
of	O
bytecode	O
in	O
typical	O
program	O
usage	O
ends	O
up	O
being	O
directly	O
processed	O
in	O
the	O
hardware	B-Architecture
.	O
</s>
<s>
The	O
published	O
specifications	O
are	O
very	O
incomplete	O
,	O
being	O
only	O
sufficient	O
for	O
writing	O
operating	B-General_Concept
system	I-General_Concept
code	O
that	O
can	O
support	O
a	O
JVM	B-Language
that	O
uses	O
Jazelle	B-Language
.	O
</s>
<s>
The	O
declared	O
intent	O
is	O
that	O
only	O
the	O
JVM	B-Language
software	O
needs	O
to	O
(	O
or	O
is	O
allowed	O
to	O
)	O
depend	O
on	O
the	O
hardware	B-Architecture
interface	O
details	O
.	O
</s>
<s>
This	O
tight	O
binding	O
facilitates	O
that	O
the	O
hardware	B-Architecture
and	O
JVM	B-Language
can	O
evolve	O
together	O
without	O
affecting	O
other	O
software	O
.	O
</s>
<s>
In	O
effect	O
,	O
this	O
gives	O
ARM	B-Architecture
Holdings	O
considerable	O
control	O
over	O
which	O
JVMs	B-Language
are	O
able	O
to	O
exploit	O
Jazelle	B-Language
.	O
</s>
<s>
It	O
also	O
prevents	O
open	O
source	O
JVMs	B-Language
from	O
using	O
Jazelle	B-Language
.	O
</s>
<s>
These	O
issues	O
do	O
not	O
apply	O
to	O
the	O
ARMv7	O
ThumbEE	O
environment	O
,	O
the	O
nominal	O
successor	O
to	O
Jazelle	B-Language
DBX	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
extension	O
uses	O
low-level	O
binary	O
translation	O
,	O
implemented	O
as	O
an	O
extra	O
stage	O
between	O
the	O
fetch	O
and	O
decode	O
stages	O
in	O
the	O
processor	O
instruction	B-General_Concept
pipeline	I-General_Concept
.	O
</s>
<s>
Recognised	O
bytecodes	O
are	O
converted	O
into	O
a	O
string	O
of	O
one	O
or	O
more	O
native	O
ARM	B-Architecture
instructions	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
mode	O
moves	O
JVM	B-Language
interpretation	O
into	O
hardware	B-Architecture
for	O
the	O
most	O
common	O
simple	O
JVM	B-Language
instructions	O
.	O
</s>
<s>
Among	O
other	O
things	O
,	O
this	O
reduces	O
the	O
need	O
for	O
Just-in-time	O
compilation	O
and	O
other	O
JVM	B-Language
accelerating	O
techniques	O
.	O
</s>
<s>
JVM	B-Language
instructions	O
that	O
are	O
not	O
implemented	O
in	O
Jazelle	B-Language
hardware	B-Architecture
cause	O
appropriate	O
routines	O
in	O
the	O
Jazelle-aware	O
JVM	B-Language
implementation	O
to	O
be	O
invoked	O
.	O
</s>
<s>
Details	O
are	O
not	O
published	O
,	O
since	O
all	O
JVM	B-Language
innards	O
are	O
transparent	O
(	O
except	O
for	O
performance	O
)	O
if	O
correctly	O
interpreted	O
.	O
</s>
<s>
Jazelle	B-Language
mode	O
is	O
entered	O
via	O
the	O
BXJ	O
instructions	O
.	O
</s>
<s>
A	O
hardware	B-Architecture
implementation	O
of	O
Jazelle	B-Language
will	O
only	O
cover	O
a	O
subset	O
of	O
JVM	B-Language
bytecodes	I-Language
.	O
</s>
<s>
For	O
unhandled	O
bytecodes	O
—	O
or	O
if	O
overridden	O
by	O
the	O
operating	B-General_Concept
system	I-General_Concept
—	O
the	O
hardware	B-Architecture
will	O
invoke	O
the	O
software	O
JVM	B-Language
.	O
</s>
<s>
The	O
system	O
is	O
designed	O
so	O
that	O
the	O
software	O
JVM	B-Language
does	O
not	O
need	O
to	O
know	O
which	O
bytecodes	O
are	O
implemented	O
in	O
hardware	B-Architecture
and	O
a	O
software	O
fallback	O
is	O
provided	O
by	O
the	O
software	O
JVM	B-Language
for	O
the	O
full	O
set	O
of	O
bytecodes	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
instruction	B-General_Concept
set	I-General_Concept
is	O
well	O
documented	O
as	O
Java	B-Language
bytecode	I-Language
.	O
</s>
<s>
However	O
,	O
ARM	B-Architecture
has	O
not	O
released	O
details	O
on	O
the	O
exact	O
execution	O
environment	O
details	O
;	O
the	O
documentation	O
provided	O
with	O
Sun	O
's	O
HotSpot	B-Language
Java	B-Language
Virtual	I-Language
Machine	I-Language
goes	O
as	O
far	O
as	O
to	O
state	O
:	O
"	O
For	O
the	O
avoidance	O
of	O
doubt	O
,	O
distribution	O
of	O
products	O
containing	O
software	O
code	O
to	O
exercise	O
the	O
BXJ	O
instruction	O
and	O
enable	O
the	O
use	O
of	O
the	O
ARM	B-Architecture
Jazelle	B-Language
architecture	O
extension	O
without	O
 [ .. ] 	O
agreement	O
from	O
ARM	B-Architecture
is	O
expressly	O
forbidden.	O
"	O
</s>
<s>
Employees	O
of	O
ARM	B-Architecture
have	O
in	O
the	O
past	O
published	O
several	O
white	O
papers	O
that	O
do	O
give	O
some	O
good	O
pointers	O
about	O
the	O
processor	O
extension	O
.	O
</s>
<s>
Versions	O
of	O
the	O
ARM	B-Architecture
Architecture	I-Architecture
reference	O
Manual	O
available	O
from	O
2008	O
have	O
included	O
pseudocode	O
for	O
the	O
"	O
BXJ	O
"	O
(	O
Branch	B-General_Concept
and	O
eXchange	O
to	O
Java	O
)	O
instruction	O
,	O
but	O
with	O
the	O
finer	O
details	O
being	O
shown	O
as	O
"	O
SUB-ARCHITECTURE	O
DEFINED	O
"	O
and	O
documented	O
elsewhere	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
state	O
relies	O
on	O
an	O
agreed	O
calling	O
convention	O
between	O
the	O
JVM	B-Language
and	O
the	O
Jazelle	B-Language
hardware	B-Architecture
state	O
.	O
</s>
<s>
This	O
application	B-Operating_System
binary	I-Operating_System
interface	I-Operating_System
is	O
not	O
published	O
by	O
ARM	B-Architecture
,	O
rendering	O
Jazelle	B-Language
an	O
undocumented	B-General_Concept
feature	I-General_Concept
for	O
most	O
users	O
and	O
Free	O
Software	O
JVMs	B-Language
.	O
</s>
<s>
The	O
entire	O
VM	O
state	O
is	O
held	O
within	O
normal	O
ARM	B-Architecture
registers	O
,	O
allowing	O
compatibility	O
with	O
existing	O
operating	B-General_Concept
systems	I-General_Concept
and	O
interrupt	O
handlers	O
unmodified	O
.	O
</s>
<s>
Restarting	O
a	O
bytecode	O
(	O
such	O
as	O
following	O
a	O
return	O
from	O
interrupt	O
)	O
will	O
re-execute	O
the	O
complete	O
sequence	O
of	O
related	O
ARM	B-Architecture
instructions	O
.	O
</s>
<s>
Specific	O
registers	O
are	O
designated	O
to	O
hold	O
the	O
most	O
important	O
parts	O
of	O
the	O
JVM	B-Language
state	O
:	O
registers	O
R0	O
–	O
R3	O
hold	O
an	O
alias	O
of	O
the	O
top	O
of	O
the	O
Java	O
stack	O
,	O
R4	O
holds	O
Java	O
local	O
operand	O
zero	O
(	O
pointer	O
to	O
*	O
this	O
)	O
and	O
R6	O
contains	O
the	O
Java	O
stack	O
pointer	O
.	O
</s>
<s>
Jazelle	B-Language
reuses	O
the	O
existing	O
program	B-General_Concept
counter	I-General_Concept
PC	O
or	O
its	O
synonym	O
register	O
R15	O
.	O
</s>
<s>
Java	B-Language
bytecode	I-Language
is	O
indicated	O
as	O
the	O
current	B-General_Concept
instruction	I-General_Concept
set	O
by	O
a	O
combination	O
of	O
two	O
bits	O
in	O
the	O
ARM	B-Architecture
CPSR	O
(	O
Current	O
Program	O
Status	O
Register	O
)	O
.	O
</s>
<s>
Bytecodes	O
are	O
decoded	O
by	O
the	O
hardware	B-Architecture
in	O
two	O
stages	O
(	O
versus	O
a	O
single	O
stage	O
for	O
Thumb	O
and	O
ARM	B-Architecture
code	O
)	O
and	O
switching	O
between	O
hardware	B-Architecture
and	O
software	O
decoding	O
(	O
Jazelle	B-Language
mode	O
and	O
ARM	B-Architecture
mode	O
)	O
takes	O
~	O
4	O
clock	O
cycles	O
.	O
</s>
<s>
For	O
entry	O
to	O
Jazelle	B-Language
hardware	B-Architecture
state	O
to	O
succeed	O
,	O
the	O
JE	O
(	O
Jazelle	B-Language
Enable	O
)	O
bit	O
in	O
the	O
CP14:C0(C2 )	O
[	O
bit	O
0 ]	O
register	O
must	O
be	O
set	O
;	O
clearing	O
of	O
the	O
JE	O
bit	O
by	O
a	O
 [ privileged ] 	O
operating	B-General_Concept
system	I-General_Concept
provides	O
a	O
high-level	O
override	O
to	O
prevent	O
application	O
programs	O
from	O
using	O
the	O
hardware	B-Architecture
Jazelle	B-Language
acceleration	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
CV	O
(	O
Configuration	O
Valid	O
)	O
bit	O
found	O
in	O
CP14:c0(c1 )	O
[	O
bit	O
1 ]	O
must	O
be	O
set	O
to	O
show	O
that	O
there	O
is	O
a	O
consistent	O
Jazelle	B-Language
state	O
setup	O
for	O
the	O
hardware	B-Architecture
to	O
use	O
.	O
</s>
<s>
The	O
BXJ	O
instruction	O
attempts	O
to	O
switch	O
to	O
Jazelle	B-Language
state	O
,	O
and	O
if	O
allowed	O
and	O
successful	O
,	O
sets	O
the	O
"	O
J	O
"	O
bit	O
in	O
the	O
CPSR	O
;	O
otherwise	O
,	O
it	O
"	O
falls	O
through	O
"	O
and	O
acts	O
as	O
a	O
standard	O
BX	O
(	O
Branch	B-General_Concept
)	O
instruction	O
.	O
</s>
<s>
The	O
only	O
time	O
when	O
an	O
operating	B-General_Concept
system	I-General_Concept
or	O
debugger	O
must	O
be	O
fully	O
aware	O
of	O
the	O
Jazelle	B-Language
mode	O
is	O
when	O
decoding	O
a	O
faulted	O
or	O
trapped	O
instruction	O
.	O
</s>
<s>
The	O
Java	O
program	B-General_Concept
counter	I-General_Concept
(	O
PC	O
)	O
pointing	O
to	O
the	O
next	B-General_Concept
instructions	I-General_Concept
must	O
be	O
placed	O
in	O
the	O
Link	O
Register	O
(	O
R14	O
)	O
before	O
executing	O
the	O
BXJ	O
branch	B-General_Concept
request	O
,	O
as	O
regardless	O
of	O
hardware	B-Architecture
or	O
software	O
processing	O
,	O
the	O
system	O
must	O
know	O
where	O
to	O
begin	O
decoding	O
.	O
</s>
<s>
Because	O
the	O
current	O
state	O
is	O
held	O
in	O
the	O
CPSR	O
,	O
the	O
bytecode	O
instruction	B-General_Concept
set	I-General_Concept
is	O
automatically	O
reselected	O
after	O
task-switching	O
and	O
processing	O
of	O
the	O
current	O
Java	B-Language
bytecode	I-Language
is	O
restarted	O
.	O
</s>
<s>
Following	O
an	O
entry	O
into	O
the	O
Jazelle	B-Language
state	O
mode	O
,	O
bytecodes	O
can	O
be	O
processed	O
in	O
one	O
of	O
three	O
ways	O
:	O
decoded	O
and	O
executed	O
natively	O
in	O
hardware	B-Architecture
,	O
handled	O
in	O
software	O
(	O
with	O
optimised	O
ARM/ThumbEE	O
JVM	B-Language
code	O
)	O
,	O
or	O
treated	O
as	O
an	O
invalid/illegal	O
opcode	O
.	O
</s>
<s>
The	O
third	O
case	O
will	O
cause	O
a	O
branch	B-General_Concept
to	O
an	O
ARM	B-Architecture
exception	O
mode	O
,	O
as	O
will	O
a	O
Java	B-Language
bytecode	I-Language
of	O
0xff	O
,	O
which	O
is	O
used	O
for	O
setting	O
JVM	B-Language
breakpoints	O
.	O
</s>
<s>
Execution	O
will	O
continue	O
in	O
hardware	B-Architecture
until	O
an	O
unhandled	O
bytecode	O
is	O
encountered	O
,	O
or	O
an	O
exception	O
occurs	O
.	O
</s>
<s>
Between	O
134	O
and	O
149	O
bytecodes	O
(	O
out	O
of	O
203	O
bytecodes	O
specified	O
in	O
the	O
JVM	B-Language
specification	O
)	O
are	O
translated	O
and	O
executed	O
directly	O
in	O
the	O
hardware	B-Architecture
.	O
</s>
<s>
Low-level	O
configuration	O
registers	O
,	O
for	O
the	O
hardware	B-Architecture
virtual	O
machine	O
,	O
are	O
held	O
in	O
the	O
ARM	B-Architecture
Co-processor	O
"	O
CP14	O
register	O
c0	O
"	O
.	O
</s>
<s>
The	O
registers	O
allow	O
detecting	O
,	O
enabling	O
or	O
disabling	O
the	O
hardware	B-Architecture
accelerator	O
(	O
if	O
it	O
is	O
available	O
)	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
Identity	O
Register	O
in	O
register	O
CP14:C0(C0 )	O
is	O
read-only	O
accessible	O
in	O
all	O
modes	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
OS	O
Control	O
Register	O
at	O
CP14:c0(c1 )	O
is	O
only	O
accessible	O
in	O
kernel	O
mode	O
and	O
will	O
cause	O
an	O
exception	O
when	O
accessed	O
in	O
user	O
mode	O
.	O
</s>
<s>
The	O
Jazelle	B-Language
Main	O
Configuration	O
Register	O
at	O
CP14:C0(C2 )	O
is	O
write-only	O
in	O
user	O
mode	O
and	O
read-write	O
in	O
kernel	O
mode	O
.	O
</s>
<s>
A	O
"	O
trivial	O
"	O
hardware	B-Architecture
implementation	O
of	O
Jazelle	B-Language
(	O
as	O
found	O
in	O
the	O
QEMU	B-Application
emulator	O
)	O
is	O
only	O
required	O
to	O
support	O
the	O
BXJ	O
opcode	O
itself	O
(	O
treating	O
BXJ	O
as	O
a	O
normal	O
BX	O
instruction	O
)	O
and	O
to	O
return	O
RAZ	O
(	O
Read-As-Zero	O
)	O
for	O
all	O
of	O
the	O
CP14:c0	O
Jazelle-related	O
registers	O
.	O
</s>
<s>
The	O
ARMv7	O
architecture	O
has	O
de-emphasized	O
Jazelle	B-Language
and	O
Direct	O
Bytecode	O
Execution	O
of	O
JVM	B-Language
bytecodes	I-Language
.	O
</s>
<s>
In	O
implementation	O
terms	O
,	O
only	O
trivial	O
hardware	B-Architecture
support	O
for	O
Jazelle	B-Language
is	O
now	O
required	O
:	O
support	O
for	O
entering	O
and	O
exiting	O
Jazelle	B-Language
mode	O
,	O
but	O
not	O
for	O
executing	O
any	O
Java	B-Language
bytecodes	I-Language
.	O
</s>
<s>
It	O
was	O
not	O
at	O
all	O
specific	O
to	O
Java	O
,	O
and	O
was	O
fully	O
documented	O
;	O
much	O
broader	O
adoption	O
was	O
anticipated	O
than	O
Jazelle	B-Language
was	O
able	O
to	O
achieve	O
.	O
</s>
<s>
ThumbEE	O
was	O
a	O
variant	O
of	O
the	O
Thumb2	O
16/32	O
-bit	O
instruction	B-General_Concept
set	I-General_Concept
.	O
</s>
