<s>
The	O
Intersil	B-General_Concept
6100	I-General_Concept
is	O
a	O
single-chip	O
microprocessor	B-Architecture
implementation	O
of	O
the	O
12-bit	B-Device
PDP-8	B-Device
instruction	O
set	O
,	O
along	O
with	O
a	O
range	O
of	O
peripheral	O
support	O
and	O
memory	O
ICs	O
developed	O
by	O
Intersil	O
in	O
the	O
mid-1970s	O
.	O
</s>
<s>
It	O
was	O
sometimes	O
referred	O
to	O
as	O
the	O
CMOS-PDP8	O
.	O
</s>
<s>
Since	O
it	O
was	O
also	O
produced	O
by	O
Harris	O
Corporation	O
,	O
it	O
was	O
also	O
known	O
as	O
the	O
Harris	O
HM-6100	O
.	O
</s>
<s>
The	O
Intersil	B-General_Concept
6100	I-General_Concept
was	O
introduced	O
in	O
the	O
second	O
quarter	O
of	O
1975	O
,	O
</s>
<s>
The	O
6100	B-General_Concept
family	O
was	O
produced	O
using	O
CMOS	B-Device
rather	O
than	O
the	O
bipolar	O
and	O
NMOS	B-Algorithm
technologies	O
used	O
by	O
most	O
of	O
its	O
contemporaries	O
(	O
Z80	B-General_Concept
,	O
8080	B-General_Concept
,	O
6502	B-General_Concept
,	O
6800	B-Device
,	O
9900	B-General_Concept
,	O
etc	O
.	O
)	O
.	O
</s>
<s>
As	O
a	O
result	O
of	O
its	O
CMOS	B-Device
technology	O
and	O
low	O
clock	O
speeds	O
,	O
8MHz	O
for	O
the	O
Harris	O
HM-6100A	O
,	O
it	O
had	O
relatively	O
low	O
power	O
consumption	O
,	O
less	O
than	O
100mW	O
at	O
10V/2MHz	O
,	O
and	O
could	O
be	O
operated	O
from	O
a	O
single	O
supply	O
over	O
the	O
wide	O
range	O
of	O
4	O
–	O
11V	O
.	O
</s>
<s>
Thus	O
,	O
it	O
could	O
be	O
used	O
in	O
high	O
reliability	O
embedded	B-Architecture
systems	I-Architecture
without	O
the	O
need	O
for	O
any	O
significant	O
thermal	O
management	O
,	O
if	O
the	O
rest	O
of	O
the	O
system	O
was	O
also	O
CMOS	B-Device
.	O
</s>
<s>
The	O
6100	B-General_Concept
was	O
available	O
to	O
military	O
specification	O
,	O
and	O
since	O
it	O
was	O
dual	O
sourced	O
by	O
Intersil	O
and	O
Harris	O
,	O
it	O
was	O
used	O
in	O
some	O
military	O
products	O
as	O
a	O
low	O
power	O
alternative	O
to	O
the	O
8080	B-General_Concept
,	O
6800	B-Device
etc	O
.	O
</s>
<s>
Although	O
it	O
had	O
a	O
very	O
simple	O
instruction	O
set	O
and	O
architecture	O
,	O
it	O
was	O
eminently	O
suitable	O
for	O
use	O
in	O
embedded	B-Architecture
systems	I-Architecture
that	O
had	O
previously	O
used	O
discrete	O
logic	O
circuits	O
and	O
even	O
Ledex	O
motorised	O
rotary	O
switches	O
or	O
relay-based	O
logic	O
controllers	O
.	O
</s>
<s>
The	O
6100	B-General_Concept
family	O
was	O
used	O
in	O
a	O
number	O
of	O
commercial	O
products	O
,	O
including	O
the	O
DECmate	B-Device
line	O
,	O
DEC	O
's	O
first	O
attempt	O
to	O
produce	O
a	O
personal	B-Device
computer	I-Device
.	O
</s>
<s>
The	O
Intersil	B-General_Concept
6100	I-General_Concept
was	O
first	O
used	O
,	O
according	O
to	O
Byte	O
magazine	O
,	O
in	O
Pacific	O
Cyber/Metrix	O
'	O
s	O
PCM-12	O
in	O
1976	O
.	O
</s>
<s>
The	O
IBM	B-Device
PC	I-Device
in	O
1981	O
cemented	O
the	O
doom	O
of	O
the	O
"	O
CMOS-8s	O
"	O
.	O
</s>
<s>
The	O
6100	B-General_Concept
is	O
a	O
12-bit	B-Device
CPU	O
that	O
closely	O
emulates	O
the	O
PDP-8	B-Device
(	O
See	O
PDP-8	B-Device
for	O
a	O
more	O
complete	O
discussion	O
)	O
.	O
</s>
<s>
It	O
has	O
three	O
primary	O
registers	O
:	O
PC	O
(	O
program	B-General_Concept
counter	I-General_Concept
)	O
,	O
12-bit	B-Device
AC	O
(	O
accumulator	B-General_Concept
)	O
,	O
and	O
MQ	O
(	O
Multiplier	O
Quotient	O
)	O
.	O
</s>
<s>
This	O
makes	O
it	O
difficult	O
to	O
have	O
subroutines	O
in	O
ROM	B-Device
,	O
these	O
must	O
find	O
some	O
other	O
location	O
to	O
store	O
the	O
address	O
.	O
</s>
<s>
This	O
was	O
not	O
a	O
problem	O
for	O
the	O
original	O
PDP-8	B-Device
,	O
where	O
all	O
main	O
memory	O
was	O
read/write	O
core	B-General_Concept
.	O
</s>
<s>
Conditionals	O
in	O
the	O
6100	B-General_Concept
allow	O
only	O
the	O
next	B-General_Concept
instruction	I-General_Concept
to	O
be	O
skipped	O
.	O
</s>
<s>
The	O
6100	B-General_Concept
has	O
a	O
12-bit	B-Device
data/address	O
bus	O
,	O
limiting	O
RAM	B-Architecture
to	O
only	O
4K	O
words	O
,	O
or	O
6KB	O
.	O
</s>
<s>
Memory	O
could	O
be	O
expanded	O
using	O
the	O
optional	O
6102	O
support	O
chip	O
,	O
which	O
added	O
three	O
address	O
lines	O
and	O
thus	O
expanded	O
memory	O
to	O
32K	O
words	O
(	O
48KB	O
)	O
in	O
the	O
same	O
way	O
that	O
the	O
PDP-8/E	O
expanded	O
the	O
PDP-8	B-Device
.	O
</s>
<s>
Intersil	O
offered	O
a	O
variety	O
of	O
related	O
chips	O
to	O
support	O
6100	B-General_Concept
systems	O
.	O
</s>
<s>
The	O
IM6100	O
CPU	O
implements	O
a	O
straight-8	O
(	O
basic	O
PDP-8	B-Device
without	O
memory	O
mapping	O
hardware	O
)	O
.	O
</s>
<s>
The	O
IM6101	O
PIE	O
(	O
Programmable	O
Interface	O
Element	O
)	O
is	O
a	O
basic	O
PDP-8	B-Device
I/O	O
port	O
.	O
</s>
<s>
The	O
IM6102	O
MEDIC	O
(	O
Memory	O
Extension	O
,	O
DMA	O
Controller	O
,	O
Interval	O
Timer	O
)	O
converts	O
an	O
IM6100	O
into	O
something	O
resembling	O
a	O
PDP-8/E	O
'	O
s	O
CPU	O
.	O
</s>
<s>
The	O
IM6103	O
PIO	O
(	O
Parallel	O
Input-Output	O
Port	O
)	O
,	O
and	O
the	O
IM6402	O
or	O
IM6403	O
UART	O
are	O
basic	O
PDP-8	B-Device
I/O	O
devices	O
on	O
ICs	O
.	O
</s>
<s>
Intersil	O
also	O
offered	O
compatible	O
sizes	O
of	O
RAM	B-Architecture
and	O
ROM	B-Device
:	O
the	O
IM6551	O
and	O
IM6561	O
(	O
1Kbit	O
,	O
256×4	O
)	O
SRAM	B-Architecture
,	O
the	O
IM6512	O
(	O
768Bit	O
,	O
64x12	O
)	O
SRAM	B-Architecture
,	O
and	O
the	O
IM6312	O
(	O
12Kbit	O
,	O
1024×12	O
)	O
mask	O
programmable	O
PROM	B-General_Concept
.	O
</s>
<s>
A	O
selection	O
of	O
these	O
components	O
were	O
offered	O
as	O
the	O
Intersil	O
6801	O
CMOS	B-Device
Family	O
Sampler	O
Kit	O
with	O
the	O
6960	O
–	O
Sampler	O
PC	O
Board	O
,	O
a	O
single-board	O
system	O
including	O
the	O
IM6100	O
CPU	O
,	O
IM6101	O
PIE	O
,	O
the	O
IM6312	O
ODT	O
(	O
Octal	O
Debugging	O
Technique	O
)	O
Monitor	O
ROM	B-Device
,	O
three	O
256×4	O
CMOS	B-Device
RAMs	I-Device
and	O
a	O
UART	O
IM6403	O
.	O
</s>
<s>
The	O
basic	O
6100	B-General_Concept
was	O
later	O
upgraded	O
to	O
the	O
6120	B-General_Concept
,	O
with	O
the	O
6102	O
memory	O
controller	O
built-in	O
.	O
</s>
