<s>
The	O
65xx	O
family	O
of	O
microprocessors	B-Architecture
,	O
consisting	O
of	O
the	O
MOS	B-General_Concept
Technology	I-General_Concept
6502	I-General_Concept
and	O
its	O
derivatives	O
,	O
the	O
WDC	B-General_Concept
65C02	I-General_Concept
,	O
WDC	B-General_Concept
65C802	I-General_Concept
and	I-General_Concept
WDC	I-General_Concept
65C816	I-General_Concept
,	O
and	O
CSG	B-General_Concept
65CE02	I-General_Concept
,	O
all	O
handle	O
interrupts	B-Application
in	O
a	O
similar	O
fashion	O
.	O
</s>
<s>
There	O
are	O
three	O
hardware	O
interrupt	B-Application
signals	O
common	O
to	O
all	O
65xx	O
processors	O
and	O
one	O
software	O
interrupt	B-Application
,	O
the	O
instruction	O
.	O
</s>
<s>
The	O
WDC	B-General_Concept
65C816	I-General_Concept
adds	O
a	O
fourth	O
hardware	O
interrupt	B-Application
,	O
useful	O
for	O
implementing	O
virtual	O
memory	O
architecturesand	O
the	O
software	O
interrupt	B-Application
instruction	O
(	O
also	O
present	O
in	O
the	O
65C802	B-General_Concept
)	O
,	O
intended	O
for	O
use	O
in	O
a	O
system	O
with	O
a	O
coprocessor	B-General_Concept
of	O
some	O
type	O
(	O
e.g.	O
,	O
a	O
floating	B-General_Concept
point	I-General_Concept
processor	I-General_Concept
)	O
.	O
</s>
<s>
The	O
hardware	O
interrupt	B-Application
signals	O
are	O
all	O
active	O
low	O
,	O
and	O
are	O
as	O
follows	O
:	O
</s>
<s>
The	O
detection	O
of	O
a	O
signal	O
causes	O
the	O
processor	O
to	O
enter	O
a	O
system	O
initialization	O
period	O
of	O
six	O
clock	O
cycles	O
,	O
after	O
which	O
it	O
sets	O
the	O
interrupt	B-Application
request	O
disable	O
flag	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
and	O
loads	O
the	O
program	B-General_Concept
counter	I-General_Concept
with	O
the	O
values	O
stored	O
at	O
the	O
processor	O
initialization	O
vector	O
(	O
)	O
before	O
commencing	O
execution	O
.	O
</s>
<s>
If	O
operating	O
in	O
native	O
mode	O
,	O
the	O
65C816/65C802	O
are	O
switched	O
back	O
to	O
emulation	O
mode	O
and	O
stay	O
there	O
until	O
returned	O
to	O
native	O
mode	O
under	O
software	O
control	O
.	O
</s>
<s>
The	O
processor	O
completes	O
the	O
current	B-General_Concept
instruction	I-General_Concept
and	O
updates	O
registers	O
or	O
memory	O
as	O
required	O
before	O
responding	O
to	O
the	O
interrupt	B-Application
.	O
</s>
<s>
65C816/65C802	O
when	O
operating	O
in	O
native	O
mode	O
:	O
The	O
program	O
bank	O
register	O
(	O
,	O
the	O
part	O
of	O
the	O
address	B-Architecture
bus	I-Architecture
)	O
is	O
pushed	O
onto	O
the	O
hardware	B-Application
stack	I-Application
.	O
</s>
<s>
The	O
most	O
significant	O
byte	O
(	O
MSB	O
)	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
(	O
)	O
is	O
pushed	O
onto	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
least	O
significant	O
byte	O
(	O
LSB	O
)	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
is	O
pushed	O
onto	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
status	B-General_Concept
register	I-General_Concept
(	O
)	O
is	O
pushed	O
onto	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
interrupt	B-Application
disable	O
flag	O
is	O
set	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
65C816/65C802	O
:	O
is	O
loaded	O
with	O
.	O
</s>
<s>
The	O
behavior	O
of	O
the	O
65C816	B-General_Concept
when	O
is	O
asserted	O
differs	O
in	O
some	O
respects	O
from	O
the	O
above	O
description	O
and	O
is	O
separately	O
discussed	O
below	O
.	O
</s>
<s>
Note	O
that	O
the	O
processor	O
does	O
not	O
push	O
the	O
accumulator	B-General_Concept
and	O
index	B-General_Concept
registers	I-General_Concept
on	O
to	O
the	O
stackcode	O
in	O
the	O
interrupt	B-General_Concept
handler	I-General_Concept
must	O
perform	O
that	O
task	O
,	O
as	O
well	O
as	O
restore	O
the	O
registers	O
at	O
the	O
termination	O
of	O
interrupt	B-Application
processing	O
,	O
as	O
necessary	O
.	O
</s>
<s>
Also	O
note	O
that	O
the	O
vector	O
for	O
is	O
the	O
same	O
as	O
that	O
for	O
in	O
all	O
eight	O
bit	O
65xx	O
processors	O
,	O
as	O
well	O
as	O
in	O
the	O
65C802/65C816	O
when	O
operating	O
in	O
emulation	O
mode	O
.	O
</s>
<s>
When	O
operating	O
in	O
native	O
mode	O
,	O
the	O
65C802/65C816	O
provide	O
separate	O
vectors	O
for	O
and	O
.	O
</s>
<s>
When	O
set	O
,	O
the	O
interrupt	B-Application
request	O
disable	O
flag	O
(	O
the	O
bit	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
)	O
will	O
disable	O
detection	O
of	O
the	O
signal	O
,	O
but	O
will	O
have	O
no	O
effect	O
on	O
any	O
other	O
interrupts	B-Application
(	O
however	O
,	O
see	O
below	O
section	O
on	O
the	O
instruction	O
implemented	O
in	O
WDC	O
CMOS	B-Device
processors	O
)	O
.	O
</s>
<s>
Additionally	O
,	O
with	O
the	O
65(c )	O
02	O
or	O
the	O
65C816/65C802	O
operating	O
in	O
emulation	O
mode	O
,	O
the	O
copy	O
of	O
the	O
status	B-General_Concept
register	I-General_Concept
that	O
is	O
pushed	O
on	O
to	O
the	O
stack	B-Application
will	O
have	O
the	O
flag	O
set	O
if	O
a	O
(	O
software	O
interrupt	B-Application
)	O
was	O
the	O
cause	O
of	O
the	O
interrupt	B-Application
,	O
or	O
cleared	O
if	O
an	O
was	O
the	O
cause	O
.	O
</s>
<s>
Hence	O
the	O
interrupt	B-General_Concept
service	I-General_Concept
routine	I-General_Concept
must	O
retrieve	O
a	O
copy	O
of	O
the	O
saved	O
status	B-General_Concept
register	I-General_Concept
from	O
where	O
it	O
was	O
pushed	O
onto	O
the	O
stack	B-Application
and	O
check	O
the	O
status	O
of	O
the	O
flag	O
in	O
order	O
to	O
distinguish	O
between	O
an	O
and	O
a	O
.	O
</s>
<s>
This	O
requirement	O
is	O
eliminated	O
when	O
operating	O
the	O
65C802/65C816	O
in	O
native	O
mode	O
,	O
due	O
to	O
the	O
separate	O
vectors	O
for	O
the	O
two	O
interrupt	B-Application
types	O
.	O
</s>
<s>
The	O
65C816	B-General_Concept
's	O
interrupt	B-Application
input	O
is	O
intended	O
to	O
provide	O
the	O
means	O
to	O
redirect	O
program	O
execution	O
when	O
a	O
hardware	O
exception	O
is	O
detected	O
,	O
such	O
as	O
a	O
page	B-General_Concept
fault	I-General_Concept
or	O
a	O
memory	B-Error_Name
access	I-Error_Name
violation	I-Error_Name
.	O
</s>
<s>
Also	O
,	O
achieving	O
correct	O
operation	O
in	O
response	O
to	O
requires	O
that	O
the	O
interrupt	B-Application
occur	O
at	O
the	O
proper	O
time	O
during	O
the	O
machine	B-General_Concept
cycle	I-General_Concept
,	O
whereas	O
no	O
such	O
requirement	O
exists	O
for	O
or	O
.	O
</s>
<s>
The	O
processor	O
completes	O
the	O
current	B-General_Concept
instruction	I-General_Concept
but	O
does	O
not	O
change	O
the	O
registers	O
or	O
memory	O
in	O
any	O
waythe	O
computational	O
results	O
of	O
the	O
completed	O
instruction	O
are	O
discarded	O
.	O
</s>
<s>
An	O
abort	O
interrupt	B-Application
does	O
not	O
literally	O
abort	O
an	O
instruction	O
.	O
</s>
<s>
The	O
program	O
bank	O
(	O
,	O
see	O
above	O
)	O
is	O
pushed	O
to	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
most	O
significant	O
byte	O
(	O
MSB	O
)	O
of	O
the	O
aborted	O
instruction	O
's	O
address	O
is	O
pushed	O
onto	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
least	O
significant	O
byte	O
(	O
LSB	O
)	O
of	O
the	O
aborted	O
instruction	O
's	O
address	O
is	O
pushed	O
onto	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
status	B-General_Concept
register	I-General_Concept
is	O
pushed	O
onto	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
interrupt	B-Application
disable	O
flag	O
is	O
set	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
.	O
</s>
<s>
The	O
program	B-General_Concept
counter	I-General_Concept
is	O
loaded	O
from	O
the	O
vector	O
(	O
see	O
tables	O
)	O
.	O
</s>
<s>
As	O
the	O
address	O
pushed	O
to	O
the	O
stack	B-Application
is	O
that	O
of	O
the	O
aborted	O
instruction	O
rather	O
than	O
the	O
contents	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
,	O
executing	O
an	O
(	O
ReTurn	O
from	O
Interrupt	B-Application
)	O
following	O
an	O
interrupt	B-Application
will	O
cause	O
the	O
processor	O
to	O
return	O
to	O
the	O
aborted	O
instruction	O
,	O
rather	O
than	O
the	O
next	B-General_Concept
instruction	I-General_Concept
,	O
as	O
would	O
be	O
the	O
case	O
with	O
the	O
other	O
interrupts	B-Application
.	O
</s>
<s>
In	O
order	O
for	O
the	O
processor	O
to	O
correctly	O
respond	O
to	O
an	O
abort	O
,	O
system	O
logic	O
must	O
assert	O
(	O
negate	O
)	O
the	O
input	O
as	O
soon	O
as	O
a	O
valid	O
address	O
has	O
been	O
placed	O
on	O
the	O
bus	O
and	O
it	O
has	O
been	O
determined	O
that	O
the	O
address	O
constitutes	O
a	O
page	B-General_Concept
fault	I-General_Concept
,	O
memory	B-Error_Name
access	I-Error_Name
violation	I-Error_Name
or	O
other	O
anomaly	O
(	O
e.g.	O
,	O
attempted	O
execution	O
of	O
a	O
privileged	O
instruction	O
)	O
.	O
</s>
<s>
If	O
these	O
timing	O
constraints	O
are	O
not	O
observed	O
,	O
the	O
abort	O
interrupt	B-General_Concept
handler	I-General_Concept
itself	O
may	O
be	O
aborted	O
,	O
causing	O
registers	O
and/or	O
memory	O
to	O
be	O
changed	O
in	O
a	O
possibly-undefined	O
manner	O
.	O
</s>
<s>
In	O
the	O
NMOS	B-Algorithm
6502	B-General_Concept
and	O
derivatives	O
(	O
e.g.	O
,	O
6510	O
)	O
,	O
the	O
simultaneous	O
assertion	O
of	O
a	O
hardware	O
interrupt	B-Application
line	I-Application
and	O
execution	O
of	O
was	O
not	O
accounted	O
for	O
in	O
the	O
designthe	O
instruction	O
will	O
be	O
ignored	O
in	O
such	O
a	O
case	O
.	O
</s>
<s>
Also	O
,	O
the	O
status	O
of	O
the	O
decimal	O
mode	O
flag	O
in	O
the	O
processor	O
status	B-General_Concept
register	I-General_Concept
is	O
unchanged	O
following	O
an	O
interrupt	B-Application
of	O
any	O
kind	O
.	O
</s>
<s>
This	O
behavior	O
can	O
potentially	O
result	O
in	O
a	O
difficult	O
to	O
locate	O
bug	B-Error_Name
in	O
the	O
interrupt	B-General_Concept
handler	I-General_Concept
if	O
decimal	O
mode	O
happens	O
to	O
be	O
enabled	O
at	O
the	O
time	O
of	O
an	O
interrupt	B-Application
.	O
</s>
<s>
These	O
anomalies	O
were	O
corrected	O
in	O
all	O
CMOS	B-Device
versions	O
of	O
the	O
processor	O
.	O
</s>
<s>
A	O
well-designed	O
and	O
succinct	O
interrupt	B-General_Concept
handler	I-General_Concept
or	O
interrupt	B-General_Concept
service	I-General_Concept
routine	I-General_Concept
(	O
ISR	O
)	O
will	O
not	O
only	O
expeditiously	O
service	O
any	O
event	O
that	O
causes	O
an	O
interrupt	B-Application
,	O
it	O
will	O
do	O
so	O
without	O
interfering	O
in	O
any	O
way	O
with	O
the	O
interrupted	O
foreground	O
taskthe	O
ISR	O
must	O
be	O
"	O
transparent	O
"	O
to	O
the	O
interrupted	O
task	O
(	O
although	O
exceptions	O
may	O
apply	O
in	O
specialized	O
cases	O
)	O
.	O
</s>
<s>
This	O
means	O
that	O
the	O
ISR	O
must	O
preserve	O
the	O
microprocessor	B-Architecture
(	O
MPU	O
)	O
state	O
and	O
not	O
disturb	O
anything	O
in	O
memory	O
that	O
it	O
is	O
not	O
supposed	O
to	O
disturb	O
.	O
</s>
<s>
Additionally	O
,	O
the	O
ISR	O
should	O
be	O
fully	O
reentrant	B-Operating_System
,	O
meaning	O
that	O
if	O
two	O
interrupts	B-Application
arrive	O
in	O
close	O
succession	O
,	O
the	O
ISR	O
will	O
be	O
able	O
to	O
resume	O
processing	O
the	O
first	O
interrupt	B-Application
after	O
the	O
second	O
one	O
has	O
been	O
serviced	O
.	O
</s>
<s>
Reentrancy	B-Operating_System
is	O
typically	O
achieved	O
by	O
using	O
only	O
the	O
MPU	B-Application
hardware	I-Application
stack	I-Application
for	O
storage	O
(	O
though	O
there	O
are	O
other	O
possible	O
methods	O
)	O
.	O
</s>
<s>
Preserving	O
the	O
MPU	O
state	O
means	O
that	O
the	O
ISR	O
must	O
assure	O
that	O
whatever	O
values	O
were	O
in	O
the	O
MPU	O
registers	O
at	O
the	O
time	O
of	O
the	O
interrupt	B-Application
are	O
there	O
when	O
the	O
ISR	O
terminates	O
.	O
</s>
<s>
A	O
part	O
of	O
the	O
preservation	O
process	O
is	O
automatically	O
handled	O
by	O
the	O
MPU	O
when	O
it	O
acknowledges	O
the	O
interrupt	B-Application
,	O
as	O
it	O
will	O
push	O
the	O
program	B-General_Concept
counter	I-General_Concept
(	O
and	O
program	O
bank	O
in	O
the	O
65C816/65C802	O
)	O
and	O
status	B-General_Concept
register	I-General_Concept
to	O
the	O
stack	B-Application
prior	O
to	O
executing	O
the	O
ISR	O
.	O
</s>
<s>
No	O
member	O
of	O
the	O
65xx	O
family	O
pushes	O
any	O
other	O
registers	O
to	O
the	O
stack	B-Application
.	O
</s>
<s>
In	O
most	O
ISRs	O
,	O
the	O
accumulator	B-General_Concept
and/or	O
index	B-General_Concept
registers	I-General_Concept
must	O
be	O
preserved	O
to	O
assure	O
transparency	O
and	O
later	O
restored	O
as	O
the	O
final	O
steps	O
prior	O
to	O
executing	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
the	O
65C816/65C802	O
,	O
consideration	O
must	O
be	O
given	O
to	O
whether	O
it	O
is	O
being	O
operated	O
in	O
emulation	O
or	O
native	O
mode	O
at	O
the	O
time	O
of	O
the	O
interrupt	B-Application
.	O
</s>
<s>
Also	O
,	O
a	O
65C816	B-General_Concept
native	O
mode	O
operating	O
system	O
may	O
well	O
use	O
a	O
different	O
stack	B-Application
location	O
than	O
the	O
application	O
software	O
,	O
which	O
means	O
the	O
ISR	O
would	O
have	O
to	O
preserve	O
and	O
subsequently	O
restore	O
the	O
stack	B-Application
pointer	O
(	O
)	O
.	O
</s>
<s>
Further	O
complicating	O
matters	O
with	O
the	O
65C816/65C802	O
is	O
that	O
the	O
sizes	O
of	O
the	O
accumulator	B-General_Concept
and	O
index	B-General_Concept
registers	I-General_Concept
may	O
be	O
either	O
8	O
or	O
16	O
bits	O
when	O
operating	O
in	O
native	O
mode	O
,	O
requiring	O
that	O
their	O
sizes	O
be	O
preserved	O
for	O
later	O
restoration	O
.	O
</s>
<s>
For	O
NMOS	B-Algorithm
processors	O
(	O
e.g.	O
,	O
6502	B-General_Concept
,	O
6510	O
,	O
8502	O
,	O
etc	O
.	O
</s>
<s>
)	O
,	O
there	O
can	O
be	O
only	O
one	O
method	O
by	O
which	O
the	O
accumulator	B-General_Concept
and	O
index	B-General_Concept
registers	I-General_Concept
are	O
preserved	O
,	O
as	O
only	O
the	O
accumulator	B-General_Concept
can	O
be	O
pushed	O
to	O
and	O
pulled	O
from	O
the	O
stack	B-Application
.	O
</s>
<s>
The	O
instruction	O
is	O
necessary	O
because	O
,	O
as	O
previously	O
noted	O
,	O
NMOS	B-Algorithm
versions	O
of	O
the	O
6502	B-General_Concept
do	O
not	O
clear	O
the	O
(	O
decimal	O
mode	O
)	O
flag	O
in	O
the	O
status	B-General_Concept
register	I-General_Concept
when	O
an	O
interrupt	B-Application
occurs	O
.	O
</s>
<s>
Once	O
the	O
accumulator	B-General_Concept
and	O
index	B-General_Concept
registers	I-General_Concept
have	O
been	O
preserved	O
,	O
the	O
ISR	O
can	O
use	O
them	O
as	O
needed	O
.	O
</s>
<s>
Again	O
,	O
the	O
following	O
NMOS	B-Algorithm
code	O
is	O
typical	O
:	O
</s>
<s>
A	O
consequence	O
of	O
the	O
instruction	O
is	O
the	O
MPU	O
will	O
return	O
to	O
decimal	O
mode	O
if	O
that	O
was	O
its	O
state	O
at	O
the	O
time	O
of	O
the	O
interrupt	B-Application
.	O
</s>
<s>
The	O
65C02	B-General_Concept
,	O
and	O
the	O
65C816/65C802	O
when	O
operating	O
in	O
emulation	O
mode	O
,	O
require	O
less	O
code	O
,	O
as	O
they	O
are	O
able	O
to	O
push	O
and	O
pull	O
the	O
index	B-General_Concept
registers	I-General_Concept
without	O
using	O
the	O
accumulator	B-General_Concept
as	O
an	O
intermediary	O
.	O
</s>
<s>
As	O
previously	O
stated	O
,	O
there	O
is	O
a	O
little	O
more	O
complexity	O
with	O
the	O
65C816/65C802	O
when	O
operating	O
in	O
native	O
mode	O
due	O
to	O
the	O
variable	O
register	O
sizes	O
and	O
the	O
necessity	O
of	O
accounting	O
for	O
the	O
and	O
registers	O
.	O
</s>
<s>
In	O
the	O
case	O
of	O
the	O
index	B-General_Concept
registers	I-General_Concept
,	O
they	O
may	O
be	O
pushed	O
without	O
regard	O
to	O
their	O
sizes	O
,	O
as	O
changing	O
sizes	O
automatically	O
sets	O
the	O
most	O
significant	O
byte	O
(	O
MSB	O
)	O
in	O
these	O
registers	O
to	O
zero	O
and	O
no	O
data	O
will	O
be	O
lost	O
when	O
the	O
pushed	O
value	O
is	O
restored	O
,	O
provided	O
the	O
index	B-General_Concept
registers	I-General_Concept
are	O
the	O
same	O
size	O
they	O
were	O
when	O
pushed	O
.	O
</s>
<s>
The	O
accumulator	B-General_Concept
,	O
however	O
,	O
is	O
really	O
two	O
registers	O
:	O
designated	O
and	O
.	O
</s>
<s>
Pushing	O
the	O
accumulator	B-General_Concept
when	O
it	O
is	O
set	O
to	O
8	O
bits	O
will	O
not	O
preserve	O
,	O
which	O
could	O
result	O
in	O
a	O
loss	O
of	O
transparency	O
should	O
the	O
ISR	O
change	O
in	O
any	O
way	O
.	O
</s>
<s>
Therefore	O
,	O
the	O
accumulator	B-General_Concept
must	O
always	O
be	O
set	O
to	O
16	O
bits	O
before	O
being	O
pushed	O
or	O
pulled	O
if	O
the	O
ISR	O
will	O
be	O
using	O
.	O
</s>
<s>
It	O
is	O
also	O
more	O
efficient	O
to	O
set	O
the	O
index	B-General_Concept
registers	I-General_Concept
to	O
16	O
bits	O
before	O
pushing	O
them	O
.	O
</s>
<s>
Otherwise	O
,	O
the	O
ISR	O
has	O
to	O
then	O
push	O
an	O
extra	O
copy	O
of	O
the	O
status	B-General_Concept
register	I-General_Concept
so	O
it	O
can	O
restore	O
the	O
register	O
sizes	O
prior	O
to	O
pulling	O
them	O
from	O
the	O
stack	B-Application
.	O
</s>
<s>
In	O
the	O
above	O
code	O
fragment	O
,	O
the	O
symbol	O
is	O
MOS	B-Architecture
Technology	I-Architecture
and	O
WDC	O
standard	O
assembly	B-Language
language	I-Language
syntax	O
for	O
a	O
bitwise	O
operand	O
.	O
</s>
<s>
If	O
the	O
ISR	O
has	O
its	O
own	O
assigned	O
stack	B-Application
location	O
,	O
preservation	O
of	O
the	O
stack	B-Application
pointer	O
(	O
)	O
must	O
occur	O
in	O
memory	O
after	O
the	O
above	O
pushes	O
have	O
occurredit	O
should	O
be	O
apparent	O
why	O
this	O
is	O
so	O
.	O
</s>
<s>
Note	O
that	O
upon	O
executing	O
,	O
the	O
65C816/65C802	O
will	O
automatically	O
restore	O
the	O
register	O
sizes	O
to	O
what	O
they	O
were	O
when	O
the	O
interrupt	B-Application
occurred	O
,	O
since	O
pulling	O
the	O
previouslysaved	O
status	B-General_Concept
register	I-General_Concept
sets	O
or	O
clears	O
both	O
register	O
size	O
bits	O
to	O
what	O
they	O
were	O
at	O
the	O
time	O
of	O
the	O
interrupt	B-Application
.	O
</s>
<s>
While	O
it	O
is	O
possible	O
to	O
switch	O
the	O
65C816/65C802	O
from	O
native	O
mode	O
to	O
emulation	O
mode	O
within	O
an	O
ISR	O
,	O
such	O
is	O
fraught	O
with	O
peril	O
.	O
</s>
<s>
In	O
addition	O
to	O
forcing	O
the	O
accumulator	B-General_Concept
and	O
index	B-General_Concept
registers	I-General_Concept
to	O
8	O
bits	O
(	O
causing	O
a	O
loss	O
of	O
the	O
most	O
significant	O
byte	O
in	O
the	O
index	B-General_Concept
registers	I-General_Concept
)	O
,	O
entering	O
emulation	O
mode	O
will	O
truncate	O
the	O
stack	B-Application
pointer	O
to	O
8	O
bits	O
and	O
relocate	O
the	O
stack	B-Application
itself	O
to	O
page	O
1	O
RAM	B-Architecture
.	O
</s>
<s>
The	O
result	O
is	O
the	O
stack	B-Application
that	O
existed	O
at	O
the	O
time	O
of	O
the	O
interrupt	B-Application
will	O
be	O
inaccessible	O
unless	O
it	O
was	O
also	O
in	O
page	O
1	O
RAM	B-Architecture
and	O
no	O
larger	O
than	O
256	O
bytes	O
.	O
</s>
<s>
In	O
general	O
,	O
mode	O
switching	O
while	O
servicing	O
an	O
interrupt	B-Application
is	O
not	O
a	O
recommended	O
procedure	O
,	O
but	O
may	O
be	O
necessary	O
in	O
specific	O
operating	O
environments	O
.	O
</s>
<s>
As	O
previously	O
noted	O
,	O
and	O
are	O
software	O
interrupts	B-Application
and	O
,	O
as	O
such	O
,	O
may	O
be	O
used	O
in	O
a	O
variety	O
of	O
ways	O
to	O
implement	O
system	O
functions	O
.	O
</s>
<s>
A	O
historical	O
use	O
of	O
has	O
been	O
to	O
assist	O
in	O
patching	O
PROMs	B-General_Concept
when	O
bugs	B-Error_Name
were	O
discovered	O
in	O
a	O
system	O
's	O
firmware	B-Application
.	O
</s>
<s>
A	O
typical	O
technique	O
often	O
used	O
during	O
firmware	B-Application
development	O
was	O
to	O
arrange	O
for	O
the	O
vector	O
to	O
point	O
to	O
an	O
unprogrammed	O
"	O
patch	O
area	O
"	O
in	O
the	O
PROM	O
.	O
</s>
<s>
In	O
the	O
event	O
a	O
bug	B-Error_Name
was	O
discovered	O
,	O
patching	O
would	O
be	O
accomplished	O
by	O
"	O
blowing	O
"	O
all	O
of	O
the	O
fuses	O
at	O
the	O
address	O
where	O
the	O
faulty	O
instruction	O
was	O
located	O
,	O
thus	O
changing	O
the	O
instruction	O
's	O
opcode	B-Language
to	O
.	O
</s>
<s>
Often	O
,	O
the	O
patch	O
area	O
code	O
started	O
by	O
"	O
sniffing	O
the	O
stack	B-Application
"	O
to	O
determine	O
the	O
address	O
at	O
which	O
the	O
bug	B-Error_Name
was	O
encountered	O
,	O
potentially	O
allowing	O
for	O
the	O
presence	O
of	O
more	O
than	O
one	O
patch	O
in	O
the	O
PROM	O
.	O
</s>
<s>
The	O
use	O
of	O
for	O
PROM	O
patching	O
diminished	O
once	O
EPROMs	B-General_Concept
and	O
EEPROMs	B-General_Concept
became	O
commonly	O
available	O
.	O
</s>
<s>
Another	O
use	O
of	O
in	O
software	O
development	O
is	O
as	O
a	O
debugging	O
aid	O
in	O
conjunction	O
with	O
a	O
machine	B-General_Concept
language	I-General_Concept
monitor	I-General_Concept
.	O
</s>
<s>
By	O
overwriting	O
an	O
opcode	B-Language
with	O
(	O
)	O
and	O
directing	O
the	O
hardware	O
vector	O
to	O
the	O
entry	O
point	O
of	O
the	O
monitor	O
,	O
one	O
can	O
cause	O
a	O
program	O
to	O
halt	O
at	O
any	O
desired	O
point	O
,	O
allowing	O
the	O
monitor	O
to	O
take	O
control	O
.	O
</s>
<s>
Debugging	O
,	O
as	O
advocated	O
by	O
Kuckes	O
and	O
Thompson	O
,	O
can	O
be	O
facilitated	O
by	O
liberally	O
sprinkling	O
one	O
's	O
code	O
with	O
instructions	O
(	O
opcode	B-Language
)	O
that	O
can	O
be	O
replaced	O
by	O
instructions	O
without	O
altering	O
the	O
actual	O
behaviour	O
of	O
the	O
program	O
being	O
debugged	O
.	O
</s>
<s>
A	O
characteristic	O
of	O
the	O
and	O
instructions	O
is	O
that	O
the	O
processor	O
treats	O
either	O
of	O
them	O
as	O
a	O
two	O
byte	O
instruction	O
:	O
the	O
opcode	B-Language
itself	O
and	O
the	O
following	O
byte	O
,	O
which	O
is	O
referred	O
to	O
as	O
the	O
"	O
signature.	O
"	O
</s>
<s>
Upon	O
execution	O
of	O
or	O
,	O
the	O
processor	O
will	O
add	O
two	O
to	O
the	O
program	B-General_Concept
counter	I-General_Concept
prior	O
to	O
pushing	O
it	O
to	O
the	O
stack	B-Application
.	O
</s>
<s>
Hence	O
when	O
(	O
ReTurn	O
from	O
Interrupt	B-Application
)	O
is	O
executed	O
,	O
the	O
interrupted	O
program	O
will	O
continue	O
at	O
the	O
address	O
immediately	O
following	O
the	O
signature	O
.	O
</s>
<s>
If	O
is	O
used	O
as	O
a	O
debugging	O
device	O
,	O
the	O
program	B-General_Concept
counter	I-General_Concept
may	O
have	O
to	O
be	O
adjusted	O
to	O
point	O
to	O
the	O
signature	O
in	O
order	O
for	O
execution	O
to	O
resume	O
where	O
expected	O
.	O
</s>
<s>
Alternatively	O
,	O
a	O
may	O
be	O
inserted	O
as	O
a	O
signature	O
"	O
placeholder	O
,	O
"	O
in	O
which	O
case	O
no	O
program	B-General_Concept
counter	I-General_Concept
adjustment	O
will	O
be	O
required	O
.	O
</s>
<s>
The	O
fact	O
that	O
and	O
double-increment	O
the	O
program	B-General_Concept
counter	I-General_Concept
before	O
pushing	O
it	O
to	O
the	O
stack	B-Application
facilitates	O
the	O
technique	O
of	O
treating	O
them	O
as	O
supervisor	B-Operating_System
call	I-Operating_System
instructions	I-Operating_System
,	O
as	O
found	O
on	O
some	O
mainframe	B-Architecture
computers	I-Architecture
.	O
</s>
<s>
The	O
operating	O
system	O
or	O
handler	O
would	O
retrieve	O
the	O
value	O
of	O
the	O
program	B-General_Concept
counter	I-General_Concept
pushed	O
to	O
the	O
stack	B-Application
,	O
decrement	O
it	O
and	O
read	O
from	O
the	O
resulting	O
memory	O
location	O
to	O
get	O
the	O
signature	O
.	O
</s>
<s>
After	O
converting	O
the	O
signature	O
to	O
a	O
zero-based	O
index	O
,	O
a	O
simple	O
lookup	B-Data_Structure
table	I-Data_Structure
can	O
be	O
consulted	O
to	O
load	O
the	O
program	B-General_Concept
counter	I-General_Concept
with	O
the	O
address	O
of	O
the	O
proper	O
service	O
routine	O
.	O
</s>
<s>
Also	O
,	O
as	O
executing	O
or	O
always	O
vectors	O
the	O
processor	O
to	O
the	O
same	O
address	O
,	O
simple	O
code	O
may	O
be	O
used	O
to	O
preserve	O
the	O
registers	O
on	O
the	O
stack	B-Application
prior	O
to	O
turning	O
control	O
over	O
to	O
the	O
requested	O
service	O
.	O
</s>
<s>
However	O
,	O
this	O
programming	O
model	O
will	O
result	O
in	O
somewhat	O
slower	O
execution	O
as	O
compared	O
to	O
calling	O
a	O
service	O
as	O
a	O
subroutine	O
,	O
primarily	O
a	O
result	O
of	O
the	O
stack	B-Application
activity	O
that	O
occurs	O
with	O
any	O
interrupt	B-Application
.	O
</s>
<s>
Also	O
,	O
interrupt	B-Application
requests	O
will	O
have	O
been	O
disabled	O
by	O
executing	O
or	O
,	O
requiring	O
that	O
the	O
operating	O
system	O
re-enable	O
them	O
.	O
</s>
<s>
(	O
WAit	O
for	O
Interrupt	B-Application
,	O
opcode	B-Language
)	O
is	O
an	O
instruction	O
available	O
on	O
the	O
WDC	O
version	O
of	O
the	O
65C02	B-General_Concept
and	O
the	O
65C816/65C802	O
microprocessors	B-Architecture
(	O
MPU	O
)	O
that	O
halts	O
the	O
MPU	O
and	O
places	O
it	O
into	O
a	O
semi-catatonic	O
state	O
until	O
a	O
hardware	O
interrupt	B-Application
of	O
any	O
kind	O
occurs	O
.	O
</s>
<s>
Despite	O
interrupt	B-Application
requests	O
(	O
IRQ	O
)	O
having	O
been	O
disabled	O
prior	O
to	O
the	O
instruction	O
,	O
the	O
MPU	O
will	O
respond	O
to	O
any	O
hardware	O
interrupt	B-Application
while	O
waiting	O
.	O
</s>
<s>
Upon	O
receipt	O
of	O
an	O
interrupt	B-Application
,	O
the	O
MPU	O
will	O
"	O
awaken	O
"	O
in	O
one	O
clock	O
cycle	O
and	O
resume	O
execution	O
at	O
the	O
instruction	O
immediately	O
following	O
.	O
</s>
<s>
Hence	O
interrupt	B-General_Concept
latency	I-General_Concept
will	O
be	O
very	O
short	O
(	O
70	O
nanoseconds	O
at	O
14	O
megahertz	O
)	O
,	O
resulting	O
in	O
the	O
most	O
rapid	O
response	O
possible	O
to	O
an	O
external	O
event	O
.	O
</s>
<s>
Similar	O
in	O
some	O
ways	O
to	O
is	O
the	O
(	O
SToP	O
,	O
opcode	B-Language
)	O
instruction	O
,	O
which	O
completely	O
shuts	O
down	O
the	O
MPU	O
while	O
waiting	O
for	O
a	O
single	O
interrupt	B-Application
input	O
.	O
</s>
<s>
The	O
MPU	O
is	O
brought	O
out	O
of	O
this	O
state	O
by	O
pulling	O
its	O
reset	B-General_Concept
input	O
pin	O
(	O
,	O
which	O
is	O
classified	O
as	O
an	O
interrupt	B-Application
input	O
)	O
low	O
.	O
</s>
<s>
Execution	O
will	O
then	O
resume	O
at	O
the	O
address	O
stored	O
at	O
locations	O
,	O
the	O
hardware	O
reset	B-General_Concept
vector	O
.	O
</s>
