<s>
Internal	B-General_Concept
RAM	I-General_Concept
,	O
or	O
IRAM	O
or	O
on-chip	O
RAM	B-Architecture
(	O
OCRAM	O
)	O
,	O
is	O
the	O
address	B-General_Concept
range	I-General_Concept
of	O
RAM	B-Architecture
that	O
is	O
internal	O
to	O
the	O
CPU	B-Device
.	O
</s>
<s>
Some	O
object	B-Application
files	I-Application
contain	O
an	O
.iram	O
section	O
.	O
</s>
<s>
Earlier	O
forms	O
of	O
what	O
we	O
have	O
today	O
as	O
DRAM	O
started	O
as	O
drum	B-General_Concept
memory	I-General_Concept
which	O
was	O
an	O
early	O
form	O
of	O
memory	O
for	O
computers	O
.	O
</s>
<s>
After	O
drum	B-General_Concept
memory	I-General_Concept
came	O
Magnetic-core	O
memory	O
which	O
would	O
store	O
information	O
using	O
the	O
polarity	O
of	O
ferrite	O
donuts	O
 '	O
magnetic	O
fields	O
.	O
</s>
<s>
Through	O
these	O
early	O
trial	O
and	O
errors	O
of	O
computing	O
memory	O
,	O
the	O
final	O
result	O
was	O
Dynamic	O
Random	B-Architecture
Access	I-Architecture
Memory	I-Architecture
which	O
we	O
use	O
today	O
in	O
our	O
devices	O
.	O
</s>
<s>
Dynamic	O
Random	B-Architecture
Access	I-Architecture
Memory	I-Architecture
or	O
(	O
RAM	B-Architecture
)	O
was	O
first	O
invented	O
in	O
1968	O
by	O
Robert	O
Dennard	O
.	O
</s>
<s>
He	O
was	O
born	O
in	O
Texas	O
and	O
is	O
an	O
engineer	O
who	O
created	O
one	O
of	O
the	O
first	O
models	O
of	O
(	O
RAM	B-Architecture
)	O
which	O
was	O
first	O
called	O
Dynamic	O
Random	B-Architecture
Access	I-Architecture
Memory	I-Architecture
.	O
</s>
<s>
Random	B-Architecture
Access	I-Architecture
Memory	I-Architecture
is	O
memory	O
storage	O
that	O
if	O
found	O
in	O
electronic	O
devices	O
such	O
as	O
computers	O
.	O
</s>
<s>
It	O
hold	O
data	O
while	O
the	O
computer	O
is	O
on	O
so	O
that	O
it	O
can	O
be	O
quickly	O
accessed	O
by	O
the	O
CPU	B-Device
or	O
(	O
Central	O
Processing	O
Unit	O
)	O
.	O
</s>
<s>
Ram	B-Architecture
is	O
different	O
from	O
regular	O
storage	O
units	O
such	O
as	O
Hard	O
Disks	O
,	O
Solid	O
State	O
Drives	O
,	O
and	O
Solid	O
State	O
Hybrid	O
Drives	O
.	O
</s>
<s>
While	O
these	O
types	O
of	O
drives	O
hold	O
much	O
permanent	O
information	O
,	O
RAM	B-Architecture
holds	O
temporary	O
,	O
yet	O
important	O
,	O
information	O
for	O
the	O
computer	O
to	O
receive	O
.	O
</s>
<s>
While	O
using	O
very	O
minimal	O
programs	O
such	O
as	O
a	O
browser	O
or	O
having	O
a	O
couple	O
of	O
programs	O
open	O
,	O
a	O
RAM	B-Architecture
is	O
working	O
so	O
that	O
it	O
can	O
load	O
up	O
small	O
tasks	O
like	O
these	O
.	O
</s>
<s>
However	O
when	O
opening	O
up	O
bigger	O
programs	O
and	O
more	O
tabs	O
for	O
a	O
computer	O
to	O
work	O
harder	O
the	O
information	O
is	O
shifted	O
from	O
the	O
RAM	B-Architecture
to	O
other	O
drives	O
such	O
as	O
the	O
hard	O
disk	O
.	O
</s>
<s>
Generally	O
,	O
IRAM	O
is	O
composed	O
of	O
very	O
high	O
speed	O
SRAM	B-Architecture
located	O
alongside	O
of	O
the	O
CPU	B-Device
.	O
</s>
<s>
It	O
acts	O
similar	O
to	O
a	O
CPU	B-General_Concept
cache	I-General_Concept
,	O
but	O
is	O
software	O
addressable	O
.	O
</s>
<s>
Associated	O
with	O
speed	O
,	O
the	O
more	O
RAM	B-Architecture
there	O
is	O
in	O
the	O
system	O
,	O
the	O
faster	O
the	O
computer	O
can	O
run	O
,	O
because	O
it	O
allows	O
the	O
RAM	B-Architecture
to	O
run	O
more	O
information	O
through	O
to	O
the	O
computer	O
's	O
(	O
CPU	B-Device
)	O
.	O
</s>
<s>
Not	O
only	O
does	O
adding	O
more	O
RAM	B-Architecture
to	O
a	O
computer	O
help	O
it	O
run	O
faster	O
,	O
it	O
helps	O
boots	O
up	O
a	O
computer	O
immensely	O
faster	O
compared	O
to	O
booting	O
up	O
a	O
system	O
with	O
less	O
RAM	B-Architecture
.	O
</s>
<s>
For	O
example	O
a	O
stick	O
of	O
RAM	B-Architecture
that	O
has	O
only	O
512	O
megabytes	O
of	O
transfer	O
speed	O
is	O
too	O
slow	O
compared	O
to	O
a	O
stick	O
of	O
RAM	B-Architecture
that	O
has	O
16	O
gigabytes	O
of	O
transfer	O
speeds	O
.	O
</s>
<s>
Not	O
only	O
does	O
the	O
transfer	O
speeds	O
depend	O
of	O
how	O
fast	O
a	O
RAM	B-Architecture
can	O
process	O
information	O
,	O
the	O
type	O
of	O
stick	O
of	O
RAM	B-Architecture
depends	O
as	O
well	O
.	O
</s>
<s>
Just	O
recently	O
,	O
there	O
was	O
an	O
announcement	O
that	O
a	O
DDR5	O
stick	O
of	O
ram	B-Architecture
would	O
be	O
released	O
sometime	O
in	O
2020	O
.	O
</s>
<s>
The	O
DDR5	O
ram	B-Architecture
would	O
use	O
less	O
power	O
and	O
would	O
have	O
double	O
the	O
bandwidth	O
compared	O
to	O
the	O
DDR4	O
RAM	B-Architecture
.	O
</s>
