<s>
In	O
computing	O
,	O
interleaved	B-General_Concept
memory	I-General_Concept
is	O
a	O
design	O
which	O
compensates	O
for	O
the	O
relatively	O
slow	O
speed	O
of	O
dynamic	O
random-access	B-Architecture
memory	I-Architecture
(	O
DRAM	O
)	O
or	O
core	B-General_Concept
memory	I-General_Concept
,	O
by	O
spreading	O
memory	O
addresses	O
evenly	O
across	O
memory	B-General_Concept
banks	I-General_Concept
.	O
</s>
<s>
That	O
way	O
,	O
contiguous	O
memory	O
reads	O
and	O
writes	O
use	O
each	O
memory	B-General_Concept
bank	I-General_Concept
in	O
turn	O
,	O
resulting	O
in	O
higher	O
memory	O
throughput	O
due	O
to	O
reduced	O
waiting	O
for	O
memory	B-General_Concept
banks	I-General_Concept
to	O
become	O
ready	O
for	O
the	O
operations	O
.	O
</s>
<s>
It	O
is	O
different	O
from	O
multi-channel	B-Architecture
memory	I-Architecture
architectures	I-Architecture
,	O
primarily	O
as	O
interleaved	B-General_Concept
memory	I-General_Concept
does	O
not	O
add	O
more	O
channels	O
between	O
the	O
main	O
memory	O
and	O
the	O
memory	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
With	O
interleaved	B-General_Concept
memory	I-General_Concept
,	O
memory	O
addresses	O
are	O
allocated	O
to	O
each	O
memory	B-General_Concept
bank	I-General_Concept
in	O
turn	O
.	O
</s>
<s>
For	O
example	O
,	O
in	O
an	O
interleaved	O
system	O
with	O
two	O
memory	B-General_Concept
banks	I-General_Concept
(	O
assuming	O
word-addressable	B-General_Concept
memory	O
)	O
,	O
if	O
logical	O
address	O
32	O
belongs	O
to	O
bank	O
0	O
,	O
then	O
logical	O
address	O
33	O
would	O
belong	O
to	O
bank	O
1	O
,	O
logical	O
address	O
34	O
would	O
belong	O
to	O
bank	O
0	O
,	O
and	O
so	O
on	O
.	O
</s>
<s>
An	O
interleaved	B-General_Concept
memory	I-General_Concept
is	O
said	O
to	O
be	O
n-way	O
interleaved	O
when	O
there	O
are	O
banks	O
and	O
memory	O
location	O
resides	O
in	O
bank	O
.	O
</s>
<s>
Interleaved	B-General_Concept
memory	I-General_Concept
results	O
in	O
contiguous	O
reads	O
(	O
which	O
are	O
common	O
both	O
in	O
multimedia	O
and	O
execution	O
of	O
programs	O
)	O
and	O
contiguous	O
writes	O
(	O
which	O
are	O
used	O
frequently	O
when	O
filling	O
storage	O
or	O
communication	O
buffers	O
)	O
actually	O
using	O
each	O
memory	B-General_Concept
bank	I-General_Concept
in	O
turn	O
,	O
instead	O
of	O
using	O
the	O
same	O
one	O
repeatedly	O
.	O
</s>
<s>
Main	O
memory	O
(	O
random-access	B-Architecture
memory	I-Architecture
,	O
RAM	B-Architecture
)	O
is	O
usually	O
composed	O
of	O
a	O
collection	O
of	O
DRAM	O
memory	O
chips	O
,	O
where	O
a	O
number	O
of	O
chips	O
can	O
be	O
grouped	O
together	O
to	O
form	O
a	O
memory	B-General_Concept
bank	I-General_Concept
.	O
</s>
<s>
It	O
is	O
then	O
possible	O
,	O
with	O
a	O
memory	B-General_Concept
controller	I-General_Concept
that	O
supports	O
interleaving	O
,	O
to	O
lay	O
out	O
these	O
memory	B-General_Concept
banks	I-General_Concept
so	O
that	O
the	O
memory	B-General_Concept
banks	I-General_Concept
will	O
be	O
interleaved	O
.	O
</s>
<s>
Each	O
DRAM	B-General_Concept
bank	I-General_Concept
has	O
a	O
row	O
buffer	O
that	O
serves	O
as	O
a	O
cache	O
for	O
accessing	O
any	O
page	O
in	O
the	O
bank	O
.	O
</s>
<s>
Before	O
a	O
page	O
in	O
the	O
DRAM	B-General_Concept
bank	I-General_Concept
is	O
read	O
,	O
it	O
is	O
first	O
loaded	O
into	O
the	O
row-buffer	O
.	O
</s>
<s>
Row-buffer	O
conflicts	O
or	O
misses	O
come	O
from	O
a	O
sequence	O
of	O
accesses	O
to	O
difference	O
pages	O
in	O
the	O
same	O
memory	B-General_Concept
bank	I-General_Concept
.	O
</s>
<s>
The	O
study	O
shows	O
that	O
a	O
conventional	O
memory	B-General_Concept
interleaving	I-General_Concept
method	O
would	O
propagate	O
address-mapping	O
conflicts	O
at	O
a	O
cache	O
level	O
to	O
the	O
memory	O
address	O
space	O
,	O
causing	O
row-buffer	O
misses	O
in	O
a	O
memory	B-General_Concept
bank	I-General_Concept
.	O
</s>
<s>
The	O
permutation-based	O
interleaved	B-General_Concept
memory	I-General_Concept
method	O
solved	O
the	O
problem	O
with	O
a	O
trivial	O
microarchitecture	O
cost	O
.	O
</s>
<s>
In	O
traditional	O
(	O
flat	O
)	O
layouts	O
,	O
memory	B-General_Concept
banks	I-General_Concept
can	O
be	O
allocated	O
a	O
contiguous	O
block	O
of	O
memory	O
addresses	O
,	O
which	O
is	O
very	O
simple	O
for	O
the	O
memory	B-General_Concept
controller	I-General_Concept
and	O
gives	O
equal	O
performance	O
in	O
completely	O
random	O
access	O
scenarios	O
,	O
when	O
compared	O
to	O
performance	O
levels	O
achieved	O
through	O
interleaving	O
.	O
</s>
<s>
However	O
,	O
in	O
reality	O
memory	O
reads	O
are	O
rarely	O
random	O
due	O
to	O
locality	B-General_Concept
of	I-General_Concept
reference	I-General_Concept
,	O
and	O
optimizing	O
for	O
close	O
together	O
access	O
gives	O
far	O
better	O
performance	O
in	O
interleaved	O
layouts	O
.	O
</s>
<s>
The	O
way	O
memory	O
is	O
addressed	O
has	O
no	O
effect	O
on	O
the	O
access	O
time	O
for	O
memory	O
locations	O
which	O
are	O
already	O
cached	B-General_Concept
,	O
having	O
an	O
impact	O
only	O
on	O
memory	O
locations	O
which	O
need	O
to	O
be	O
retrieved	O
from	O
DRAM	O
.	O
</s>
<s>
Early	O
research	O
into	O
interleaved	B-General_Concept
memory	I-General_Concept
was	O
performed	O
at	O
IBM	O
in	O
the	O
60s	O
and	O
70s	O
in	O
relation	O
to	O
the	O
IBM	B-Device
7030	I-Device
Stretch	I-Device
computer	O
,	O
but	O
development	O
went	O
on	O
for	O
decades	O
improving	O
design	O
,	O
flexibility	O
and	O
performance	O
to	O
produce	O
modern	O
implementations	O
.	O
</s>
