<s>
The	O
interconnect	B-Protocol
bottleneck	I-Protocol
comprises	O
limits	O
on	O
integrated	O
circuit	O
(	O
IC	O
)	O
performance	O
due	O
to	O
connections	O
between	O
components	O
instead	O
of	O
their	O
internal	O
speed	O
.	O
</s>
<s>
This	O
allows	O
the	O
basic	O
IC	O
building	O
block	O
,	O
the	O
transistor	B-Application
,	O
to	O
operate	O
at	O
a	O
higher	O
frequency	O
,	O
performing	O
more	O
computations	O
per	O
second	O
.	O
</s>
<s>
However	O
,	O
downscaling	O
of	O
the	O
minimum	O
feature	O
size	O
also	O
results	O
in	O
tighter	O
packing	O
of	O
the	O
wires	O
on	O
a	O
microprocessor	B-Architecture
,	O
which	O
increases	O
parasitic	O
capacitance	O
and	O
signal	O
propagation	O
delay	O
.	O
</s>
<s>
This	O
phenomenon	O
,	O
known	O
as	O
an	O
“	O
interconnect	B-Protocol
bottleneck	I-Protocol
”	O
,	O
is	O
becoming	O
a	O
major	O
problem	O
in	O
high-performance	O
computer	O
systems	O
.	O
</s>
<s>
This	O
interconnect	B-Protocol
bottleneck	I-Protocol
can	O
be	O
solved	O
by	O
utilizing	O
optical	O
interconnects	B-General_Concept
to	O
replace	O
the	O
long	O
metallic	O
interconnects	B-General_Concept
.	O
</s>
<s>
Such	O
hybrid	O
optical/electronic	O
interconnects	B-General_Concept
promise	O
better	O
performance	O
even	O
with	O
larger	O
designs	O
.	O
</s>
