<s>
Intel	O
's	O
i960	B-General_Concept
(	O
or	O
80960	B-General_Concept
)	O
was	O
a	O
RISC-based	B-Architecture
microprocessor	B-Architecture
design	O
that	O
became	O
popular	O
during	O
the	O
early	O
1990s	O
as	O
an	O
embedded	B-Architecture
microcontroller	B-Architecture
.	O
</s>
<s>
It	O
became	O
a	O
best-selling	O
CPU	O
in	O
that	O
segment	O
,	O
along	O
with	O
the	O
competing	O
AMD	B-General_Concept
29000	I-General_Concept
.	O
</s>
<s>
In	O
spite	O
of	O
its	O
success	O
,	O
Intel	O
stopped	O
marketing	O
the	O
i960	B-General_Concept
in	O
the	O
late	O
1990s	O
,	O
as	O
a	O
result	O
of	O
a	O
settlement	O
with	O
DEC	O
whereby	O
Intel	O
received	O
the	O
rights	O
to	O
produce	O
the	O
StrongARM	B-Device
CPU	O
.	O
</s>
<s>
The	O
i960	B-General_Concept
design	O
was	O
begun	O
in	O
response	O
to	O
the	O
failure	O
of	O
Intel	O
's	O
iAPX	B-Device
432	I-Device
design	O
of	O
the	O
early	O
1980s	O
.	O
</s>
<s>
The	O
iAPX	B-Device
432	I-Device
was	O
intended	O
to	O
directly	O
support	O
high-level	O
languages	O
that	O
supported	O
tagged	B-Architecture
,	O
protected	B-General_Concept
,	O
garbage-collected	B-General_Concept
memory	O
—	O
such	O
as	O
Ada	B-Language
and	O
Lisp	B-Language
—	O
in	O
hardware	O
.	O
</s>
<s>
Because	O
of	O
its	O
instruction-set	O
complexity	O
,	O
its	O
multi-chip	O
implementation	O
,	O
and	O
design	O
flaws	O
,	O
the	O
iAPX	B-Device
432	I-Device
was	O
very	O
slow	O
in	O
comparison	O
to	O
other	O
processors	O
of	O
its	O
time	O
.	O
</s>
<s>
In	O
1984	O
,	O
Intel	O
and	O
Siemens	O
started	O
a	O
joint	O
project	O
,	O
ultimately	O
called	O
BiiN	O
,	O
to	O
create	O
a	O
high-end	O
,	O
fault-tolerant	B-General_Concept
,	O
object-oriented	O
computer	O
system	O
programmed	O
entirely	O
in	O
Ada	B-Language
.	O
</s>
<s>
Many	O
of	O
the	O
original	O
i432	B-Device
team	O
members	O
joined	O
this	O
project	O
,	O
although	O
a	O
new	O
lead	O
architect	O
,	O
Glenford	O
Myers	O
,	O
was	O
brought	O
in	O
from	O
IBM	O
.	O
</s>
<s>
Intel	O
's	O
major	O
contribution	O
to	O
the	O
BiiN	O
system	O
was	O
a	O
new	O
processor	O
design	O
,	O
influenced	O
by	O
the	O
protected-memory	O
concepts	O
from	O
the	O
i432	B-Device
.	O
</s>
<s>
The	O
new	O
design	O
was	O
to	O
include	O
a	O
number	O
of	O
features	O
to	O
improve	O
performance	O
and	O
avoid	O
problems	O
that	O
had	O
led	O
to	O
the	O
i432	B-Device
's	O
downfall	O
.	O
</s>
<s>
He	O
tried	O
to	O
convince	O
Intel	O
management	O
to	O
market	O
the	O
i960	B-General_Concept
(	O
then	O
still	O
known	O
as	O
the	O
"	O
P7	O
"	O
)	O
as	O
a	O
general-purpose	O
processor	O
,	O
both	O
in	O
place	O
of	O
the	O
Intel	B-General_Concept
80286	I-General_Concept
and	O
i386	B-General_Concept
(	O
which	O
taped-out	O
the	O
same	O
month	O
as	O
the	O
first	O
i960	B-General_Concept
)	O
,	O
as	O
well	O
as	O
the	O
emerging	O
RISC	B-Architecture
market	O
for	O
Unix	B-Application
systems	I-Application
,	O
including	O
a	O
pitch	O
to	O
Steve	O
Jobs	O
for	O
use	O
in	O
the	O
NeXT	O
system	O
.	O
</s>
<s>
Competition	O
within	O
and	O
outside	O
of	O
Intel	O
came	O
not	O
only	O
from	O
the	O
i386	B-General_Concept
camp	O
but	O
also	O
from	O
the	O
i860	B-General_Concept
processor	O
,	O
yet	O
another	O
RISC	B-Architecture
processor	I-Architecture
design	O
emerging	O
within	O
Intel	O
at	O
the	O
time	O
.	O
</s>
<s>
Myers	O
was	O
unsuccessful	O
at	O
convincing	O
Intel	O
management	O
to	O
support	O
the	O
i960	B-General_Concept
as	O
a	O
general-purpose	O
or	O
Unix	B-Application
processor	O
,	O
but	O
the	O
chip	O
found	O
a	O
ready	O
market	O
in	O
early	O
high-performance	O
32-bit	O
embedded	B-Architecture
systems	I-Architecture
.	O
</s>
<s>
The	O
lead	O
architect	O
of	O
i960	B-General_Concept
was	O
superscalarity	O
specialist	O
Fred	O
Pollack	O
who	O
was	O
also	O
the	O
lead	O
engineer	O
of	O
the	O
Intel	B-Device
iAPX	I-Device
432	I-Device
and	O
the	O
lead	O
architect	O
of	O
the	O
i686	O
chip	O
,	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
To	O
avoid	O
the	O
performance	O
issues	O
that	O
plagued	O
the	O
i432	B-Device
,	O
the	O
central	O
i960	B-General_Concept
instruction-set	O
architecture	O
was	O
a	O
RISC	B-Architecture
design	O
,	O
which	O
was	O
only	O
implemented	O
in	O
full	O
in	O
the	O
i960MX	O
.	O
</s>
<s>
The	O
memory	O
subsystem	O
was	O
33-bits	O
wide	O
—	O
to	O
accommodate	O
a	O
32-bit	O
word	O
and	O
a	O
"	O
tag	O
"	O
bit	O
to	O
implement	O
memory	B-General_Concept
protection	I-General_Concept
in	O
hardware	O
.	O
</s>
<s>
In	O
many	O
ways	O
,	O
the	O
i960	B-General_Concept
followed	O
the	O
original	O
Berkeley	B-General_Concept
RISC	I-General_Concept
design	O
,	O
notably	O
in	O
its	O
use	O
of	O
register	B-General_Concept
windows	I-General_Concept
,	O
an	O
implementation-specific	O
number	O
of	O
caches	O
for	O
the	O
per-subroutine	O
registers	O
that	O
allowed	O
for	O
fast	O
subroutine	O
calls	O
.	O
</s>
<s>
The	O
competing	O
Stanford	O
University	O
design	O
,	O
MIPS	B-General_Concept
,	O
did	O
not	O
use	O
this	O
system	O
,	O
instead	O
relying	O
on	O
the	O
compiler	O
to	O
generate	O
optimal	O
subroutine	O
call	O
and	O
return	O
code	O
.	O
</s>
<s>
In	O
common	O
with	O
most	O
32-bit	O
designs	O
,	O
the	O
i960	B-General_Concept
has	O
a	O
flat	O
32-bit	O
memory	O
space	O
,	O
with	O
no	O
memory	B-General_Concept
segmentation	I-General_Concept
,	O
except	O
for	O
the	O
i960MX	O
,	O
which	O
could	O
support	O
up	O
to	O
226	O
"	O
objects	O
"	O
,	O
each	O
up	O
to	O
232	O
bytes	O
in	O
size	O
.	O
</s>
<s>
The	O
i960	B-General_Concept
architecture	O
also	O
anticipated	O
a	O
superscalar	B-General_Concept
implementation	O
,	O
with	O
instructions	O
being	O
simultaneously	O
dispatched	O
to	O
more	O
than	O
one	O
unit	O
within	O
the	O
processor	O
.	O
</s>
<s>
It	O
contains	O
32	O
of	O
32-bit	O
register	O
,	O
a	O
512	O
byte	O
of	O
instruction	O
cache	O
,	O
a	O
stack	O
frame	O
cache	O
,	O
a	O
high	O
speed	O
32-bit	O
multiplexed	B-General_Concept
burst	I-General_Concept
bus	I-General_Concept
,	O
and	O
an	O
interrupt	O
controller	O
.	O
</s>
<s>
The	O
"	O
full	O
"	O
i960MX	O
was	O
never	O
released	O
for	O
the	O
non-military	O
market	O
,	O
but	O
the	O
otherwise	O
identical	O
i960MC	O
was	O
used	O
in	O
high-end	O
embedded	B-Architecture
applications	O
.	O
</s>
<s>
Later	O
iterations	O
of	O
the	O
i960	B-General_Concept
,	O
like	O
the	O
80960Jx	O
series	O
,	O
have	O
a	O
more	O
typical	O
number	O
of	O
"	O
do	O
no	O
connect	O
"	O
and	O
use	O
more	O
power	O
and	O
ground	O
pins	O
and	O
have	O
additional	O
I/O	O
pins	O
instead	O
.	O
</s>
<s>
The	O
80960MC	O
does	O
contains	O
on-chip	O
memory	B-General_Concept
management	I-General_Concept
unit	I-General_Concept
and	O
supports	O
fault	B-General_Concept
tolerant	I-General_Concept
system	I-General_Concept
.	O
</s>
<s>
A	O
version	O
of	O
the	O
RISC	B-Architecture
core	O
without	O
memory	O
management	O
or	O
an	O
FPU	B-General_Concept
became	O
the	O
i960KA	O
,	O
and	O
the	O
RISC	B-Architecture
core	O
with	O
an	O
FPU	B-General_Concept
became	O
the	O
i960KB	O
.	O
</s>
<s>
These	O
processors	O
can	O
perform	O
around	O
7.5	O
VAX	O
MIPS	B-General_Concept
.	O
</s>
<s>
Both	O
processors	O
are	O
packaged	O
in	O
132-PGA	B-Algorithm
.	O
</s>
<s>
The	O
i960KA	O
became	O
successful	O
as	O
a	O
low-cost	O
32-bit	O
processor	O
for	O
the	O
laser-printer	O
market	O
,	O
as	O
well	O
as	O
for	O
early	O
graphics	O
terminals	O
and	O
other	O
embedded	B-Architecture
applications	O
.	O
</s>
<s>
The	O
i960CA	O
,	O
first	O
announced	O
in	O
July	O
1989	O
,	O
was	O
the	O
first	O
pure	O
RISC	B-Architecture
implementation	O
of	O
the	O
i960	B-General_Concept
architecture	O
.	O
</s>
<s>
It	O
featured	O
a	O
newly	O
designed	O
superscalar	B-General_Concept
RISC	B-Architecture
core	O
and	O
added	O
an	O
unusual	O
addressable	O
on-chip	O
cache	O
,	O
but	O
lacked	O
an	O
FPU	B-General_Concept
and	O
MMU	O
,	O
as	O
it	O
was	O
intended	O
for	O
high-performance	O
embedded	B-Architecture
applications	O
.	O
</s>
<s>
The	O
i960CA	O
is	O
widely	O
considered	O
to	O
have	O
been	O
the	O
first	O
single-chip	O
superscalar	B-General_Concept
RISC	B-Architecture
implementation	O
.	O
</s>
<s>
The	O
first	O
versions	O
released	O
ran	O
at	O
33MHz	O
,	O
and	O
Intel	O
promoted	O
the	O
chip	O
as	O
capable	O
of	O
66	O
MIPS	B-General_Concept
.	O
</s>
<s>
Later	O
,	O
in	O
May	O
1992	O
,	O
came	O
the	O
i960CF	O
,	O
which	O
included	O
a	O
larger	O
instruction	O
cache	O
(	O
4	O
KB	O
instead	O
of	O
1	O
KB	O
)	O
and	O
added	O
1	O
KB	O
of	O
data	O
cache	O
,	O
but	O
was	O
still	O
without	O
an	O
FPU	B-General_Concept
or	O
MMU	O
.	O
</s>
<s>
The	O
80960Jx	O
is	O
a	O
processor	O
for	O
embedded	B-Architecture
applications	O
.	O
</s>
<s>
Announced	O
in	O
October	O
1998	O
,	O
the	O
i960VH	O
Embedded-PCI	O
processor	O
featured	O
a	O
32-bit	O
33MHz	O
PCI	B-Protocol
bus	I-Protocol
and	O
100MHz	O
i960JT	O
processor	O
core	O
.	O
</s>
<s>
Other	O
core	O
features	O
included	O
two	O
32-bit	O
timers	O
,	O
programmable	O
interrupt	O
controller	O
,	O
I²C	O
interface	O
,	O
and	O
a	O
two-channel	O
DMA	B-General_Concept
controller	I-General_Concept
.	O
</s>
<s>
The	O
80960Rx	O
processors	O
were	O
labeled	O
as	O
I/O	O
Processors	O
and	O
included	O
an	O
implementation	O
of	O
the	O
PCI	B-Protocol
Bus	I-Protocol
(	O
2.1	O
or	O
2.2	O
depending	O
on	O
the	O
variant	O
)	O
as	O
well	O
as	O
a	O
80960Jx	O
core	O
.	O
</s>
<s>
These	O
could	O
be	O
used	O
on	O
motherboards	O
to	O
implement	O
on-board	O
PCI	B-Protocol
device	O
as	O
well	O
as	O
on	O
PCI	B-Protocol
expansion	O
cards	O
.	O
</s>
<s>
Intel	O
attempted	O
to	O
bolster	O
the	O
i960	B-General_Concept
in	O
the	O
I/O	O
device	O
controller	O
market	O
with	O
the	O
I2O	B-General_Concept
standard	O
,	O
but	O
this	O
had	O
little	O
success	O
and	O
the	O
design	O
work	O
was	O
eventually	O
ended	O
.	O
</s>
<s>
In	O
1990	O
,	O
the	O
i960	B-General_Concept
team	O
was	O
redirected	O
to	O
be	O
the	O
"	O
second	O
team	O
"	O
working	O
in	O
parallel	O
on	O
future	O
i386	B-General_Concept
implementations	O
—	O
specifically	O
the	O
P6	O
processor	O
,	O
which	O
later	O
became	O
the	O
Pentium	B-Device
Pro	I-Device
.	O
</s>
<s>
The	O
i960	B-General_Concept
project	O
was	O
given	O
to	O
another	O
smaller	O
development	O
team	O
,	O
essentially	O
ensuring	O
the	O
end	O
of	O
its	O
developmental	O
life	O
.	O
</s>
<s>
Because	O
of	O
its	O
high	O
performance	O
in	O
calculating	O
XOR	B-Application
values	O
,	O
i960	B-General_Concept
processors	O
,	O
such	O
as	O
the	O
80303	O
,	O
are	O
often	O
used	O
in	O
controllers	O
for	O
higher-end	O
,	O
RAID-capable	O
,	O
SCSI-disk-array	O
,	O
host-adapter	O
cards	O
as	O
well	O
as	O
Digital	O
Equipment/Compaq/HP	O
'	O
s	O
high-end	O
SCSI	B-Architecture
and	O
DSSI	B-Architecture
,	O
and	O
eventually	O
Fibre	B-Architecture
Channel	I-Architecture
HSx-series	O
,	O
standalone	O
RAID	B-Architecture
controllers	O
.	O
</s>
<s>
An	O
i960RS	O
chip	O
also	O
powers	O
Adaptec	O
's	O
AAR-2400A	O
controller	O
,	O
which	O
uses	O
four	O
commodity	O
parallel	B-Protocol
ATA	I-Protocol
drives	O
to	O
build	O
an	O
affordable	O
RAID-5	B-General_Concept
protected	B-General_Concept
fault-tolerant	B-General_Concept
storage	O
system	O
for	O
small	O
PC	O
servers	O
and	O
workstations	O
.	O
</s>
<s>
The	O
i960	B-General_Concept
was	O
also	O
used	O
in	O
some	O
Brocade	O
Fibre	B-Architecture
Channel	I-Architecture
switches	O
to	O
run	O
Fabric	B-Protocol
OS	I-Protocol
.	O
</s>
<s>
The	O
i960	B-General_Concept
architecture	O
is	O
also	O
used	O
in	O
slot	O
machines	O
.	O
</s>
<s>
Currently	O
,	O
they	O
are	O
found	O
in	O
IGT	O
's	O
Stepper	O
S2000	O
family	O
and	O
i960	B-General_Concept
video	O
family	O
.	O
</s>
<s>
The	O
Indian	O
Air	O
Force	O
's	O
HAL	O
Tejas	O
light	O
combat	O
aircraft	O
's	O
MMR	O
(	O
multi-mode	O
radar	B-Application
)	O
is	O
said	O
to	O
use	O
the	O
i960	B-General_Concept
.	O
</s>
<s>
The	O
i960	B-General_Concept
processor	O
is	O
also	O
used	O
in	O
Automatic	B-Algorithm
Radar	I-Algorithm
Plotting	I-Algorithm
Aid	I-Algorithm
(	O
ARPA	O
)	O
interfacing	O
boards	O
in	O
radars	B-Application
from	O
Kelvin	O
Hughes	O
.	O
</s>
<s>
The	O
chip	O
was	O
used	O
on	O
some	O
HP	B-Device
X-Terminals	I-Device
.	O
</s>
<s>
Some	O
SATA	O
RAID	B-Architecture
controllers	O
use	O
Intel	O
's	O
80303	O
IOP	O
(	O
Intelligent	O
I/O	O
Processor	O
)	O
,	O
which	O
integrates	O
a	O
PCI-to-PCI	O
bridge	O
,	O
memory	O
controller	O
,	O
and	O
a	O
80960JT-100	O
CPU	O
core	O
.	O
</s>
